1 From 7836f8aa56ef0f18c8658dc7e4952a9d097ba7e8 Mon Sep 17 00:00:00 2001
2 From: Zhenhua Luo <zhenhua.luo@nxp.com>
3 Date: Sat, 11 Jun 2016 22:08:29 -0500
4 Subject: [PATCH 11/17] fix the incorrect assembling for ppc wait mnemonic
6 Signed-off-by: Zhenhua Luo <zhenhua.luo@nxp.com>
8 Upstream-Status: Pending
10 opcodes/ppc-opc.c | 4 +---
11 1 file changed, 1 insertion(+), 3 deletions(-)
13 diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
14 index 5e20d617664..4c9656ecf08 100644
15 --- a/opcodes/ppc-opc.c
16 +++ b/opcodes/ppc-opc.c
17 @@ -6265,8 +6265,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
18 {"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}},
19 {"waitrsv", XWCPL(31,30,1,0),0xffffffff, POWER10, 0, {0}},
20 {"pause_short", XWCPL(31,30,2,0),0xffffffff, POWER10, 0, {0}},
21 -{"wait", X(31,30), XWCPL_MASK, POWER10, 0, {WC, PL}},
22 -{"wait", X(31,30), XWC_MASK, POWER9, POWER10, {WC}},
24 {"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
26 @@ -6326,7 +6324,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
28 {"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
29 {"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
30 -{"wait", X(31,62), XWC_MASK, E500MC|PPCA2, 0, {WC}},
31 +{"wait", X(31,62), XWC_MASK, E500MC|PPCA2|POWER9|POWER10, 0, {WC}},
33 {"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},