code.ossystems Code Review - openembedded-core.git/blob

   1 From f52838cd03de045aa67cc1a0c1614ea5bfb30fcc Mon Sep 17 00:00:00 2001
   2 From: Alan Olsen <alan.r.olsen@intel.com>
   3 Date: Wed, 11 Nov 2009 13:12:42 -0800
   4 Subject: [PATCH 065/104] Moorestown SPI Slave Controller driver v1.1 consolidation patch
   5
   6 This patch contains the following patches:
   7
   8 Alpha2-1.0-1-1-mrst-SPI-Slave-Core-Driver-K29.patch
   9
  10    [PATCH] SPI Slave Support Added to SPI Core Driver
  11
  12    Signed-off-by: Pranav K. Sanghadia <pranav.k.sanghadia@intel.com>
  13
  14 Alpha2-1.0-1-1-mrst-SPI-Slave-controller-driver.patch
  15
  16    [PATCH]     SPI slave controller driver for Moorestown platform
  17
  18    This driver currently supports only programmed IO mode.
  19
  20    Config settings are:
  21
  22         CONFIG_SPI_MRST_SLAVE=y
  23         CONFIG_SPI_MRST_SLAVE_DMA is not set
  24
  25    Signed-off-by: Ken Mills <ken.k.mills@intel.com>
  26
  27 Alpha2-1.0-1-1-DMA-Support-added-in-SPI-Slave-Controller-Driver.patch
  28
  29    [PATCH] This patch adds DMA support for SPI Slave Controller Driver. DMA provides
  30    highspeed data transfer between SPI-SSP and external Master mode device
  31
  32    Signed-off-by: Pranav K. Sanghadia <pranav.k.sanghadia@intel.com>
  33
  34 Alpha2-1.0-1-1-mrst-SPI-Slave-controller-fix-DMA-Issue.patch
  35
  36    [PATCH] Alpha2-1.0-1-1-mrst-SPI-Slave-controller-fix-DMA-Issue.patch
  37
  38 [PATCH] Optimized SSP clock bitbang routine
  39
  40 Signed-off-by: Ken Mills <ken.k.mills@intel.com>
  41
  42 Signed-off-by: Alan Olsen <alan.r.olsen@intel.com>
  43 ---
  44  drivers/spi/Kconfig                |   11 +
  45  drivers/spi/Makefile               |    1 +
  46  drivers/spi/mrst_spi_slave.c       | 1227 ++++++++++++++++++++++++++++++++++++
  47  drivers/spi/spi.c                  |  403 +++++++++++-
  48  include/linux/spi/mrst_spi_slave.h |  143 +++++
  49  include/linux/spi/spi.h            |   98 +++-
  50  6 files changed, 1862 insertions(+), 21 deletions(-)
  51  create mode 100644 drivers/spi/mrst_spi_slave.c
  52  create mode 100644 include/linux/spi/mrst_spi_slave.h
  53
  54 diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
  55 index 9d4ff53..b94445b 100644
  56 --- a/drivers/spi/Kconfig
  57 +++ b/drivers/spi/Kconfig
  58 @@ -360,5 +360,16 @@ config SPI_TLE62X0
  59  endif # SPI_MASTER
  60
  61  # (slave support would go here)
  62 +config SPI_MRST_SLAVE
  63 +          tristate "SPI slave controller driver for Intel Moorestown platform "
  64 +          depends on SPI_MASTER
  65 +          help
  66 +            This is the SPI slave controller driver for Intel Moorestown platform
  67 +
  68 +config SPI_MRST_SLAVE_DMA
  69 +          boolean "Enable DMA for MRST SPI Slave Controller"
  70 +          depends on INTEL_LNW_DMAC1
  71 +          help
  72 +            This has to be enabled after Moorestown DMAC1 driver is enabled
  73
  74  endif # SPI
  75 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
  76 index c78cb77..8acdd96 100644
  77 --- a/drivers/spi/Makefile
  78 +++ b/drivers/spi/Makefile
  79 @@ -56,6 +56,7 @@ obj-$(CONFIG_SPI_TLE62X0)     += tle62x0.o
  80  #      ... add above this line ...
  81
  82  # SPI slave controller drivers (upstream link)
  83 +obj-$(CONFIG_SPI_MRST_SLAVE)                  += mrst_spi_slave.o
  84  #      ... add above this line ...
  85
  86  # SPI slave drivers (protocol for that link)
  87 diff --git a/drivers/spi/mrst_spi_slave.c b/drivers/spi/mrst_spi_slave.c
  88 new file mode 100644
  89 index 0000000..82a50b7
  90 --- /dev/null
  91 +++ b/drivers/spi/mrst_spi_slave.c
  92 @@ -0,0 +1,1227 @@
  93 +/*
  94 + *  mrst_spi_slave.c - Moorestown SPI slave controller driver
  95 + *  based on pxa2xx_spi.c
  96 + *
  97 + *  Copyright (C) Intel 2009
  98 + *  Ken Mills <ken.k.mills@intel.com>
  99 + *
 100 + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 101 + *
 102 + *  This program is free software; you can redistribute it and/or modify
 103 + *  it under the terms of the GNU General Public License as published by
 104 + *  the Free Software Foundation; either version 2 of the License, or
 105 + *  (at your option) any later version.
 106 + *
 107 + *  This program is distributed in the hope that it will be useful,
 108 + *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 109 + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 110 + *  GNU General Public License for more details.
 111 + *
 112 + *  You should have received a copy of the GNU General Public License
 113 + *  along with this program; if not, write to the Free Software
 114 + *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 115 + *
 116 + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 117 + *
 118 + */
 119 +
 120 +/*
 121 + * Note:
 122 + *
 123 + * Supports interrupt programmed I/O, DMA and non-interrupt polled transfers.
 124 + *
 125 + */
 126 +
 127 +#include <linux/delay.h>
 128 +#include <linux/highmem.h>
 129 +#include <linux/pci.h>
 130 +#include <linux/interrupt.h>
 131 +
 132 +#ifdef CONFIG_SPI_MRST_SLAVE_DMA
 133 +#include <linux/dma-mapping.h>
 134 +#include <linux/lnw_dma.h>
 135 +#endif
 136 +
 137 +#include <linux/spi/spi.h>
 138 +#include <linux/spi/mrst_spi_slave.h>
 139 +
 140 +
 141 +#define DRIVER_NAME "mrst_spi_slave"
 142 +
 143 +#define SSP_NOT_SYNC 0x400000
 144 +
 145 +MODULE_AUTHOR("");
 146 +MODULE_DESCRIPTION("Moorestown SPI Slave Contoller");
 147 +MODULE_LICENSE("GPL");
 148 +
 149 +/*
 150 + * For testing SSCR1 changes that require SSP restart, basically
 151 + * everything except the service and interrupt enables
 152 + */
 153 +#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_EBCEI | SSCR1_SCFR \
 154 +                                              | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
 155 +                                              | SSCR1_SFRMDIR \
 156 +                                              | SSCR1_RWOT | SSCR1_TRAIL | SSCR1_PINTE \
 157 +                                              | SSCR1_STRF | SSCR1_EFWR | SSCR1_RFT \
 158 +                                              | SSCR1_TFT | SSCR1_SPH | SSCR1_SPO)
 159 +
 160 +#define DEFINE_SSP_REG(reg, off) \
 161 +static inline u32 read_##reg(void *p) { return __raw_readl(p + (off)); } \
 162 +static inline void write_##reg(u32 v, void *p) { __raw_writel(v, p + (off)); }
 163 +
 164 +DEFINE_SSP_REG(SSCR0, 0x00)
 165 +DEFINE_SSP_REG(SSCR1, 0x04)
 166 +DEFINE_SSP_REG(SSSR, 0x08)
 167 +DEFINE_SSP_REG(SSITR, 0x0c)
 168 +DEFINE_SSP_REG(SSDR, 0x10)
 169 +DEFINE_SSP_REG(SSTO, 0x28)
 170 +DEFINE_SSP_REG(SSPSP, 0x2c)
 171 +
 172 +DEFINE_SSP_REG(IPCCSR, 0x00);
 173 +DEFINE_SSP_REG(IPCPISR, 0x08);
 174 +DEFINE_SSP_REG(IPCPIMR, 0x10);
 175 +
 176 +DEFINE_SSP_REG(I2CCTRL, 0x00);
 177 +DEFINE_SSP_REG(I2CDATA, 0x04);
 178 +
 179 +DEFINE_SSP_REG(GPLR1, 0x04);
 180 +DEFINE_SSP_REG(GPDR1, 0x0c);
 181 +DEFINE_SSP_REG(GPSR1, 0x14);
 182 +DEFINE_SSP_REG(GPCR1, 0x1C);
 183 +DEFINE_SSP_REG(GAFR1_U, 0x44);
 184 +
 185 +#define START_STATE ((void *)0)
 186 +#define RUNNING_STATE ((void *)1)
 187 +#define DONE_STATE ((void *)2)
 188 +#define ERROR_STATE ((void *)-1)
 189 +
 190 +struct driver_data {
 191 +          /* Driver model hookup */
 192 +          struct pci_dev *pdev;
 193 +
 194 +          /* SPI framework hookup */
 195 +          struct spi_slave *slave;
 196 +
 197 +          /* SSP register addresses */
 198 +          void *paddr;
 199 +          void *ioaddr;
 200 +          u32 iolen;
 201 +          int irq;
 202 +
 203 +          /* IPC registers */
 204 +          void *IPC_paddr;
 205 +          void *IPC_ioaddr;
 206 +
 207 +          /* I2C registers */
 208 +          void *I2C_paddr;
 209 +          void *I2C_ioaddr;
 210 +
 211 +          /* SSP masks*/
 212 +          u32 dma_cr1;
 213 +          u32 int_cr1;
 214 +          u32 clear_sr;
 215 +          u32 mask_sr;
 216 +
 217 +          struct tasklet_struct poll_transfer;
 218 +
 219 +          spinlock_t lock;
 220 +          int busy;
 221 +          int run;
 222 +
 223 +          /* Current message transfer state info */
 224 +          struct spi_message *cur_msg;
 225 +          size_t len;
 226 +          void *tx;
 227 +          void *tx_end;
 228 +          void *rx;
 229 +          void *rx_end;
 230 +          int dma_mapped;
 231 +          dma_addr_t rx_dma;
 232 +          dma_addr_t tx_dma;
 233 +          size_t rx_map_len;
 234 +          size_t tx_map_len;
 235 +          u8 n_bytes;
 236 +          int (*write)(struct driver_data *drv_data);
 237 +          int (*read)(struct driver_data *drv_data);
 238 +          irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
 239 +          void (*cs_control)(u32 command);
 240 +
 241 +#ifdef CONFIG_SPI_MRST_SLAVE_DMA
 242 +          struct lnw_dma_slave    dmas_tx;
 243 +          struct lnw_dma_slave    dmas_rx;
 244 +          struct dma_chan                        *txchan;
 245 +          struct dma_chan                        *rxchan;
 246 +
 247 +          int txdma_done;
 248 +          int rxdma_done;
 249 +       u64 tx_param;
 250 +       u64 rx_param;
 251 +       struct pci_dev *dmac1;
 252 +#endif
 253 +};
 254 +
 255 +struct chip_data {
 256 +          u32 cr0;
 257 +          u32 cr1;
 258 +          u32 psp;
 259 +          u32 timeout;
 260 +          u8 n_bytes;
 261 +          u32 threshold;
 262 +          u8 enable_dma;
 263 +          u8 poll_mode;               /* 1 means use poll mode */
 264 +          u8 bits_per_word;
 265 +          int (*write)(struct driver_data *drv_data);
 266 +          int (*read)(struct driver_data *drv_data);
 267 +};
 268 +
 269 +static void flush(struct driver_data *drv_data)
 270 +{
 271 +          void *reg = drv_data->ioaddr;
 272 +          u32 sssr;
 273 +
 274 +          /* If the transmit fifo is not empty, reset the interface. */
 275 +          sssr = read_SSSR(reg);
 276 +          if ((sssr & 0xf00) || (sssr & SSSR_TNF) == 0) {
 277 +                      write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
 278 +                      return;
 279 +          }
 280 +
 281 +          while (read_SSSR(reg) & SSSR_RNE)
 282 +                      read_SSDR(reg);
 283 +
 284 +          write_SSSR(SSSR_ROR, reg);
 285 +          write_SSSR(SSSR_TUR, reg);
 286 +
 287 +          return;
 288 +}
 289 +
 290 +static int null_writer(struct driver_data *drv_data)
 291 +{
 292 +          void *reg = drv_data->ioaddr;
 293 +          u8 n_bytes = drv_data->n_bytes;
 294 +
 295 +          if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
 296 +                      || (drv_data->tx == drv_data->tx_end))
 297 +                      return 0;
 298 +
 299 +          write_SSDR(0, reg);
 300 +          drv_data->tx += n_bytes;
 301 +
 302 +          return 1;
 303 +}
 304 +
 305 +static int null_reader(struct driver_data *drv_data)
 306 +{
 307 +          void *reg = drv_data->ioaddr;
 308 +          u8 n_bytes = drv_data->n_bytes;
 309 +
 310 +          while ((read_SSSR(reg) & SSSR_RNE)
 311 +                      && (drv_data->rx < drv_data->rx_end)) {
 312 +                      read_SSDR(reg);
 313 +                      drv_data->rx += n_bytes;
 314 +          }
 315 +
 316 +          return drv_data->rx == drv_data->rx_end;
 317 +}
 318 +
 319 +static int u8_writer(struct driver_data *drv_data)
 320 +{
 321 +          void *reg = drv_data->ioaddr;
 322 +          if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
 323 +                      || (drv_data->tx == drv_data->tx_end))
 324 +                      return 0;
 325 +
 326 +          write_SSDR(*(u8 *)(drv_data->tx), reg);
 327 +          ++drv_data->tx;
 328 +
 329 +          return 1;
 330 +}
 331 +
 332 +static int u8_reader(struct driver_data *drv_data)
 333 +{
 334 +          void *reg = drv_data->ioaddr;
 335 +          while ((read_SSSR(reg) & SSSR_RNE)
 336 +                      && (drv_data->rx < drv_data->rx_end)) {
 337 +                      *(u8 *)(drv_data->rx) = read_SSDR(reg);
 338 +                      ++drv_data->rx;
 339 +          }
 340 +
 341 +          return drv_data->rx == drv_data->rx_end;
 342 +}
 343 +
 344 +static int u16_writer(struct driver_data *drv_data)
 345 +{
 346 +          void *reg = drv_data->ioaddr;
 347 +          if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
 348 +                      || (drv_data->tx == drv_data->tx_end))
 349 +                      return 0;
 350 +
 351 +          write_SSDR(*(u16 *)(drv_data->tx), reg);
 352 +          drv_data->tx += 2;
 353 +
 354 +          return 1;
 355 +}
 356 +
 357 +static int u16_reader(struct driver_data *drv_data)
 358 +{
 359 +          void *reg = drv_data->ioaddr;
 360 +          while ((read_SSSR(reg) & SSSR_RNE)
 361 +                      && (drv_data->rx < drv_data->rx_end)) {
 362 +                      *(u16 *)(drv_data->rx) = read_SSDR(reg);
 363 +                      drv_data->rx += 2;
 364 +          }
 365 +
 366 +          return drv_data->rx == drv_data->rx_end;
 367 +}
 368 +
 369 +static int u32_writer(struct driver_data *drv_data)
 370 +{
 371 +          void *reg = drv_data->ioaddr;
 372 +          if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
 373 +                      || (drv_data->tx == drv_data->tx_end))
 374 +                      return 0;
 375 +
 376 +          write_SSDR(*(u32 *)(drv_data->tx), reg);
 377 +          drv_data->tx += 4;
 378 +
 379 +          return 1;
 380 +}
 381 +
 382 +static int u32_reader(struct driver_data *drv_data)
 383 +{
 384 +          void *reg = drv_data->ioaddr;
 385 +          while ((read_SSSR(reg) & SSSR_RNE)
 386 +                      && (drv_data->rx < drv_data->rx_end)) {
 387 +                      *(u32 *)(drv_data->rx) = read_SSDR(reg);
 388 +                      drv_data->rx += 4;
 389 +          }
 390 +
 391 +          return drv_data->rx == drv_data->rx_end;
 392 +}
 393 +
 394 +
 395 +
 396 +/* caller already set message->status; dma and pio irqs are blocked */
 397 +static void giveback(struct driver_data *drv_data)
 398 +{
 399 +          struct spi_message *msg;
 400 +
 401 +          msg = drv_data->cur_msg;
 402 +          msg->state = NULL;
 403 +          if (msg->complete)
 404 +                      msg->complete(msg->context);
 405 +}
 406 +
 407 +#ifdef CONFIG_SPI_MRST_SLAVE_DMA
 408 +
 409 +static bool chan_filter(struct dma_chan *chan, void *param)
 410 +{
 411 +          struct driver_data *drv_data = (struct driver_data *)param;
 412 +          bool ret = false;
 413 +
 414 +          if (!drv_data->dmac1)
 415 +                      return ret;
 416 +
 417 +          if (chan->device->dev == &drv_data->dmac1->dev)
 418 +                      ret = true;
 419 +
 420 +          return ret;
 421 +}
 422 +
 423 +static void int_transfer_complete(struct driver_data *drv_data);
 424 +
 425 +static void mrst_spi_dma_done(void *arg)
 426 +{
 427 +          u64 *param = arg;
 428 +          struct driver_data *drv_data;
 429 +       int *done;
 430 +
 431 +          drv_data = (struct driver_data *)(u32)(*param >> 32);
 432 +       done = (int *)(u32)(*param & 0xffffffff);
 433 +       *done = 1;
 434 +
 435 +       if (!drv_data->txdma_done || !drv_data->rxdma_done)
 436 +               return;
 437 +       int_transfer_complete(drv_data);
 438 +}
 439 +
 440 +static void mrst_spi_dma_init(struct driver_data *drv_data)
 441 +{
 442 +          struct lnw_dma_slave *rxs, *txs;
 443 +          dma_cap_mask_t mask;
 444 +
 445 +       /* Use DMAC1 */
 446 +       drv_data->dmac1 = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0814, NULL);
 447 +       if (!drv_data->dmac1) {
 448 +               printk(KERN_WARNING "SPI Slave:Can't find DMAC1\n");
 449 +               return;
 450 +       }
 451 +
 452 +          /* 1. init rx channel */
 453 +          rxs = &drv_data->dmas_rx;
 454 +
 455 +          rxs->dirn = DMA_FROM_DEVICE;
 456 +       rxs->hs_mode = LNW_DMA_HW_HS;
 457 +          rxs->cfg_mode = LNW_DMA_PER_TO_MEM;
 458 +          rxs->src_width = LNW_DMA_WIDTH_16BIT;
 459 +       rxs->dst_width = LNW_DMA_WIDTH_32BIT;
 460 +       rxs->src_msize = LNW_DMA_MSIZE_8;
 461 +       rxs->dst_msize = LNW_DMA_MSIZE_8;
 462 +
 463 +
 464 +          dma_cap_zero(mask);
 465 +          dma_cap_set(DMA_MEMCPY, mask);
 466 +          dma_cap_set(DMA_SLAVE, mask);
 467 +
 468 +       drv_data->rxchan = dma_request_channel(mask, chan_filter, drv_data);
 469 +       if (!drv_data->rxchan)
 470 +               goto err_exit;
 471 +
 472 +          drv_data->rxchan->private = rxs;
 473 +
 474 +          /* 2. init tx channel */
 475 +          txs = &drv_data->dmas_tx;
 476 +
 477 +          txs->dirn = DMA_TO_DEVICE;
 478 +       txs->hs_mode = LNW_DMA_HW_HS;
 479 +          txs->cfg_mode = LNW_DMA_MEM_TO_PER;
 480 +       txs->src_width = LNW_DMA_WIDTH_32BIT;
 481 +          txs->dst_width = LNW_DMA_WIDTH_16BIT;
 482 +       txs->src_msize = LNW_DMA_MSIZE_8;
 483 +       txs->dst_msize = LNW_DMA_MSIZE_8;
 484 +
 485 +
 486 +          dma_cap_set(DMA_SLAVE, mask);
 487 +          dma_cap_set(DMA_MEMCPY, mask);
 488 +
 489 +       drv_data->txchan = dma_request_channel(mask, chan_filter, drv_data);
 490 +       if (!drv_data->txchan)
 491 +               goto free_rxchan;
 492 +       else
 493 +
 494 +          drv_data->txchan->private = txs;
 495 +
 496 +          /* set the dma done bit to 1 */
 497 +          drv_data->txdma_done = 1;
 498 +          drv_data->rxdma_done = 1;
 499 +
 500 +       drv_data->tx_param = ((u64)(u32)drv_data << 32)
 501 +                               | (u32)(&drv_data->txdma_done);
 502 +       drv_data->rx_param = ((u64)(u32)drv_data << 32)
 503 +                               | (u32)(&drv_data->rxdma_done);
 504 +          return;
 505 +
 506 +free_rxchan:
 507 +       printk(KERN_ERR "SPI-Slave Error : DMA Channle Not available\n");
 508 +          dma_release_channel(drv_data->rxchan);
 509 +err_exit:
 510 +       printk(KERN_ERR "SPI-Slave Error : DMA Channel Not available\n");
 511 +       pci_dev_put(drv_data->dmac1);
 512 +          return;
 513 +}
 514 +
 515 +static void mrst_spi_dma_exit(struct driver_data *drv_data)
 516 +{
 517 +          dma_release_channel(drv_data->txchan);
 518 +          dma_release_channel(drv_data->rxchan);
 519 +       pci_dev_put(drv_data->dmac1);
 520 +}
 521 +
 522 +static void dma_transfer(struct driver_data *drv_data)
 523 +{
 524 +       dma_addr_t ssdr_addr;
 525 +          struct dma_async_tx_descriptor *txdesc = NULL, *rxdesc = NULL;
 526 +          struct dma_chan *txchan, *rxchan;
 527 +          enum dma_ctrl_flags flag;
 528 +
 529 +       /* get Data Read/Write address */
 530 +       ssdr_addr = (dma_addr_t)(u32)(drv_data->paddr + 0x10);
 531 +
 532 +          if (drv_data->tx_dma)
 533 +                      drv_data->txdma_done = 0;
 534 +
 535 +          if (drv_data->rx_dma)
 536 +                      drv_data->rxdma_done = 0;
 537 +
 538 +          /* 2. start the TX dma transfer */
 539 +          txchan = drv_data->txchan;
 540 +          rxchan = drv_data->rxchan;
 541 +
 542 +          flag = DMA_PREP_INTERRUPT | DMA_CTRL_ACK;
 543 +
 544 +       if (drv_data->rx_dma) {
 545 +               rxdesc = rxchan->device->device_prep_dma_memcpy
 546 +                               (rxchan,                /* DMA Channel */
 547 +                               drv_data->rx_dma,       /* DAR */
 548 +                               ssdr_addr,              /* SAR */
 549 +                               drv_data->len,  /* Data Length */
 550 +                               flag);          /* Flag */
 551 +
 552 +               rxdesc->callback = mrst_spi_dma_done;
 553 +               rxdesc->callback_param = &drv_data->rx_param;
 554 +          }
 555 +
 556 +          /* 3. start the RX dma transfer */
 557 +       if (drv_data->tx_dma) {
 558 +               txdesc = txchan->device->device_prep_dma_memcpy
 559 +                               (txchan,                /* DMA Channel */
 560 +                               ssdr_addr,              /* DAR */
 561 +                               drv_data->tx_dma,       /* SAR */
 562 +                               drv_data->len,  /* Data Length */
 563 +                               flag);          /* Flag */
 564 +
 565 +               txdesc->callback = mrst_spi_dma_done;
 566 +               txdesc->callback_param = &drv_data->tx_param;
 567 +          }
 568 +
 569 +          if (rxdesc)
 570 +                      rxdesc->tx_submit(rxdesc);
 571 +          if (txdesc)
 572 +                      txdesc->tx_submit(txdesc);
 573 +
 574 +}
 575 +
 576 +static int map_dma_buffers(struct driver_data *drv_data)
 577 +{
 578 +       drv_data->rx_dma = (dma_addr_t) virt_to_phys(drv_data->rx);
 579 +       drv_data->tx_dma = (dma_addr_t) virt_to_phys(drv_data->tx);
 580 +       return 1;
 581 +}
 582 +#endif
 583 +
 584 +static void int_error_stop(struct driver_data *drv_data, const char* msg)
 585 +{
 586 +          void *reg = drv_data->ioaddr;
 587 +
 588 +          /* Stop and reset SSP */
 589 +          write_SSSR(drv_data->clear_sr, reg);
 590 +          write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
 591 +          write_SSTO(0, reg);
 592 +          flush(drv_data);
 593 +
 594 +          dev_err(&drv_data->pdev->dev, "%s\n", msg);
 595 +
 596 +          drv_data->cur_msg->state = ERROR_STATE;
 597 +}
 598 +
 599 +static void int_transfer_complete(struct driver_data *drv_data)
 600 +{
 601 +          void *reg = drv_data->ioaddr;
 602 +
 603 +       /* Clear Status Register */
 604 +          write_SSSR(drv_data->clear_sr, reg);
 605 +
 606 +#ifdef CONFIG_SPI_MRST_SLAVE_DMA
 607 +       /* Disable Triggers to DMA */
 608 +          write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
 609 +#else
 610 +       /* Disable Interrupt */
 611 +          write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
 612 +#endif
 613 +       /* Stop getting Time Outs */
 614 +          write_SSTO(0, reg);
 615 +
 616 +          /* Update total byte transfered return count actual bytes read */
 617 +          drv_data->cur_msg->actual_length += drv_data->len -
 618 +                                              (drv_data->rx_end - drv_data->rx);
 619 +
 620 +          drv_data->cur_msg->status = 0;
 621 +          giveback(drv_data);
 622 +}
 623 +
 624 +static void transfer_complete(struct driver_data *drv_data)
 625 +{
 626 +          /* Update total byte transfered return count actual bytes read */
 627 +          drv_data->cur_msg->actual_length +=
 628 +                      drv_data->len - (drv_data->rx_end - drv_data->rx);
 629 +
 630 +          drv_data->cur_msg->status = 0;
 631 +          giveback(drv_data);
 632 +}
 633 +
 634 +static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
 635 +{
 636 +          void *reg = drv_data->ioaddr;
 637 +          u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
 638 +                                  drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
 639 +
 640 +          u32 irq_status = read_SSSR(reg) & irq_mask;
 641 +          if (irq_status & SSSR_ROR) {
 642 +                      int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
 643 +                      return IRQ_HANDLED;
 644 +          }
 645 +
 646 +          if (irq_status & SSSR_TINT) {
 647 +                      write_SSSR(SSSR_TINT, reg);
 648 +                      if (drv_data->read(drv_data)) {
 649 +                                  int_transfer_complete(drv_data);
 650 +                                  return IRQ_HANDLED;
 651 +                      }
 652 +          }
 653 +
 654 +          /* Drain rx fifo, Fill tx fifo and prevent overruns */
 655 +          do {
 656 +                      if (drv_data->read(drv_data)) {
 657 +                                  int_transfer_complete(drv_data);
 658 +                                  return IRQ_HANDLED;
 659 +                      }
 660 +          } while (drv_data->write(drv_data));
 661 +
 662 +          if (drv_data->read(drv_data)) {
 663 +                      int_transfer_complete(drv_data);
 664 +                      return IRQ_HANDLED;
 665 +          }
 666 +
 667 +          if (drv_data->tx == drv_data->tx_end)
 668 +                      write_SSCR1(read_SSCR1(reg) & ~SSCR1_TIE, reg);
 669 +
 670 +          return IRQ_HANDLED;
 671 +}
 672 +
 673 +static irqreturn_t ssp_int(int irq, void *dev_id)
 674 +{
 675 +          struct driver_data *drv_data = dev_id;
 676 +          void *reg = drv_data->ioaddr;
 677 +       u32 status = read_SSSR(reg);
 678 +
 679 + #ifdef CONFIG_SPI_MRST_SLAVE_DMA
 680 +       if (status & SSSR_ROR || status & SSSR_TUR) {
 681 +               printk(KERN_DEBUG "--- SPI ROR or TUR Occred : SSSR=%x\n", status);
 682 +               write_SSSR(SSSR_ROR, reg);              /* Clear ROR */
 683 +               write_SSSR(SSSR_TUR, reg);              /* Clear TUR */
 684 +               return IRQ_HANDLED;
 685 +       }
 686 +               return IRQ_NONE;
 687 + #endif
 688 +          /* just return if this is not our interrupt */
 689 +          if (!(read_SSSR(reg) & drv_data->mask_sr))
 690 +                      return IRQ_NONE;
 691 +
 692 +          if (!drv_data->cur_msg) {
 693 +                      write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
 694 +                      write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
 695 +                      write_SSSR(drv_data->clear_sr, reg);
 696 +
 697 +                      /* Never fail */
 698 +                      return IRQ_HANDLED;
 699 +          }
 700 +          return drv_data->transfer_handler(drv_data);
 701 +}
 702 +
 703 +static void poll_transfer(unsigned long data)
 704 +{
 705 +          struct driver_data *drv_data = (struct driver_data *)data;
 706 +
 707 +          if (drv_data->tx)
 708 +                      while (drv_data->tx != drv_data->tx_end) {
 709 +                                  drv_data->write(drv_data);
 710 +                                  drv_data->read(drv_data);
 711 +          }
 712 +
 713 +          while (!drv_data->read(drv_data))
 714 +                      ;
 715 +
 716 +          transfer_complete(drv_data);
 717 +}
 718 +
 719 +static int transfer(struct spi_device *spi, struct spi_message *msg)
 720 +{
 721 +          struct driver_data *drv_data = \
 722 +                                  spi_slave_get_devdata(spi->slave);
 723 +          unsigned long flags;
 724 +          struct chip_data *chip = NULL;
 725 +          struct spi_transfer *transfer = NULL;
 726 +          void *reg = drv_data->ioaddr;
 727 +          void *i2cReg = drv_data->I2C_ioaddr;
 728 +          u32 clk_div = 0;
 729 +          u8 bits = 0;
 730 +          u32 cr0;
 731 +          u32 cr1;
 732 +          u32 sssr;
 733 +
 734 +          spin_lock_irqsave(&drv_data->lock, flags);
 735 +          msg->actual_length = 0;
 736 +          msg->status = -EINPROGRESS;
 737 +          drv_data->cur_msg = msg;
 738 +          /* Initial message state*/
 739 +          msg->state = START_STATE;
 740 +
 741 +          /* We handle only one transfer message since the protocol module has to
 742 +             control the out of band signaling. */
 743 +          transfer = list_entry(msg->transfers.next,
 744 +                                                                      struct spi_transfer,
 745 +                                                                      transfer_list);
 746 +
 747 +          chip = spi_get_ctldata(msg->spi);
 748 +
 749 +          drv_data->busy = 1;
 750 +
 751 +          /* Check transfer length */
 752 +          if (transfer->len > 8192) {
 753 +                      dev_warn(&drv_data->pdev->dev, "SPI-SLAVE: transfer "
 754 +                                              "length greater than 8192\n");
 755 +                      msg->status = -EINVAL;
 756 +                      giveback(drv_data);
 757 +                      spin_unlock_irqrestore(&drv_data->lock, flags);
 758 +                      return 0;
 759 +          }
 760 +
 761 +          /* Setup the transfer state based on the type of transfer */
 762 +          flush(drv_data);
 763 +          drv_data->n_bytes = chip->n_bytes;
 764 +          drv_data->tx = (void *)transfer->tx_buf;
 765 +          drv_data->tx_end = drv_data->tx + transfer->len;
 766 +          drv_data->rx = transfer->rx_buf;
 767 +          drv_data->rx_end = drv_data->rx + transfer->len;
 768 +          drv_data->rx_dma = transfer->rx_dma;
 769 +          drv_data->tx_dma = transfer->tx_dma;
 770 +          drv_data->len = transfer->len;
 771 +          drv_data->write = drv_data->tx ? chip->write : null_writer;
 772 +          drv_data->read = drv_data->rx ? chip->read : null_reader;
 773 +
 774 +          /* Change speed and bit per word on a per transfer */
 775 +          cr0 = chip->cr0;
 776 +          if (transfer->bits_per_word) {
 777 +
 778 +                      bits = chip->bits_per_word;
 779 +
 780 +                      clk_div = 0x0;
 781 +
 782 +                      if (transfer->bits_per_word)
 783 +                                  bits = transfer->bits_per_word;
 784 +
 785 +
 786 +                      if (bits <= 8) {
 787 +                                  drv_data->n_bytes = 1;
 788 +                                  drv_data->read = drv_data->read != null_reader ?
 789 +                                                                      u8_reader : null_reader;
 790 +                                  drv_data->write = drv_data->write != null_writer ?
 791 +                                                                      u8_writer : null_writer;
 792 +                      } else if (bits <= 16) {
 793 +                                  drv_data->n_bytes = 2;
 794 +                                  drv_data->read = drv_data->read != null_reader ?
 795 +                                                                      u16_reader : null_reader;
 796 +                                  drv_data->write = drv_data->write != null_writer ?
 797 +                                                                      u16_writer : null_writer;
 798 +                      } else if (bits <= 32) {
 799 +                                  drv_data->n_bytes = 4;
 800 +                                  drv_data->read = drv_data->read != null_reader ?
 801 +                                                                      u32_reader : null_reader;
 802 +                                  drv_data->write = drv_data->write != null_writer ?
 803 +                                                                      u32_writer : null_writer;
 804 +                      }
 805 +
 806 +                      cr0 = clk_div
 807 +                                  | SSCR0_Motorola
 808 +                                  | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
 809 +                                  | SSCR0_SSE
 810 +                                  | SSCR0_TIM
 811 +                                  | SSCR0_RIM
 812 +                                  | (bits > 16 ? SSCR0_EDSS : 0);
 813 +          }
 814 +
 815 +
 816 +#ifdef CONFIG_SPI_MRST_SLAVE_DMA
 817 +       drv_data->dma_mapped = 0;
 818 +       if (chip->enable_dma)
 819 +               drv_data->dma_mapped = map_dma_buffers(drv_data);
 820 +#endif
 821 +
 822 +          msg->state = RUNNING_STATE;
 823 +                      /* Ensure we have the correct interrupt handler    */
 824 +          drv_data->transfer_handler = interrupt_transfer;
 825 +                      /* Clear status  */
 826 +          cr1 = chip->cr1 | chip->threshold;
 827 +          write_SSSR(drv_data->clear_sr, reg);
 828 +
 829 +       /* Reload the config and do bitbanging only if SSP not-enable or not-synchronized */
 830 +       if( ( read_SSSR(reg) & SSP_NOT_SYNC )  || (!(read_SSCR0(reg) & SSCR0_SSE) ) ) {
 831 +
 832 +                     write_SSSR(drv_data->clear_sr, reg);      /* clear status */
 833 +                      write_SSCR0(cr0 & ~SSCR0_SSE, reg);
 834 +                      write_SSPSP(0x02010007, reg);
 835 +                      write_SSTO(chip->timeout, reg);
 836 +                      write_SSCR1(0x13001DC0, reg);            /* TBD remove hardcoded value */
 837 +                      write_SSCR0(cr0, reg);
 838 +
 839 +                      /*
 840 +                      *  This routine uses the DFx block to override the SSP inputs
 841 +                      *  and outputs allowing us to bit bang SSPSCLK. On Langwell,
 842 +                      *  we have to generate the clock to clear busy.
 843 +                      */
 844 +
 845 +                      write_I2CDATA(0x3, i2cReg);
 846 +                      udelay(10);
 847 +                      write_I2CCTRL(0x01070034, i2cReg);
 848 +                      udelay(10);
 849 +                      write_I2CDATA(0x00000099, i2cReg);
 850 +                      udelay(10);
 851 +                      write_I2CCTRL(0x01070038, i2cReg);
 852 +                      udelay(10);
 853 +                      sssr = read_SSSR(reg);
 854 +
 855 +                      /* Bit bang the clock until CSS clears */
 856 +                      while (sssr & 0x400000) {
 857 +                                  write_I2CDATA(0x2, i2cReg);
 858 +                                  udelay(10);
 859 +                                  write_I2CCTRL(0x01070034, i2cReg);
 860 +                                  udelay(10);
 861 +                                  write_I2CDATA(0x3, i2cReg);
 862 +                                  udelay(10);
 863 +                                  write_I2CCTRL(0x01070034, i2cReg);
 864 +                                  udelay(10);
 865 +                                  sssr = read_SSSR(reg);
 866 +                      }
 867 +
 868 +                      write_I2CDATA(0x0, i2cReg);
 869 +                      udelay(10);
 870 +                      write_I2CCTRL(0x01070038, i2cReg);
 871 +
 872 +          } else {
 873 +                      write_SSTO(chip->timeout, reg);
 874 +                      write_SSCR1(0x13001DC0, reg);    /* TBD: remove hardcoded value */
 875 +          }
 876 +
 877 +          /* transfer using DMA */
 878 +          if (drv_data->dma_mapped) {
 879 +#ifdef CONFIG_SPI_MRST_SLAVE_DMA
 880 +       cr1 = cr1 | drv_data->dma_cr1;
 881 +       write_SSCR1(0x13701DC0, reg);   /* TBD: remove hardcoded value */
 882 +       dma_transfer(drv_data);
 883 +#endif
 884 +          }
 885 +
 886 +          /* transfer using non interrupt polling */
 887 +          else if (chip->poll_mode)
 888 +                      tasklet_schedule(&drv_data->poll_transfer);
 889 +
 890 +          /* transfer using interrupt driven programmed I/O */
 891 +          else {
 892 +                      cr1 = cr1 | drv_data->int_cr1;
 893 +                      write_SSCR1(cr1, reg);
 894 +          }
 895 +
 896 +          spin_unlock_irqrestore(&drv_data->lock, flags);
 897 +          return 0;
 898 +}
 899 +
 900 +static int setup(struct spi_device *spi)
 901 +{
 902 +          struct mrst_spi_chip *chip_info = NULL;
 903 +          struct chip_data *chip;
 904 +
 905 +          if (!spi->bits_per_word)
 906 +                      spi->bits_per_word = 8;
 907 +
 908 +          if ((spi->bits_per_word < 4 || spi->bits_per_word > 32))
 909 +                      return -EINVAL;
 910 +
 911 +          /* Only alloc on first setup */
 912 +          chip = spi_get_ctldata(spi);
 913 +          if (!chip) {
 914 +                      chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 915 +                      if (!chip) {
 916 +                                  dev_err(&spi->dev,
 917 +                                              "failed setup: can't allocate chip data\n");
 918 +                                  return -ENOMEM;
 919 +                      }
 920 +
 921 +                       chip->enable_dma = 1;
 922 +                       chip->poll_mode = 1;
 923 +                       chip->timeout = 1000;
 924 +                       chip->threshold = SSCR1_RxTresh(1) | SSCR1_TxTresh(1);
 925 +          }
 926 +
 927 +          /*
 928 +          *  protocol drivers may change the chip settings, so...
 929 +          * if chip_info exists, use it
 930 +          */
 931 +          chip_info = spi->controller_data;
 932 +
 933 +          /* chip_info isn't always needed */
 934 +          chip->cr1 = 0;
 935 +          if (chip_info) {
 936 +
 937 +                      chip->timeout = chip_info->timeout;
 938 +
 939 +                      chip->threshold = (SSCR1_RxTresh(chip_info->rx_threshold) &
 940 +                                                                                              SSCR1_RFT) |
 941 +                                              (SSCR1_TxTresh(chip_info->tx_threshold) &
 942 +                                                                                              SSCR1_TFT);
 943 +
 944 +
 945 +                      if (chip_info->enable_loopback)
 946 +                                  chip->cr1 = SSCR1_LBM;
 947 +          }
 948 +
 949 +          chip->cr0 =       SSCR0_Motorola
 950 +                                  | SSCR0_DataSize(spi->bits_per_word > 16 ?
 951 +                                              spi->bits_per_word - 16 : spi->bits_per_word)
 952 +                                  | SSCR0_SSE
 953 +                                  | SSCR0_TIM
 954 +                                  | SSCR0_RIM
 955 +                                  | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
 956 +          chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
 957 +          chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
 958 +                                  | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
 959 +          /* set slave mode */
 960 +          chip->cr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR;
 961 +          chip->cr1 |= SSCR1_SCFR;       /* slave clock is not free running */
 962 +          dev_dbg(&spi->dev, "%d bits/word, mode %d\n",
 963 +                                  spi->bits_per_word,
 964 +                                  spi->mode & 0x3);
 965 +
 966 +          if (spi->bits_per_word <= 8) {
 967 +                      chip->n_bytes = 1;
 968 +                      chip->read = u8_reader;
 969 +                      chip->write = u8_writer;
 970 +          } else if (spi->bits_per_word <= 16) {
 971 +                      chip->n_bytes = 2;
 972 +                      chip->read = u16_reader;
 973 +                      chip->write = u16_writer;
 974 +          } else if (spi->bits_per_word <= 32) {
 975 +                      chip->cr0 |= SSCR0_EDSS;
 976 +                      chip->n_bytes = 4;
 977 +                      chip->read = u32_reader;
 978 +                      chip->write = u32_writer;
 979 +          } else {
 980 +                      dev_err(&spi->dev, "invalid wordsize\n");
 981 +                      return -ENODEV;
 982 +          }
 983 +          chip->bits_per_word = spi->bits_per_word;
 984 +          spi_set_ctldata(spi, chip);
 985 +
 986 +          return 0;
 987 +}
 988 +
 989 +static void cleanup(struct spi_device *spi)
 990 +{
 991 +          struct chip_data *chip = spi_get_ctldata(spi);
 992 +
 993 +          kfree(chip);
 994 +}
 995 +
 996 +static struct mrst_spi_chip spidev_chip_info = {
 997 +          .tx_threshold = 8, /* SSP hardware FIFO threshold */
 998 +          .rx_threshold = 8, /* SSP hardware FIFO threshold */
 999 +          .timeout = 235,      /* See Intel documentation */
1000 +};
1001 +
1002 +/*
1003 + * mrst_parse_spi_dib - mrst-ssp parse the spi device info block
1004 + *        table
1005 + * @pdev: spi controller pci device structure
1006 + * @drv_data: spi controller driver data
1007 + * Context: can sleep
1008 + *
1009 + * ssp controller needs to parse the spi device info block table
1010 + * saved in PCI bar 1 and register them with the spi core subsystem.
1011 + */
1012 +static void mrst_parse_spi_dib(struct pci_dev *pdev,
1013 +                                                                      struct driver_data *drv_data)
1014 +{
1015 +          u32 dib_len;
1016 +          void *dib_vaddr;
1017 +          unsigned long dib_paddr;
1018 +          struct spi_board_info info[1];
1019 +          struct spi_dib_header *header;
1020 +          struct spi_dib *dib;
1021 +          int info_num, i, j, dib_bar;
1022 +          u16  *pval;
1023 +
1024 +          dib_bar = 1;
1025 +          dib_paddr = pci_resource_start(pdev, dib_bar);
1026 +          dib_len = pci_resource_len(pdev, dib_bar);
1027 +
1028 +          printk(KERN_INFO "SPI-Slave: %s() - paddr = 0x%08lx, "
1029 +                                  "iolen = 0x%x\n", __func__, dib_paddr, dib_len);
1030 +
1031 +          dib_vaddr = ioremap(dib_paddr, dib_len);
1032 +          if (!dib_vaddr) {
1033 +                      dev_err(&pdev->dev, "%s(): ioremap failed\n", __func__);
1034 +                      goto err_ioremap;
1035 +          }
1036 +
1037 +          /* bar1 contains a pointer to the SPI DIB table */
1038 +          if (dib_len == 8) {
1039 +                      u32 *ptemp = (u32 *)dib_vaddr;
1040 +                      dib_len = *(ptemp + 1);
1041 +                      dib_vaddr = ioremap(*(unsigned long *)dib_vaddr, dib_len);
1042 +                      iounmap(ptemp);
1043 +          }
1044 +
1045 +          header = (struct spi_dib_header *)dib_vaddr;
1046 +          info_num = (header->length - sizeof(*header)) /
1047 +                                                                                              sizeof(*dib);
1048 +          dib = (struct spi_dib *)&header[1];
1049 +
1050 +          /* search for our dib entry. */
1051 +          for (i = 0; i < info_num; i++)
1052 +                      if (dib[i].host_num == 3)
1053 +                                  break;
1054 +          if (i == info_num)
1055 +                      return;
1056 +
1057 +          strncpy(info[0].modalias, dib[i].name, SPI_DIB_NAME_LEN);
1058 +          info[0].irq = dib[i].irq;
1059 +          info[0].bus_num = dib[i].host_num;
1060 +          info[0].chip_select = dib[i].cs;
1061 +          info[0].mode = 0;
1062 +          info[0].max_speed_hz = 0;
1063 +
1064 +          printk(KERN_INFO "SPI-Slave: name = %s, irq = 0x%x, "
1065 +                      "bus = %d, cs = %d\n", info[0].modalias, info[0].irq,
1066 +                      info[0].bus_num, info[0].chip_select);
1067 +
1068 +          pval = (u16 *)&(dib[i].dev_data[0]);
1069 +
1070 +          info[0].controller_data = &spidev_chip_info; /* Slave chip config */
1071 +
1072 +          for (j = 0; j < 5; j++) {
1073 +                      spidev_chip_info.extra_data[j] = *pval;
1074 +                      pval++;
1075 +          }
1076 +
1077 +          spi_register_board_info(info, 1);
1078 +
1079 +err_ioremap:
1080 +          pci_release_region(pdev, dib_bar);
1081 +
1082 +          return;
1083 +}
1084 +
1085 +static int mrst_spi_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1086 +{
1087 +          struct device *dev = &pdev->dev;
1088 +          struct spi_slave *slave;
1089 +          struct driver_data *drv_data = 0;
1090 +          int status = 0;
1091 +          int pci_bar = 0;
1092 +
1093 +          printk(KERN_INFO "SPI-Slave: found PCI SSP controller(ID: %04x:%04x)\n",
1094 +                      pdev->vendor, pdev->device);
1095 +
1096 +          status = pci_enable_device(pdev);
1097 +          if (status)
1098 +                      return status;
1099 +
1100 +          /* Allocate Slave with space for drv_data and null dma buffer */
1101 +          slave = spi_alloc_slave(dev, sizeof(struct driver_data));
1102 +
1103 +          if (!slave) {
1104 +                      dev_err(&pdev->dev, "cannot alloc spi_slave\n");
1105 +                      status = -ENOMEM;
1106 +                      goto err_free_slave0;
1107 +          }
1108 +
1109 +          drv_data = spi_slave_get_devdata(slave);
1110 +          drv_data->slave = slave;
1111 +
1112 +          drv_data->pdev = pdev;
1113 +          spin_lock_init(&drv_data->lock);
1114 +
1115 +          slave->bus_num = 3;
1116 +          slave->num_chipselect = 1;
1117 +          slave->cleanup = cleanup;
1118 +          slave->setup = setup;
1119 +          slave->transfer = transfer;
1120 +
1121 +          /* get basic io resource and map it */
1122 +          drv_data->paddr = (void *)pci_resource_start(pdev, pci_bar);
1123 +          drv_data->iolen = pci_resource_len(pdev, pci_bar);
1124 +
1125 +          status = pci_request_region(pdev, pci_bar, dev_name(&pdev->dev));
1126 +          if (status)
1127 +                      goto err_free_slave1;
1128 +
1129 +          drv_data->ioaddr =
1130 +                      ioremap_nocache((u32)drv_data->paddr, drv_data->iolen);
1131 +          if (!drv_data->ioaddr) {
1132 +                      status = -ENOMEM;
1133 +                      goto err_free_slave2;
1134 +          }
1135 +          printk(KERN_INFO "SPI-Slave: ioaddr = : %08x\n", (int)drv_data->ioaddr);
1136 +          printk(KERN_INFO "SPI-Slave: attaching to IRQ: %04x\n", pdev->irq);
1137 +
1138 +          mrst_parse_spi_dib(pdev, drv_data);
1139 +
1140 +          /* get base address of IPC registers */
1141 +          drv_data->IPC_paddr = (void *)0xffae8000;
1142 +          drv_data->IPC_ioaddr =
1143 +                      ioremap_nocache((unsigned long)drv_data->IPC_paddr, 0x80);
1144 +          if (!drv_data->IPC_ioaddr) {
1145 +                      status = -ENOMEM;
1146 +                      goto err_free_slave3;
1147 +          }
1148 +          /* get base address of I2C_Serbus registers */
1149 +          drv_data->I2C_paddr = (void *)0xff12b000;
1150 +          drv_data->I2C_ioaddr =
1151 +                      ioremap_nocache((unsigned long)drv_data->I2C_paddr, 0x10);
1152 +          if (!drv_data->I2C_ioaddr) {
1153 +                      status = -ENOMEM;
1154 +                      goto err_free_slave4;
1155 +          }
1156 +
1157 +          printk(KERN_INFO "SPI-Slave: IPC_ioaddr = : %08x\n",
1158 +                      (int)drv_data->IPC_ioaddr);
1159 +          printk(KERN_INFO "SPI-Slave: IPCCSR = : %08x\n",
1160 +                      read_IPCCSR(drv_data->IPC_ioaddr));
1161 +          write_IPCCSR(0x802, drv_data->IPC_ioaddr);
1162 +          printk(KERN_INFO "SPI-Slave: IPCCSR = : %08x\n",
1163 +                      read_IPCCSR(drv_data->IPC_ioaddr));
1164 +
1165 +          /* Attach to IRQ */
1166 +          drv_data->irq = pdev->irq;
1167 +          status = request_irq(drv_data->irq, ssp_int, IRQF_SHARED,
1168 +                                  "mrst_spi3", drv_data);
1169 +          if (status < 0) {
1170 +                      dev_err(&pdev->dev, "can not get IRQ\n");
1171 +                      goto err_free_slave5;
1172 +          }
1173 +
1174 +          drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1175 +                 drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL;
1176 +          drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1177 +          drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1178 +
1179 +          tasklet_init(&drv_data->poll_transfer,
1180 +                                  poll_transfer,     (unsigned long)drv_data);
1181 +
1182 +          /* Setup DMA if requested */
1183 +
1184 +          /* Load default SSP configuration */
1185 +          printk(KERN_INFO "SPI-Slave: setup default SSP configuration\n");
1186 +          write_SSCR0(0, drv_data->ioaddr);
1187 +          write_SSCR1(SSCR1_RxTresh(4) | SSCR1_TxTresh(12), drv_data->ioaddr);
1188 +          write_SSCR0(SSCR0_Motorola
1189 +                                   | SSCR0_DataSize(8),
1190 +                                   drv_data->ioaddr);
1191 +          write_SSTO(0, drv_data->ioaddr);
1192 +          write_SSPSP(0x02010007, drv_data->ioaddr);
1193 +
1194 +          /* Register with the SPI framework */
1195 +          printk(KERN_INFO "SPI-Slave: register with SPI framework\n");
1196 +
1197 +          status = spi_register_slave(slave);
1198 +
1199 +          if (status != 0) {
1200 +                      dev_err(&pdev->dev, "problem registering spi slave\n");
1201 +                      goto err_free_slave6;
1202 +          }
1203 +
1204 +#ifdef CONFIG_SPI_MRST_SLAVE_DMA
1205 +          mrst_spi_dma_init(drv_data);
1206 +#endif
1207 +
1208 +          pci_set_drvdata(pdev, drv_data);
1209 +
1210 +          return status;
1211 +
1212 +err_free_slave6:
1213 +          free_irq(drv_data->irq, drv_data);
1214 +err_free_slave5:
1215 +          iounmap(drv_data->I2C_ioaddr);
1216 +err_free_slave4:
1217 +          iounmap(drv_data->IPC_ioaddr);
1218 +err_free_slave3:
1219 +          iounmap(drv_data->ioaddr);
1220 +err_free_slave2:
1221 +          pci_release_region(pdev, pci_bar);
1222 +err_free_slave1:
1223 +          spi_slave_put(slave);
1224 +err_free_slave0:
1225 +          pci_disable_device(pdev);
1226 +
1227 +          return status;
1228 +}
1229 +
1230 +static void __devexit mrst_spi_remove(struct pci_dev *pdev)
1231 +{
1232 +          struct driver_data *drv_data = pci_get_drvdata(pdev);
1233 +
1234 +          if (!drv_data)
1235 +                      return;
1236 +
1237 +          pci_set_drvdata(pdev, NULL);
1238 +
1239 +#ifdef CONFIG_SPI_MRST_SLAVE_DMA
1240 +          mrst_spi_dma_exit(drv_data);
1241 +          pci_dev_put(drv_data->dmac1);
1242 +#endif
1243 +
1244 +          /* Release IRQ */
1245 +          free_irq(drv_data->irq, drv_data);
1246 +
1247 +          iounmap(drv_data->ioaddr);
1248 +          iounmap(drv_data->I2C_ioaddr);
1249 +          iounmap(drv_data->IPC_ioaddr);
1250 +
1251 +          pci_release_region(pdev, 0);
1252 +
1253 +          /* disconnect from the SPI framework */
1254 +          spi_unregister_slave(drv_data->slave);
1255 +
1256 +          pci_disable_device(pdev);
1257 +
1258 +          return;
1259 +}
1260 +
1261 +#ifdef CONFIG_PM
1262 +
1263 +static int mrst_spi_suspend(struct pci_dev *pdev, pm_message_t state)
1264 +{
1265 +          struct driver_data *drv_data = pci_get_drvdata(pdev);
1266 +          printk(KERN_ERR "spi-slave: suspend\n");
1267 +
1268 +          tasklet_disable(&drv_data->poll_transfer);
1269 +
1270 +          return 0;
1271 +}
1272 +
1273 +static int mrst_spi_resume(struct pci_dev *pdev)
1274 +{
1275 +          struct driver_data *drv_data = pci_get_drvdata(pdev);
1276 +          printk(KERN_ERR "spi-slave: resume\n");
1277 +
1278 +          tasklet_enable(&drv_data->poll_transfer);
1279 +
1280 +          return 0;
1281 +}
1282 +#else
1283 +#define mrst_spi_suspend NULL
1284 +#define mrst_spi_resume NULL
1285 +#endif /* CONFIG_PM */
1286 +
1287 +
1288 +static const struct pci_device_id pci_ids[] __devinitdata = {
1289 +
1290 +          {
1291 +                      .vendor             = PCI_VENDOR_ID_INTEL,
1292 +                      .device             = 0x0815,
1293 +                      .subvendor       = PCI_ANY_ID,
1294 +                      .subdevice        = PCI_ANY_ID,
1295 +          },
1296 +          {},
1297 +};
1298 +
1299 +static struct pci_driver mrst_spi_slave_driver = {
1300 +          .name =                        DRIVER_NAME,
1301 +          .id_table =        pci_ids,
1302 +          .probe =           mrst_spi_probe,
1303 +          .remove =         __devexit_p(mrst_spi_remove),
1304 +          .suspend =       mrst_spi_suspend,
1305 +          .resume            =          mrst_spi_resume,
1306 +};
1307 +
1308 +static int __init mrst_spi_init(void)
1309 +{
1310 +          return pci_register_driver(&mrst_spi_slave_driver);
1311 +}
1312 +
1313 +late_initcall_sync(mrst_spi_init);
1314 +
1315 +static void __exit mrst_spi_exit(void)
1316 +{
1317 +          pci_unregister_driver(&mrst_spi_slave_driver);
1318 +}
1319 +module_exit(mrst_spi_exit);
1320 diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
1321 index b76f246..f58f8c3 100644
1322 --- a/drivers/spi/spi.c
1323 +++ b/drivers/spi/spi.c
1324 @@ -27,10 +27,16 @@
1325  #include <linux/spi/spi.h>
1326
1327
1328 -/* SPI bustype and spi_master class are registered after board init code
1329 - * provides the SPI device tables, ensuring that both are present by the
1330 - * time controller driver registration causes spi_devices to "enumerate".
1331 - */
1332 +/* SPI bustype, spi_master and spi_slave class are registered after board
1333 +* init code provides the SPI device tables, ensuring that both are present
1334 +* by the time controller driver registration causes spi_devices
1335 +* to "enumerate".
1336 +*/
1337 +
1338 +/* SPI Slave Support is added for new spi slave devices: It uses common APIs,
1339 +* apart from few new APIs and a spi_slave structure.
1340 +*/
1341 +
1342  static void spidev_release(struct device *dev)
1343  {
1344         struct spi_device       *spi = to_spi_device(dev);
1345 @@ -43,11 +49,22 @@ static void spidev_release(struct device *dev)
1346         kfree(dev);
1347  }
1348
1349 +static void spidev_slave_release(struct device *dev)
1350 +{
1351 +       struct spi_device       *spi = to_spi_device(dev);
1352 +
1353 +       /* spi slave may cleanup */
1354 +       if (spi->slave->cleanup)
1355 +               spi->slave->cleanup(spi);
1356 +
1357 +       spi_slave_put(spi->slave);
1358 +       kfree(dev);
1359 +}
1360 +
1361  static ssize_t
1362  modalias_show(struct device *dev, struct device_attribute *a, char *buf)
1363  {
1364         const struct spi_device *spi = to_spi_device(dev);
1365 -
1366         return sprintf(buf, "%s\n", spi->modalias);
1367  }
1368
1369 @@ -177,10 +194,13 @@ int spi_register_driver(struct spi_driver *sdrv)
1370         sdrv->driver.bus = &spi_bus_type;
1371         if (sdrv->probe)
1372                 sdrv->driver.probe = spi_drv_probe;
1373 +
1374         if (sdrv->remove)
1375                 sdrv->driver.remove = spi_drv_remove;
1376 +
1377         if (sdrv->shutdown)
1378                 sdrv->driver.shutdown = spi_drv_shutdown;
1379 +
1380         return driver_register(&sdrv->driver);
1381  }
1382  EXPORT_SYMBOL_GPL(spi_register_driver);
1383 @@ -201,6 +221,7 @@ struct boardinfo {
1384
1385  static LIST_HEAD(board_list);
1386  static DEFINE_MUTEX(board_lock);
1387 +static DEFINE_MUTEX(slave_board_lock);
1388
1389  /**
1390   * spi_alloc_device - Allocate a new SPI device
1391 @@ -221,28 +242,70 @@ static DEFINE_MUTEX(board_lock);
1392   */
1393  struct spi_device *spi_alloc_device(struct spi_master *master)
1394  {
1395 -       struct spi_device       *spi;
1396 +       struct spi_device       *spi_m_dev;
1397         struct device           *dev = master->dev.parent;
1398
1399         if (!spi_master_get(master))
1400                 return NULL;
1401
1402 -       spi = kzalloc(sizeof *spi, GFP_KERNEL);
1403 -       if (!spi) {
1404 +       spi_m_dev = kzalloc(sizeof *spi_m_dev, GFP_KERNEL);
1405 +       if (!spi_m_dev) {
1406                 dev_err(dev, "cannot alloc spi_device\n");
1407                 spi_master_put(master);
1408                 return NULL;
1409         }
1410
1411 -       spi->master = master;
1412 -       spi->dev.parent = dev;
1413 -       spi->dev.bus = &spi_bus_type;
1414 -       spi->dev.release = spidev_release;
1415 -       device_initialize(&spi->dev);
1416 -       return spi;
1417 +       spi_m_dev->master = master;
1418 +       spi_m_dev->using_slave = 0;
1419 +       spi_m_dev->dev.parent = dev;
1420 +       spi_m_dev->dev.bus = &spi_bus_type;
1421 +       spi_m_dev->dev.release = spidev_release;
1422 +       device_initialize(&spi_m_dev->dev);
1423 +       return spi_m_dev;
1424  }
1425  EXPORT_SYMBOL_GPL(spi_alloc_device);
1426
1427 +/*
1428 +* spi_alloc_slave_device - Allocate a new SPI device
1429 +* @slave: Controller to which device is connected
1430 +* Context: can sleep
1431 +*
1432 +* Allows a driver to allocate and initialize a spi_device without
1433 +* registering it immediately.  This allows a driver to directly
1434 +* fill the spi_device with device parameters before calling
1435 +* spi_add_slave_device() on it.
1436 +*
1437 +* Caller is responsible to call spi_add_slave_device() on the returned
1438 +* spi_device structure to add it to the SPI slave.  If the caller
1439 +* needs to discard the spi_device without adding it, then it should
1440 +* call spi_dev_slave_put() on it.
1441 +* Returns a pointer to the new device, or NULL.
1442 +*/
1443 +struct spi_device *spi_alloc_slave_device(struct spi_slave *slave)
1444 +{
1445 +       struct spi_device       *spi_s;
1446 +       struct device           *dev = slave->dev.parent;
1447 +
1448 +       if (!spi_slave_get(slave))
1449 +               return NULL;
1450 +
1451 +       spi_s = kzalloc(sizeof *spi_s, GFP_KERNEL);
1452 +       if (!spi_s) {
1453 +               dev_err(dev, "cannot alloc spi_slave_device\n");
1454 +               spi_slave_put(slave);
1455 +               return NULL;
1456 +       }
1457 +
1458 +       spi_s->slave = slave;
1459 +       spi_s->using_slave = 9;
1460 +       spi_s->dev.parent = dev;
1461 +       spi_s->dev.bus = &spi_bus_type;
1462 +       spi_s->dev.release = spidev_slave_release;
1463 +       device_initialize(&spi_s->dev);
1464 +       return spi_s;
1465 +}
1466 +EXPORT_SYMBOL_GPL(spi_alloc_slave_device);
1467 +
1468  /**
1469   * spi_add_device - Add spi_device allocated with spi_alloc_device
1470   * @spi: spi_device to register
1471 @@ -301,6 +364,7 @@ int spi_add_device(struct spi_device *spi)
1472         if (status < 0)
1473                 dev_err(dev, "can't %s %s, status %d\n",
1474                                 "add", dev_name(&spi->dev), status);
1475 +
1476         else
1477                 dev_dbg(dev, "registered child %s\n", dev_name(&spi->dev));
1478
1479 @@ -311,6 +375,74 @@ done:
1480  EXPORT_SYMBOL_GPL(spi_add_device);
1481
1482  /**
1483 +* spi_add_slave_device - Add spi_device allocated with spi_alloc_slave_device
1484 +* @spi: spi_device to register
1485 +*
1486 +* Companion function to spi_alloc_slave_device.  Devices allocated with
1487 +* spi_alloc_slave_device can be added onto the spi bus with this function.
1488 +*
1489 +* Returns 0 on success; negative errno on failure
1490 +*/
1491 +int spi_add_slave_device(struct spi_device *spi)
1492 +{
1493 +       static DEFINE_MUTEX(spi_slave_add_lock);
1494 +       struct device *dev = spi->slave->dev.parent;
1495 +       int status;
1496 +
1497 +       /* Chipselects are numbered 0..max; validate. */
1498 +       if (spi->chip_select >= spi->slave->num_chipselect) {
1499 +               dev_err(dev, "cs%d >= max %d\n",
1500 +                       spi->chip_select,
1501 +                       spi->slave->num_chipselect);
1502 +               return -EINVAL;
1503 +       }
1504 +
1505 +       /* Set the bus ID string */
1506 +       dev_set_name(&spi->dev, "%s.%u", dev_name(&spi->slave->dev),
1507 +                       spi->chip_select);
1508 +
1509 +
1510 +       /* We need to make sure there's no other device with this
1511 +        * chipselect **BEFORE** we call setup(), else we'll trash
1512 +        * its configuration.  Lock against concurrent add() calls.
1513 +        */
1514 +       mutex_lock(&spi_slave_add_lock);
1515 +
1516 +       if (bus_find_device_by_name(&spi_bus_type, NULL, dev_name(&spi->dev))
1517 +                       != NULL) {
1518 +               dev_err(dev, "chipselect %d already in use\n",
1519 +                               spi->chip_select);
1520 +               status = -EBUSY;
1521 +               goto done;
1522 +       }
1523 +
1524 +       /* Drivers may modify this initial i/o setup, but will
1525 +        * normally rely on the device being setup.  Devices
1526 +        * using SPI_CS_HIGH can't coexist well otherwise...
1527 +        */
1528 +       status = spi->slave->setup(spi);
1529 +       if (status < 0) {
1530 +               dev_err(dev, "can't %s %s, status %d\n",
1531 +                               "setup", dev_name(&spi->dev), status);
1532 +               goto done;
1533 +       }
1534 +
1535 +       /* Device may be bound to an active driver when this returns */
1536 +       status = device_add(&spi->dev);
1537 +       if (status < 0)
1538 +               dev_err(dev, "can't %s %s, status %d\n",
1539 +                               "add", dev_name(&spi->dev), status);
1540 +       else
1541 +               dev_dbg(dev, "registered child %s\n", dev_name(&spi->dev));
1542 +
1543 +done:
1544 +       mutex_unlock(&spi_slave_add_lock);
1545 +       return status;
1546 +}
1547 +EXPORT_SYMBOL_GPL(spi_add_slave_device);
1548 +
1549 +
1550 +/**
1551   * spi_new_device - instantiate one new SPI device
1552   * @master: Controller to which device is connected
1553   * @chip: Describes the SPI device
1554 @@ -341,6 +473,8 @@ struct spi_device *spi_new_device(struct spi_master *master,
1555         if (!proxy)
1556                 return NULL;
1557
1558 +
1559 +
1560         WARN_ON(strlen(chip->modalias) >= sizeof(proxy->modalias));
1561
1562         proxy->chip_select = chip->chip_select;
1563 @@ -363,6 +497,54 @@ struct spi_device *spi_new_device(struct spi_master *master,
1564  EXPORT_SYMBOL_GPL(spi_new_device);
1565
1566  /**
1567 +* spi_slave_new_device - instantiate one new SPI device
1568 +* @slave: Controller to which device is connected
1569 +* @chip: Describes the SPI device
1570 +* Context: can sleep
1571 +*
1572 +* On typical mainboards, this is purely internal; and it's not needed
1573 +* after board init creates the hard-wired devices.  Some development
1574 +* platforms may not be able to use spi_register_board_info though, and
1575 +* this is exported so that for example a USB or parport based adapter
1576 +* driver could add devices (which it would learn about out-of-band).
1577 +*
1578 +* Returns the new device, or NULL.
1579 +*/
1580 +struct spi_device *spi_slave_new_device(struct spi_slave *slave,
1581 +                                 struct spi_board_info *chip)
1582 +{
1583 +       struct spi_device       *proxy_slave;
1584 +       int                     status;
1585 +
1586 +       proxy_slave = spi_alloc_slave_device(slave);
1587 +
1588 +       if (!proxy_slave)
1589 +               return NULL;
1590 +
1591 +       WARN_ON(strlen(chip->modalias) >= sizeof(proxy_slave->modalias));
1592 +
1593 +       proxy_slave->chip_select = chip->chip_select;
1594 +       proxy_slave->max_speed_hz = chip->max_speed_hz;
1595 +       proxy_slave->mode = chip->mode;
1596 +       proxy_slave->irq = chip->irq;
1597 +       strlcpy(proxy_slave->modalias, chip->modalias,
1598 +                                       sizeof(proxy_slave->modalias));
1599 +       proxy_slave->dev.platform_data = (void *) chip->platform_data;
1600 +       proxy_slave->controller_data = chip->controller_data;
1601 +       proxy_slave->controller_state = NULL;
1602 +
1603 +       status = spi_add_slave_device(proxy_slave);
1604 +       if (status < 0) {
1605 +               spi_dev_put(proxy_slave);
1606 +               return NULL;
1607 +       }
1608 +
1609 +       return proxy_slave;
1610 +}
1611 +EXPORT_SYMBOL_GPL(spi_slave_new_device);
1612 +
1613 +
1614 +/**
1615   * spi_register_board_info - register SPI devices for a given board
1616   * @info: array of chip descriptors
1617   * @n: how many descriptors are provided
1618 @@ -389,6 +571,7 @@ spi_register_board_info(struct spi_board_info const *info, unsigned n)
1619         bi = kmalloc(sizeof(*bi) + n * sizeof *info, GFP_KERNEL);
1620         if (!bi)
1621                 return -ENOMEM;
1622 +
1623         bi->n_board_info = n;
1624         memcpy(bi->board_info, info, n * sizeof *info);
1625
1626 @@ -398,6 +581,7 @@ spi_register_board_info(struct spi_board_info const *info, unsigned n)
1627         return 0;
1628  }
1629
1630 +
1631  /* FIXME someone should add support for a __setup("spi", ...) that
1632   * creates board info from kernel command lines
1633   */
1634 @@ -423,6 +607,28 @@ static void scan_boardinfo(struct spi_master *master)
1635         mutex_unlock(&board_lock);
1636  }
1637
1638 +static void spi_slave_scan_boardinfo(struct spi_slave *slave)
1639 +{
1640 +       struct boardinfo        *bi;
1641 +
1642 +       mutex_lock(&slave_board_lock);
1643 +       list_for_each_entry(bi, &board_list, list) {
1644 +               struct spi_board_info   *chip = bi->board_info;
1645 +               unsigned                n;
1646 +
1647 +               for (n = bi->n_board_info; n > 0; n--, chip++) {
1648 +                       if (chip->bus_num != slave->bus_num)
1649 +                               continue;
1650 +                       /* NOTE: this relies on spi_new_device to
1651 +                        * issue diagnostics when given bogus inputs
1652 +                        */
1653 +                       (void) spi_slave_new_device(slave, chip);
1654 +
1655 +               }
1656 +       }
1657 +       mutex_unlock(&slave_board_lock);
1658 +}
1659 +
1660  /*-------------------------------------------------------------------------*/
1661
1662  static void spi_master_release(struct device *dev)
1663 @@ -439,6 +645,19 @@ static struct class spi_master_class = {
1664         .dev_release    = spi_master_release,
1665  };
1666
1667 +static void spi_slave_release(struct device *dev)
1668 +{
1669 +       struct spi_slave *slave;
1670 +
1671 +       slave = container_of(dev, struct spi_slave, dev);
1672 +       kfree(slave);
1673 +}
1674 +
1675 +static struct class spi_slave_class = {
1676 +       .name           = "spi_slave",
1677 +       .owner          = THIS_MODULE,
1678 +       .dev_release    = spi_slave_release,
1679 +};
1680
1681  /**
1682   * spi_alloc_master - allocate SPI master controller
1683 @@ -480,6 +699,47 @@ struct spi_master *spi_alloc_master(struct device *dev, unsigned size)
1684  EXPORT_SYMBOL_GPL(spi_alloc_master);
1685
1686  /**
1687 +* spi_alloc_slave - allocate SPI slave controller
1688 +* @dev: the controller, possibly using the platform_bus
1689 +* @size: how much zeroed driver-private data to allocate; the pointer to this
1690 +*      memory is in the driver_data field of the returned device,
1691 +*      accessible with spi_slave_get_devdata().
1692 +* Context: can sleep
1693 +*
1694 +* This call is used only by SPI master controller drivers, which are the
1695 +* only ones directly touching chip registers.  It's how they allocate
1696 +* an spi_master structure, prior to calling spi_register_slave().
1697 +*
1698 +* This must be called from context that can sleep.  It returns the SPI
1699 +* master structure on success, else NULL.
1700 +*
1701 +* The caller is responsible for assigning the bus number and initializing
1702 +* the master's methods before calling spi_register_slave(); and (after errors
1703 +* adding the device) calling spi_slave_put() to prevent a memory leak.
1704 +*/
1705 +struct spi_slave *spi_alloc_slave(struct device *dev, unsigned size)
1706 +{
1707 +       struct spi_slave        *slave;
1708 +
1709 +       if (!dev)
1710 +               return NULL;
1711 +
1712 +       slave = kzalloc(size + sizeof *slave, GFP_KERNEL);
1713 +       if (!slave)
1714 +               return NULL;
1715 +
1716 +       device_initialize(&slave->dev);
1717 +       slave->dev.class = &spi_slave_class;
1718 +       slave->dev.parent = get_device(dev);
1719 +       spi_slave_set_devdata(slave, &slave[1]);
1720 +
1721 +       return slave;
1722 +}
1723 +EXPORT_SYMBOL_GPL(spi_alloc_slave);
1724 +
1725 +
1726 +
1727 +/**
1728   * spi_register_master - register SPI master controller
1729   * @master: initialized master, originally from spi_alloc_master()
1730   * Context: can sleep
1731 @@ -531,7 +791,8 @@ int spi_register_master(struct spi_master *master)
1732         status = device_add(&master->dev);
1733         if (status < 0)
1734                 goto done;
1735 -       dev_dbg(dev, "registered master %s%s\n", dev_name(&master->dev),
1736 +
1737 +       dev_dbg(dev, "spi_register_master() : %s%s\n", dev_name(&master->dev),
1738                         dynamic ? " (dynamic)" : "");
1739
1740         /* populate children from any spi device tables */
1741 @@ -542,6 +803,71 @@ done:
1742  }
1743  EXPORT_SYMBOL_GPL(spi_register_master);
1744
1745 +/**
1746 +* spi_register_slave - register SPI slave controller
1747 +* @master: initialized master, originally from spi_alloc_slave()
1748 +* Context: can sleep
1749 +*
1750 +* SPI slave controllers connect to their drivers using some non-SPI bus,
1751 +* such as the platform bus.  The final stage of probe() in that code
1752 +* includes calling spi_register_slave() to hook up to this SPI bus glue.
1753 +*
1754 +* SPI controllers use board specific (often SOC specific) bus numbers,
1755 +* and board-specific addressing for SPI devices combines those numbers
1756 +* with chip select numbers.  Since SPI does not directly support dynamic
1757 +* device identification, boards need configuration tables telling which
1758 +* chip is at which address.
1759 +*
1760 +* This must be called from context that can sleep.  It returns zero on
1761 +* success, else a negative error code (dropping the slave's refcount).
1762 +* After a successful return, the caller is responsible for calling
1763 +* spi_unregister_slave().
1764 +*/
1765 +int spi_register_slave(struct spi_slave *slave)
1766 +{
1767 +       static atomic_t         dyn_bus_id = ATOMIC_INIT((1<<15) - 1);
1768 +       struct device           *dev = slave->dev.parent;
1769 +       int                     status = -ENODEV;
1770 +       int                     dynamic = 0;
1771 +
1772 +       if (!dev)
1773 +               return -ENODEV;
1774 +
1775 +       /* even if it's just one always-selected device, there must
1776 +        * be at least one chipselect
1777 +        */
1778 +       if (slave->num_chipselect == 0)
1779 +               return -EINVAL;
1780 +
1781 +       /* convention:  dynamically assigned bus IDs count down from the max */
1782 +       if (slave->bus_num < 0) {
1783 +               /* FIXME switch to an IDR based scheme, something like
1784 +                * I2C now uses, so we can't run out of "dynamic" IDs
1785 +                */
1786 +               slave->bus_num = atomic_dec_return(&dyn_bus_id);
1787 +               dynamic = 1;
1788 +       }
1789 +
1790 +       /* register the device, then userspace will see it.
1791 +        * registration fails if the bus ID is in use.
1792 +        */
1793 +       dev_set_name(&slave->dev, "spi%u", slave->bus_num);
1794 +       status = device_add(&slave->dev);
1795 +       if (status < 0)
1796 +               goto done;
1797 +
1798 +       dev_dbg(dev, "registered slave %s%s\n", dev_name(&slave->dev),
1799 +                       dynamic ? " (dynamic)" : "");
1800 +
1801 +       /* populate children from any spi device tables */
1802 +       spi_slave_scan_boardinfo(slave);
1803 +       status = 0;
1804 +done:
1805 +       return status;
1806 +}
1807 +EXPORT_SYMBOL_GPL(spi_register_slave);
1808 +
1809 +
1810
1811  static int __unregister(struct device *dev, void *master_dev)
1812  {
1813 @@ -571,6 +897,27 @@ void spi_unregister_master(struct spi_master *master)
1814  }
1815  EXPORT_SYMBOL_GPL(spi_unregister_master);
1816
1817 +/**
1818 +* spi_unregister_slave - unregister SPI slave controller
1819 +* @master: the slave being unregistered
1820 +* Context: can sleep
1821 +*
1822 +* This call is used only by SPI slave controller drivers, which are the
1823 +* only ones directly touching chip registers.
1824 +*
1825 +* This must be called from context that can sleep.
1826 +*/
1827 +void spi_unregister_slave(struct spi_slave *slave)
1828 +{
1829 +       int dummy;
1830 +
1831 +       dummy = device_for_each_child(slave->dev.parent, &slave->dev,
1832 +                                       __unregister);
1833 +       device_unregister(&slave->dev);
1834 +}
1835 +EXPORT_SYMBOL_GPL(spi_unregister_slave);
1836 +
1837 +
1838  static int __spi_master_match(struct device *dev, void *data)
1839  {
1840         struct spi_master *m;
1841 @@ -718,7 +1065,12 @@ int spi_async(struct spi_device *spi, struct spi_message *message)
1842
1843         message->spi = spi;
1844         message->status = -EINPROGRESS;
1845 -       return master->transfer(spi, message);
1846 +
1847 +       /* TODO: ugly*/
1848 +       if (spi->using_slave == 9)
1849 +               return spi->slave->transfer(spi, message);      /* Slave */
1850 +       else
1851 +               return spi->master->transfer(spi, message);     /* Master */
1852  }
1853  EXPORT_SYMBOL_GPL(spi_async);
1854
1855 @@ -773,6 +1125,18 @@ int spi_sync(struct spi_device *spi, struct spi_message *message)
1856  }
1857  EXPORT_SYMBOL_GPL(spi_sync);
1858
1859 +/* spi_transfer_async - Wraper function to allow spi_async to expose to
1860 +* user protocol drivers for modem handshaking
1861 +*/
1862 +
1863 +int spi_transfer_async(struct spi_device *spi, struct spi_message *message)
1864 +{
1865 +       int status;
1866 +       status = spi_async(spi, message);
1867 +       return status;
1868 +}
1869 +EXPORT_SYMBOL_GPL(spi_transfer_async);
1870 +
1871  /* portable code must never pass more than 32 bytes */
1872  #define        SPI_BUFSIZ      max(32,SMP_CACHE_BYTES)
1873
1874 @@ -871,6 +1235,12 @@ static int __init spi_init(void)
1875         status = class_register(&spi_master_class);
1876         if (status < 0)
1877                 goto err2;
1878 +
1879 +       status = class_register(&spi_slave_class);
1880 +
1881 +       if (status < 0)
1882 +               goto err2;
1883 +
1884         return 0;
1885
1886  err2:
1887 @@ -890,4 +1260,3 @@ err0:
1888   * include needing to have boardinfo data structures be much more public.
1889   */
1890  postcore_initcall(spi_init);
1891 -
1892 diff --git a/include/linux/spi/mrst_spi_slave.h b/include/linux/spi/mrst_spi_slave.h
1893 new file mode 100644
1894 index 0000000..4d73f0e
1895 --- /dev/null
1896 +++ b/include/linux/spi/mrst_spi_slave.h
1897 @@ -0,0 +1,143 @@
1898 +/*
1899 + *  Copyright (C) Intel 2009
1900 + *  Ken Mills <ken.k.mills@intel.com>
1901 + *
1902 + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1903 + *
1904 + *  This program is free software; you can redistribute it and/or modify
1905 + *  it under the terms of the GNU General Public License as published by
1906 + *  the Free Software Foundation; either version 2 of the License, or
1907 + *  (at your option) any later version.
1908 + *
1909 + *  This program is distributed in the hope that it will be useful,
1910 + *  but WITHOUT ANY WARRANTY; without even the implied warranty of
1911 + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1912 + *  GNU General Public License for more details.
1913 + *
1914 + *  You should have received a copy of the GNU General Public License
1915 + *  along with this program; if not, write to the Free Software
1916 + *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
1917 + *
1918 + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1919 + *
1920 + */
1921 +#ifndef MRST_SSP_H_
1922 +#define MRST_SSP_H_
1923 +
1924 +
1925 +/*
1926 + * Langwell SSP serial port register definitions
1927 + */
1928 +
1929 +#define SSCR0_DSS   (0x0000000f)     /* Data Size Select (mask) */
1930 +#define SSCR0_DataSize(x)  ((x) - 1)    /* Data Size Select [4..16] */
1931 +#define SSCR0_FRF   (0x00000030)     /* FRame Format (mask) */
1932 +#define SSCR0_Motorola        (0x0 << 4)         /* Motorola's SPI mode */
1933 +#define SSCR0_ECS   (1 << 6) /* External clock select */
1934 +#define SSCR0_SSE   (1 << 7) /* Synchronous Serial Port Enable */
1935 +
1936 +
1937 +#define SSCR0_SCR   (0x000fff00)      /* Serial Clock Rate (mask) */
1938 +#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
1939 +#define SSCR0_EDSS            (1 << 20)           /* Extended data size select */
1940 +#define SSCR0_NCS   (1 << 21)           /* Network clock select */
1941 +#define SSCR0_RIM    (1 << 22)           /* Receive FIFO overrrun int mask */
1942 +#define SSCR0_TUM   (1 << 23)           /* Transmit FIFO underrun int mask */
1943 +#define SSCR0_FRDC (0x07000000)     /* Frame rate divider control (mask) */
1944 +#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24)            /* Time slots per frame */
1945 +#define SSCR0_ADC   (1 << 30)           /* Audio clock select */
1946 +#define SSCR0_MOD  (1 << 31)           /* Mode (normal or network) */
1947 +
1948 +
1949 +#define SSCR1_RIE    (1 << 0) /* Receive FIFO Interrupt Enable */
1950 +#define SSCR1_TIE     (1 << 1) /* Transmit FIFO Interrupt Enable */
1951 +#define SSCR1_LBM   (1 << 2) /* Loop-Back Mode */
1952 +#define SSCR1_SPO   (1 << 3) /* SSPSCLK polarity setting */
1953 +#define SSCR1_SPH   (1 << 4) /* Motorola SPI SSPSCLK phase setting */
1954 +#define SSCR1_MWDS           (1 << 5) /* Microwire Transmit Data Size */
1955 +#define SSCR1_TFT    (0x000003c0)     /* Transmit FIFO Threshold (mask) */
1956 +#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
1957 +#define SSCR1_RFT    (0x00003c00)     /* Receive FIFO Threshold (mask) */
1958 +#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
1959 +
1960 +#define SSSR_TNF     (1 << 2) /* Transmit FIFO Not Full */
1961 +#define SSSR_RNE     (1 << 3) /* Receive FIFO Not Empty */
1962 +#define SSSR_BSY     (1 << 4) /* SSP Busy */
1963 +#define SSSR_TFS     (1 << 5) /* Transmit FIFO Service Request */
1964 +#define SSSR_RFS     (1 << 6) /* Receive FIFO Service Request */
1965 +#define SSSR_ROR    (1 << 7) /* Receive FIFO Overrun */
1966 +
1967 +#define SSCR0_TIM    (1 << 23)           /* Transmit FIFO Under Run Int Mask */
1968 +#define SSCR0_RIM    (1 << 22)           /* Receive FIFO Over Run int Mask */
1969 +#define SSCR0_NCS   (1 << 21)           /* Network Clock Select */
1970 +#define SSCR0_EDSS            (1 << 20)           /* Extended Data Size Select */
1971 +
1972 +#define SSCR0_TISSP            (1 << 4) /* TI Sync Serial Protocol */
1973 +#define SSCR0_PSP   (3 << 4) /* PSP - Programmable Serial Protocol */
1974 +#define SSCR1_TTELP            (1 << 31)           /* TXD Tristate Enable Last Phase */
1975 +#define SSCR1_TTE    (1 << 30)           /* TXD Tristate Enable */
1976 +#define SSCR1_EBCEI            (1 << 29)           /* Enable Bit Count Error interrupt */
1977 +#define SSCR1_SCFR (1 << 28)           /* Slave Clock free Running */
1978 +#define SSCR1_ECRA (1 << 27)           /* Enable Clock Request A */
1979 +#define SSCR1_ECRB (1 << 26)           /* Enable Clock request B */
1980 +#define SSCR1_SCLKDIR        (1 << 25)           /* Serial Bit Rate Clock Direction */
1981 +#define SSCR1_SFRMDIR       (1 << 24)           /* Frame Direction */
1982 +#define SSCR1_RWOT            (1 << 23)           /* Receive Without Transmit */
1983 +#define SSCR1_TRAIL (1 << 22)           /* Trailing Byte */
1984 +#define SSCR1_TSRE (1 << 21)           /* Transmit Service Request Enable */
1985 +#define SSCR1_RSRE (1 << 20)           /* Receive Service Request Enable */
1986 +#define SSCR1_TINTE (1 << 19)           /* Receiver Time-out Interrupt enable */
1987 +#define SSCR1_PINTE            (1 << 18)           /* Trailing Byte Interupt Enable */
1988 +#define SSCR1_STRF (1 << 15)           /* Select FIFO or EFWR */
1989 +#define SSCR1_EFWR            (1 << 14)           /* Enable FIFO Write/Read */
1990 +
1991 +#define SSSR_BCE     (1 << 23)           /* Bit Count Error */
1992 +#define SSSR_CSS     (1 << 22)           /* Clock Synchronisation Status */
1993 +#define SSSR_TUR     (1 << 21)           /* Transmit FIFO Under Run */
1994 +#define SSSR_EOC    (1 << 20)           /* End Of Chain */
1995 +#define SSSR_TINT     (1 << 19)           /* Receiver Time-out Interrupt */
1996 +#define SSSR_PINT    (1 << 18)           /* Peripheral Trailing Byte Interrupt */
1997 +
1998 +#define SSPSP_FSRT (1 << 25)           /* Frame Sync Relative Timing */
1999 +#define SSPSP_DMYSTOP(x) ((x) << 23)         /* Dummy Stop */
2000 +#define SSPSP_SFRMWDTH(x) ((x) << 16)      /* Serial Frame Width */
2001 +#define SSPSP_SFRMDLY(x) ((x) << 9)           /* Serial Frame Delay */
2002 +#define SSPSP_DMYSTRT(x) ((x) << 7)           /* Dummy Start */
2003 +#define SSPSP_STRTDLY(x) ((x) << 4)            /* Start Delay */
2004 +#define SSPSP_ETDS            (1 << 3) /* End of Transfer data State */
2005 +#define SSPSP_SFRMP          (1 << 2) /* Serial Frame Polarity */
2006 +#define SSPSP_SCMODE(x)   ((x) << 0)           /* Serial Bit Rate Clock Mode */
2007 +
2008 +/* spi_board_info.controller_data for SPI slave devices,
2009 + * copied to spi_device.platform_data ... mostly for dma tuning
2010 + */
2011 +struct mrst_spi_chip {
2012 +          u8 tx_threshold;
2013 +          u8 rx_threshold;
2014 +          u8 dma_burst_size;
2015 +          u32 timeout;
2016 +          u8 enable_loopback;
2017 +          u16 extra_data[5];
2018 +};
2019 +
2020 +
2021 +#define SPI_DIB_NAME_LEN  16
2022 +#define SPI_DIB_SPEC_INFO_LEN      10
2023 +
2024 +struct spi_dib_header {
2025 +          u32       signature;
2026 +          u32       length;
2027 +          u8         rev;
2028 +          u8         checksum;
2029 +          u8         dib[0];
2030 +} __attribute__((packed));
2031 +
2032 +struct spi_dib {
2033 +          u16       host_num;
2034 +          u16       cs;
2035 +          u16       irq;
2036 +          char      name[SPI_DIB_NAME_LEN];
2037 +          u8         dev_data[SPI_DIB_SPEC_INFO_LEN];
2038 +} __attribute__((packed));
2039 +
2040 +#endif /*MRST_SSP_H_*/
2041 diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
2042 index 97b60b3..87b4d12 100644
2043 --- a/include/linux/spi/spi.h
2044 +++ b/include/linux/spi/spi.h
2045 @@ -23,15 +23,19 @@
2046  #include <linux/mod_devicetable.h>
2047
2048  /*
2049 - * INTERFACES between SPI master-side drivers and SPI infrastructure.
2050 - * (There's no SPI slave support for Linux yet...)
2051 + * INTERFACES between SPI Master/Slave side drivers and
2052 + * SPI infrastructure.
2053 + * SPI Slave Support added : It uses few new APIs and
2054 + * a new spi_slave struct
2055   */
2056  extern struct bus_type spi_bus_type;
2057
2058  /**
2059   * struct spi_device - Master side proxy for an SPI slave device
2060   * @dev: Driver model representation of the device.
2061 - * @master: SPI controller used with the device.
2062 + * @master: SPI Master controller used with the device.
2063 + * @slave: SPI Slave Controller used with the device
2064 + * @using_slave: SPI Slave Flag used by spi_async()
2065   * @max_speed_hz: Maximum clock rate to be used with this chip
2066   *     (on this board); may be changed by the device's driver.
2067   *     The spi_transfer.speed_hz can override this for each transfer.
2068 @@ -68,6 +72,8 @@ extern struct bus_type spi_bus_type;
2069  struct spi_device {
2070         struct device           dev;
2071         struct spi_master       *master;
2072 +       struct spi_slave        *slave;
2073 +       u8                      using_slave;
2074         u32                     max_speed_hz;
2075         u8                      chip_select;
2076         u8                      mode;
2077 @@ -143,7 +149,6 @@ static inline void *spi_get_drvdata(struct spi_device *spi)
2078  struct spi_message;
2079
2080
2081 -
2082  /**
2083   * struct spi_driver - Host side "protocol" driver
2084   * @id_table: List of SPI devices supported by this driver
2085 @@ -295,16 +300,56 @@ struct spi_master {
2086         void                    (*cleanup)(struct spi_device *spi);
2087  };
2088
2089 +/**
2090 + * struct spi_slave - interface to SPI Slave Controller
2091 + * @dev: device interface to this driver
2092 + * @bus_num: board-specific (and often SOC-specific) identifier for a
2093 + *     given SPI controller.
2094 + * @num_chipselect: chipselects are used to distinguish individual
2095 + *     SPI slaves, and are numbered from zero to num_chipselects.
2096 + *     each slave has a chipselect signal, but it's common that not
2097 + *     every chipselect is connected to a slave.
2098 + * @setup: updates the device mode and clocking records used by a
2099 + *     device's SPI controller; protocol code may call this.  This
2100 + *     must fail if an unrecognized or unsupported mode is requested.
2101 + *     It's always safe to call this unless transfers are pending on
2102 + *     the device whose settings are being modified.
2103 + * @transfer: adds a message to the controller's transfer queue.
2104 + * @cleanup: frees controller-specific state
2105 + */
2106 +struct spi_slave {
2107 +       struct device   dev;
2108 +       s16                     bus_num;
2109 +       u16                     num_chipselect;
2110 +
2111 +       int                     (*setup)(struct spi_device *spi);
2112 +
2113 +       int                     (*transfer)(struct spi_device *spi,
2114 +                                               struct spi_message *mesg);
2115 +
2116 +       void                    (*cleanup)(struct spi_device *spi);
2117 +};
2118 +
2119  static inline void *spi_master_get_devdata(struct spi_master *master)
2120  {
2121         return dev_get_drvdata(&master->dev);
2122  }
2123
2124 +static inline void *spi_slave_get_devdata(struct spi_slave *slave)
2125 +{
2126 +       return dev_get_drvdata(&slave->dev);
2127 +}
2128 +
2129  static inline void spi_master_set_devdata(struct spi_master *master, void *data)
2130  {
2131         dev_set_drvdata(&master->dev, data);
2132  }
2133
2134 +static inline void spi_slave_set_devdata(struct spi_slave *slave, void *data)
2135 +{
2136 +       dev_set_drvdata(&slave->dev, data);
2137 +}
2138 +
2139  static inline struct spi_master *spi_master_get(struct spi_master *master)
2140  {
2141         if (!master || !get_device(&master->dev))
2142 @@ -312,20 +357,42 @@ static inline struct spi_master *spi_master_get(struct spi_master *master)
2143         return master;
2144  }
2145
2146 +static inline struct spi_slave *spi_slave_get(struct spi_slave *slave)
2147 +{
2148 +       if (!slave || !get_device(&slave->dev))
2149 +               return NULL;
2150 +       return slave;
2151 +}
2152 +
2153  static inline void spi_master_put(struct spi_master *master)
2154  {
2155         if (master)
2156                 put_device(&master->dev);
2157  }
2158
2159 +static inline void spi_slave_put(struct spi_slave *slave)
2160 +{
2161 +       if (slave)
2162 +               put_device(&slave->dev);
2163 +}
2164 +
2165
2166  /* the spi driver core manages memory for the spi_master classdev */
2167  extern struct spi_master *
2168  spi_alloc_master(struct device *host, unsigned size);
2169
2170 +extern struct spi_slave *
2171 +spi_alloc_slave(struct device *host, unsigned size);
2172 +
2173 +
2174  extern int spi_register_master(struct spi_master *master);
2175 +
2176 +extern int spi_register_slave(struct spi_slave *slave);
2177 +
2178  extern void spi_unregister_master(struct spi_master *master);
2179
2180 +extern void spi_unregister_slave(struct spi_slave *slave);
2181 +
2182  extern struct spi_master *spi_busnum_to_master(u16 busnum);
2183
2184  /*---------------------------------------------------------------------------*/
2185 @@ -551,6 +618,18 @@ extern int spi_async(struct spi_device *spi, struct spi_message *message);
2186
2187  extern int spi_sync(struct spi_device *spi, struct spi_message *message);
2188
2189 +static inline int
2190 +spi_slave_setup(struct spi_device *spi)
2191 +{
2192 +       return spi->slave->setup(spi);
2193 +}
2194 +
2195 +
2196 +/* spi_transfer_async() exposes spi_async() functionality */
2197 +extern int spi_transfer_async(struct spi_device *spi,
2198 +                             struct spi_message *message);
2199 +
2200 +
2201  /**
2202   * spi_write - SPI synchronous write
2203   * @spi: device to which data will be written
2204 @@ -759,12 +838,23 @@ spi_register_board_info(struct spi_board_info const *info, unsigned n)
2205  extern struct spi_device *
2206  spi_alloc_device(struct spi_master *master);
2207
2208 +extern struct spi_device *
2209 +spi_alloc_slave_device(struct spi_slave *slave);
2210 +
2211  extern int
2212  spi_add_device(struct spi_device *spi);
2213
2214 +extern int
2215 +spi_add_slave_device(struct spi_device *spi);
2216 +
2217 +
2218  extern struct spi_device *
2219  spi_new_device(struct spi_master *, struct spi_board_info *);
2220
2221 +extern struct spi_device *
2222 +spi_slave_new_device(struct spi_slave *, struct spi_board_info *);
2223 +
2224 +
2225  static inline void
2226  spi_unregister_device(struct spi_device *spi)
2227  {
2228 --
2229 1.6.2.5
2230