1 From: Jesse Barnes <jbarnes@virtuousgeek.org>
2 Date: Tue, 29 Jul 2008 18:54:06 +0000 (-0700)
3 Subject: i915: Use more consistent names for regs, and store them in a separate file.
5 X-Git-Url: http://gitweb.freedesktop.org/?p=users/anholt/anholt/linux-2.6.git;a=commitdiff;h=db1cbbd8c4d42e58e9acb3e7af59ad1bb238260d
7 i915: Use more consistent names for regs, and store them in a separate file.
9 Signed-off-by: Eric Anholt <eric@anholt.net>
12 --- a/drivers/gpu/drm/i915/i915_dma.c
13 +++ b/drivers/gpu/drm/i915/i915_dma.c
14 @@ -40,11 +40,11 @@ int i915_wait_ring(struct drm_device * d
16 drm_i915_private_t *dev_priv = dev->dev_private;
17 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
18 - u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
19 + u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
22 for (i = 0; i < 10000; i++) {
23 - ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
24 + ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
25 ring->space = ring->head - (ring->tail + 8);
27 ring->space += ring->Size;
28 @@ -67,8 +67,8 @@ void i915_kernel_lost_context(struct drm
29 drm_i915_private_t *dev_priv = dev->dev_private;
30 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
32 - ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
33 - ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
34 + ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
35 + ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
36 ring->space = ring->head - (ring->tail + 8);
38 ring->space += ring->Size;
39 @@ -98,13 +98,13 @@ static int i915_dma_cleanup(struct drm_d
40 drm_pci_free(dev, dev_priv->status_page_dmah);
41 dev_priv->status_page_dmah = NULL;
42 /* Need to rewrite hardware status page */
43 - I915_WRITE(0x02080, 0x1ffff000);
44 + I915_WRITE(HWS_PGA, 0x1ffff000);
47 if (dev_priv->status_gfx_addr) {
48 dev_priv->status_gfx_addr = 0;
49 drm_core_ioremapfree(&dev_priv->hws_map, dev);
50 - I915_WRITE(0x2080, 0x1ffff000);
51 + I915_WRITE(HWS_PGA, 0x1ffff000);
55 @@ -170,7 +170,7 @@ static int i915_initialize(struct drm_de
56 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
58 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
59 - I915_WRITE(0x02080, dev_priv->dma_status_page);
60 + I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
62 DRM_DEBUG("Enabled hardware status page\n");
64 @@ -201,9 +201,9 @@ static int i915_dma_resume(struct drm_de
65 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
67 if (dev_priv->status_gfx_addr != 0)
68 - I915_WRITE(0x02080, dev_priv->status_gfx_addr);
69 + I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
71 - I915_WRITE(0x02080, dev_priv->dma_status_page);
72 + I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
73 DRM_DEBUG("Enabled hardware status page\n");
76 @@ -402,8 +402,8 @@ static void i915_emit_breadcrumb(struct
77 dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1;
80 - OUT_RING(CMD_STORE_DWORD_IDX);
82 + OUT_RING(MI_STORE_DWORD_INDEX);
83 + OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
84 OUT_RING(dev_priv->counter);
87 @@ -505,7 +505,7 @@ static int i915_dispatch_flip(struct drm
88 i915_kernel_lost_context(dev);
91 - OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
92 + OUT_RING(MI_FLUSH | MI_READ_FLUSH);
96 @@ -530,8 +530,8 @@ static int i915_dispatch_flip(struct drm
97 dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
100 - OUT_RING(CMD_STORE_DWORD_IDX);
102 + OUT_RING(MI_STORE_DWORD_INDEX);
103 + OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
104 OUT_RING(dev_priv->counter);
107 @@ -728,8 +728,8 @@ static int i915_set_status_page(struct d
108 dev_priv->hw_status_page = dev_priv->hws_map.handle;
110 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
111 - I915_WRITE(0x02080, dev_priv->status_gfx_addr);
112 - DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n",
113 + I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
114 + DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
115 dev_priv->status_gfx_addr);
116 DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
118 --- a/drivers/gpu/drm/i915/i915_drv.c
119 +++ b/drivers/gpu/drm/i915/i915_drv.c
120 @@ -279,13 +279,13 @@ static int i915_suspend(struct drm_devic
121 dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
122 dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
123 dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
124 - dev_priv->saveDSPABASE = I915_READ(DSPABASE);
125 + dev_priv->saveDSPAADDR = I915_READ(DSPAADDR);
127 dev_priv->saveDSPASURF = I915_READ(DSPASURF);
128 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
130 i915_save_palette(dev, PIPE_A);
131 - dev_priv->savePIPEASTAT = I915_READ(I915REG_PIPEASTAT);
132 + dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT);
134 /* Pipe & plane B info */
135 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
136 @@ -307,13 +307,13 @@ static int i915_suspend(struct drm_devic
137 dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
138 dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
139 dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
140 - dev_priv->saveDSPBBASE = I915_READ(DSPBBASE);
141 + dev_priv->saveDSPBADDR = I915_READ(DSPBADDR);
142 if (IS_I965GM(dev) || IS_IGD_GM(dev)) {
143 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
144 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
146 i915_save_palette(dev, PIPE_B);
147 - dev_priv->savePIPEBSTAT = I915_READ(I915REG_PIPEBSTAT);
148 + dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);
151 dev_priv->saveADPA = I915_READ(ADPA);
152 @@ -328,9 +328,9 @@ static int i915_suspend(struct drm_devic
153 dev_priv->saveLVDS = I915_READ(LVDS);
154 if (!IS_I830(dev) && !IS_845G(dev))
155 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
156 - dev_priv->saveLVDSPP_ON = I915_READ(LVDSPP_ON);
157 - dev_priv->saveLVDSPP_OFF = I915_READ(LVDSPP_OFF);
158 - dev_priv->savePP_CYCLE = I915_READ(PP_CYCLE);
159 + dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
160 + dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
161 + dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
163 /* FIXME: save TV & SDVO state */
165 @@ -341,19 +341,19 @@ static int i915_suspend(struct drm_devic
166 dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
168 /* Interrupt state */
169 - dev_priv->saveIIR = I915_READ(I915REG_INT_IDENTITY_R);
170 - dev_priv->saveIER = I915_READ(I915REG_INT_ENABLE_R);
171 - dev_priv->saveIMR = I915_READ(I915REG_INT_MASK_R);
172 + dev_priv->saveIIR = I915_READ(IIR);
173 + dev_priv->saveIER = I915_READ(IER);
174 + dev_priv->saveIMR = I915_READ(IMR);
177 - dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0);
178 - dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1);
179 - dev_priv->saveVCLK_POST_DIV = I915_READ(VCLK_POST_DIV);
180 + dev_priv->saveVGA0 = I915_READ(VGA0);
181 + dev_priv->saveVGA1 = I915_READ(VGA1);
182 + dev_priv->saveVGA_PD = I915_READ(VGA_PD);
183 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
185 /* Clock gating state */
186 dev_priv->saveD_STATE = I915_READ(D_STATE);
187 - dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D);
188 + dev_priv->saveCG_2D_DIS = I915_READ(CG_2D_DIS);
190 /* Cache mode state */
191 dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
192 @@ -363,7 +363,7 @@ static int i915_suspend(struct drm_devic
195 for (i = 0; i < 16; i++) {
196 - dev_priv->saveSWF0[i] = I915_READ(SWF0 + (i << 2));
197 + dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));
198 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
200 for (i = 0; i < 3; i++)
201 @@ -424,7 +424,7 @@ static int i915_resume(struct drm_device
202 I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
203 I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
204 I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
205 - I915_WRITE(DSPABASE, dev_priv->saveDSPABASE);
206 + I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR);
207 I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
209 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
210 @@ -436,7 +436,7 @@ static int i915_resume(struct drm_device
211 i915_restore_palette(dev, PIPE_A);
212 /* Enable the plane */
213 I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
214 - I915_WRITE(DSPABASE, I915_READ(DSPABASE));
215 + I915_WRITE(DSPAADDR, I915_READ(DSPAADDR));
217 /* Pipe & plane B info */
218 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
219 @@ -466,7 +466,7 @@ static int i915_resume(struct drm_device
220 I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
221 I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
222 I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
223 - I915_WRITE(DSPBBASE, dev_priv->saveDSPBBASE);
224 + I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR);
225 I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
227 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
228 @@ -478,7 +478,7 @@ static int i915_resume(struct drm_device
229 i915_restore_palette(dev, PIPE_B);
230 /* Enable the plane */
231 I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
232 - I915_WRITE(DSPBBASE, I915_READ(DSPBBASE));
233 + I915_WRITE(DSPBADDR, I915_READ(DSPBADDR));
236 I915_WRITE(ADPA, dev_priv->saveADPA);
237 @@ -493,9 +493,9 @@ static int i915_resume(struct drm_device
239 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
240 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
241 - I915_WRITE(LVDSPP_ON, dev_priv->saveLVDSPP_ON);
242 - I915_WRITE(LVDSPP_OFF, dev_priv->saveLVDSPP_OFF);
243 - I915_WRITE(PP_CYCLE, dev_priv->savePP_CYCLE);
244 + I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
245 + I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
246 + I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
247 I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
249 /* FIXME: restore TV & SDVO state */
250 @@ -508,14 +508,14 @@ static int i915_resume(struct drm_device
253 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
254 - I915_WRITE(VCLK_DIVISOR_VGA0, dev_priv->saveVCLK_DIVISOR_VGA0);
255 - I915_WRITE(VCLK_DIVISOR_VGA1, dev_priv->saveVCLK_DIVISOR_VGA1);
256 - I915_WRITE(VCLK_POST_DIV, dev_priv->saveVCLK_POST_DIV);
257 + I915_WRITE(VGA0, dev_priv->saveVGA0);
258 + I915_WRITE(VGA1, dev_priv->saveVGA1);
259 + I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
262 /* Clock gating state */
263 I915_WRITE (D_STATE, dev_priv->saveD_STATE);
264 - I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
265 + I915_WRITE(CG_2D_DIS, dev_priv->saveCG_2D_DIS);
267 /* Cache mode state */
268 I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
269 @@ -524,7 +524,7 @@ static int i915_resume(struct drm_device
270 I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
272 for (i = 0; i < 16; i++) {
273 - I915_WRITE(SWF0 + (i << 2), dev_priv->saveSWF0[i]);
274 + I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);
275 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]);
277 for (i = 0; i < 3; i++)
278 --- a/drivers/gpu/drm/i915/i915_drv.h
279 +++ b/drivers/gpu/drm/i915/i915_drv.h
284 +#include "i915_reg.h"
286 /* General customization:
289 @@ -138,7 +140,7 @@ typedef struct drm_i915_private {
297 u32 savePFIT_PGM_RATIOS;
298 @@ -159,24 +161,24 @@ typedef struct drm_i915_private {
306 - u32 saveVCLK_DIVISOR_VGA0;
307 - u32 saveVCLK_DIVISOR_VGA1;
308 - u32 saveVCLK_POST_DIV;
316 - u32 saveLVDSPP_OFF;
317 + u32 savePP_ON_DELAYS;
318 + u32 savePP_OFF_DELAYS;
326 + u32 savePP_DIVISOR;
327 u32 savePFIT_CONTROL;
328 u32 save_palette_a[256];
329 u32 save_palette_b[256];
330 @@ -189,7 +191,7 @@ typedef struct drm_i915_private {
332 u32 saveCACHE_MODE_0;
334 - u32 saveDSPCLK_GATE_D;
336 u32 saveMI_ARB_STATE;
339 @@ -283,816 +285,26 @@ extern void i915_mem_release(struct drm_
340 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
341 dev_priv->ring.tail = outring; \
342 dev_priv->ring.space -= outcount * 4; \
343 - I915_WRITE(LP_RING + RING_TAIL, outring); \
344 + I915_WRITE(PRB0_TAIL, outring); \
347 -extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
349 -/* Extended config space */
354 -#define VGA_ST01_MDA 0x3ba
355 -#define VGA_ST01_CGA 0x3da
357 -#define VGA_MSR_WRITE 0x3c2
358 -#define VGA_MSR_READ 0x3cc
359 -#define VGA_MSR_MEM_EN (1<<1)
360 -#define VGA_MSR_CGA_MODE (1<<0)
362 -#define VGA_SR_INDEX 0x3c4
363 -#define VGA_SR_DATA 0x3c5
365 -#define VGA_AR_INDEX 0x3c0
366 -#define VGA_AR_VID_EN (1<<5)
367 -#define VGA_AR_DATA_WRITE 0x3c0
368 -#define VGA_AR_DATA_READ 0x3c1
370 -#define VGA_GR_INDEX 0x3ce
371 -#define VGA_GR_DATA 0x3cf
373 -#define VGA_GR_MEM_READ_MODE_SHIFT 3
374 -#define VGA_GR_MEM_READ_MODE_PLANE 1
376 -#define VGA_GR_MEM_MODE_MASK 0xc
377 -#define VGA_GR_MEM_MODE_SHIFT 2
378 -#define VGA_GR_MEM_A0000_AFFFF 0
379 -#define VGA_GR_MEM_A0000_BFFFF 1
380 -#define VGA_GR_MEM_B0000_B7FFF 2
381 -#define VGA_GR_MEM_B0000_BFFFF 3
383 -#define VGA_DACMASK 0x3c6
384 -#define VGA_DACRX 0x3c7
385 -#define VGA_DACWX 0x3c8
386 -#define VGA_DACDATA 0x3c9
388 -#define VGA_CR_INDEX_MDA 0x3b4
389 -#define VGA_CR_DATA_MDA 0x3b5
390 -#define VGA_CR_INDEX_CGA 0x3d4
391 -#define VGA_CR_DATA_CGA 0x3d5
393 -#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
394 -#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
395 -#define CMD_REPORT_HEAD (7<<23)
396 -#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
397 -#define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)
399 -#define INST_PARSER_CLIENT 0x00000000
400 -#define INST_OP_FLUSH 0x02000000
401 -#define INST_FLUSH_MAP_CACHE 0x00000001
403 -#define BB1_START_ADDR_MASK (~0x7)
404 -#define BB1_PROTECTED (1<<0)
405 -#define BB1_UNPROTECTED (0<<0)
406 -#define BB2_END_ADDR_MASK (~0x7)
408 -/* Framebuffer compression */
409 -#define FBC_CFB_BASE 0x03200 /* 4k page aligned */
410 -#define FBC_LL_BASE 0x03204 /* 4k page aligned */
411 -#define FBC_CONTROL 0x03208
412 -#define FBC_CTL_EN (1<<31)
413 -#define FBC_CTL_PERIODIC (1<<30)
414 -#define FBC_CTL_INTERVAL_SHIFT (16)
415 -#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
416 -#define FBC_CTL_STRIDE_SHIFT (5)
417 -#define FBC_CTL_FENCENO (1<<0)
418 -#define FBC_COMMAND 0x0320c
419 -#define FBC_CMD_COMPRESS (1<<0)
420 -#define FBC_STATUS 0x03210
421 -#define FBC_STAT_COMPRESSING (1<<31)
422 -#define FBC_STAT_COMPRESSED (1<<30)
423 -#define FBC_STAT_MODIFIED (1<<29)
424 -#define FBC_STAT_CURRENT_LINE (1<<0)
425 -#define FBC_CONTROL2 0x03214
426 -#define FBC_CTL_FENCE_DBL (0<<4)
427 -#define FBC_CTL_IDLE_IMM (0<<2)
428 -#define FBC_CTL_IDLE_FULL (1<<2)
429 -#define FBC_CTL_IDLE_LINE (2<<2)
430 -#define FBC_CTL_IDLE_DEBUG (3<<2)
431 -#define FBC_CTL_CPU_FENCE (1<<1)
432 -#define FBC_CTL_PLANEA (0<<0)
433 -#define FBC_CTL_PLANEB (1<<0)
434 -#define FBC_FENCE_OFF 0x0321b
436 -#define FBC_LL_SIZE (1536)
437 -#define FBC_LL_PAD (32)
441 -#define USER_INT_FLAG (1<<1)
442 -#define VSYNC_PIPEB_FLAG (1<<5)
443 -#define VSYNC_PIPEA_FLAG (1<<7)
444 -#define HWB_OOM_FLAG (1<<13) /* binner out of memory */
446 -#define I915REG_HWSTAM 0x02098
447 -#define I915REG_INT_IDENTITY_R 0x020a4
448 -#define I915REG_INT_MASK_R 0x020a8
449 -#define I915REG_INT_ENABLE_R 0x020a0
451 -#define I915REG_PIPEASTAT 0x70024
452 -#define I915REG_PIPEBSTAT 0x71024
454 -#define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
455 -#define I915_VBLANK_CLEAR (1UL<<1)
457 -#define SRX_INDEX 0x3c4
458 -#define SRX_DATA 0x3c5
460 -#define SR01_SCREEN_OFF (1<<5)
462 -#define PPCR 0x61204
463 -#define PPCR_ON (1<<0)
465 -#define DVOB 0x61140
466 -#define DVOB_ON (1<<31)
467 -#define DVOC 0x61160
468 -#define DVOC_ON (1<<31)
469 -#define LVDS 0x61180
470 -#define LVDS_ON (1<<31)
472 -#define ADPA 0x61100
473 -#define ADPA_DPMS_MASK (~(3<<10))
474 -#define ADPA_DPMS_ON (0<<10)
475 -#define ADPA_DPMS_SUSPEND (1<<10)
476 -#define ADPA_DPMS_STANDBY (2<<10)
477 -#define ADPA_DPMS_OFF (3<<10)
479 -#define NOPID 0x2094
480 -#define LP_RING 0x2030
481 -#define HP_RING 0x2040
482 -/* The binner has its own ring buffer:
484 -#define HWB_RING 0x2400
486 -#define RING_TAIL 0x00
487 -#define TAIL_ADDR 0x001FFFF8
488 -#define RING_HEAD 0x04
489 -#define HEAD_WRAP_COUNT 0xFFE00000
490 -#define HEAD_WRAP_ONE 0x00200000
491 -#define HEAD_ADDR 0x001FFFFC
492 -#define RING_START 0x08
493 -#define START_ADDR 0x0xFFFFF000
494 -#define RING_LEN 0x0C
495 -#define RING_NR_PAGES 0x001FF000
496 -#define RING_REPORT_MASK 0x00000006
497 -#define RING_REPORT_64K 0x00000002
498 -#define RING_REPORT_128K 0x00000004
499 -#define RING_NO_REPORT 0x00000000
500 -#define RING_VALID_MASK 0x00000001
501 -#define RING_VALID 0x00000001
502 -#define RING_INVALID 0x00000000
504 -/* Instruction parser error reg:
506 -#define IPEIR 0x2088
508 -/* Scratch pad debug 0 reg:
510 -#define SCPD0 0x209c
512 -/* Error status reg:
516 -/* Secondary DMA fetch address debug reg:
518 -#define DMA_FADD_S 0x20d4
520 -/* Memory Interface Arbitration State
522 -#define MI_ARB_STATE 0x20e4
524 -/* Cache mode 0 reg.
525 - * - Manipulating render cache behaviour is central
526 - * to the concept of zone rendering, tuning this reg can help avoid
527 - * unnecessary render cache reads and even writes (for z/stencil)
528 - * at beginning and end of scene.
530 - * - To change a bit, write to this reg with a mask bit set and the
531 - * bit of interest either set or cleared. EG: (BIT<<16) | BIT to set.
533 -#define Cache_Mode_0 0x2120
534 -#define CACHE_MODE_0 0x2120
535 -#define CM0_MASK_SHIFT 16
536 -#define CM0_IZ_OPT_DISABLE (1<<6)
537 -#define CM0_ZR_OPT_DISABLE (1<<5)
538 -#define CM0_DEPTH_EVICT_DISABLE (1<<4)
539 -#define CM0_COLOR_EVICT_DISABLE (1<<3)
540 -#define CM0_DEPTH_WRITE_DISABLE (1<<1)
541 -#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
544 -/* Graphics flush control. A CPU write flushes the GWB of all writes.
545 - * The data is discarded.
547 -#define GFX_FLSH_CNTL 0x2170
549 -/* Binner control. Defines the location of the bin pointer list:
551 -#define BINCTL 0x2420
552 -#define BC_MASK (1 << 9)
554 -/* Binned scene info.
556 -#define BINSCENE 0x2428
557 -#define BS_OP_LOAD (1 << 8)
558 -#define BS_MASK (1 << 22)
560 -/* Bin command parser debug reg:
564 -/* Bin memory control debug reg:
568 -/* Bin data cache debug reg:
572 -/* Binner pointer cache debug reg:
576 -/* Binner scratch pad debug reg:
578 -#define BINSKPD 0x24f0
580 -/* HWB scratch pad debug reg:
582 -#define HWBSKPD 0x24f4
584 -/* Binner memory pool reg:
586 -#define BMP_BUFFER 0x2430
587 -#define BMP_PAGE_SIZE_4K (0 << 10)
588 -#define BMP_BUFFER_SIZE_SHIFT 1
589 -#define BMP_ENABLE (1 << 0)
591 -/* Get/put memory from the binner memory pool:
593 -#define BMP_GET 0x2438
594 -#define BMP_PUT 0x2440
595 -#define BMP_OFFSET_SHIFT 5
597 -/* 3D state packets:
599 -#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
601 -#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
602 -#define SC_UPDATE_SCISSOR (0x1<<1)
603 -#define SC_ENABLE_MASK (0x1<<0)
604 -#define SC_ENABLE (0x1<<0)
606 -#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
608 -#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
609 -#define SCI_YMIN_MASK (0xffff<<16)
610 -#define SCI_XMIN_MASK (0xffff<<0)
611 -#define SCI_YMAX_MASK (0xffff<<16)
612 -#define SCI_XMAX_MASK (0xffff<<0)
614 -#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
615 -#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
616 -#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
617 -#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
618 -#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
619 -#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
620 -#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
622 -#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
624 -#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
625 -#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
626 -#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
627 -#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
628 -#define XY_SRC_COPY_BLT_SRC_TILED (1<<15)
629 -#define XY_SRC_COPY_BLT_DST_TILED (1<<11)
631 -#define MI_BATCH_BUFFER ((0x30<<23)|1)
632 -#define MI_BATCH_BUFFER_START (0x31<<23)
633 -#define MI_BATCH_BUFFER_END (0xA<<23)
634 -#define MI_BATCH_NON_SECURE (1)
635 -#define MI_BATCH_NON_SECURE_I965 (1<<8)
637 -#define MI_WAIT_FOR_EVENT ((0x3<<23))
638 -#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
639 -#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
640 -#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
642 -#define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))
644 -#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
645 -#define ASYNC_FLIP (1<<22)
646 -#define DISPLAY_PLANE_A (0<<20)
647 -#define DISPLAY_PLANE_B (1<<20)
650 -#define DSPACNTR 0x70180
651 -#define DSPBCNTR 0x71180
652 -#define DISPPLANE_SEL_PIPE_MASK (1<<24)
654 -/* Define the region of interest for the binner:
656 -#define CMD_OP_BIN_CONTROL ((0x3<<29)|(0x1d<<24)|(0x84<<16)|4)
658 -#define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
660 -#define CMD_MI_FLUSH (0x04 << 23)
661 -#define MI_NO_WRITE_FLUSH (1 << 2)
662 -#define MI_READ_FLUSH (1 << 0)
663 -#define MI_EXE_FLUSH (1 << 1)
664 -#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
665 -#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
667 -#define BREADCRUMB_BITS 31
668 -#define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1)
670 -#define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[5])
671 -#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
673 -#define BLC_PWM_CTL 0x61254
674 -#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
676 -#define BLC_PWM_CTL2 0x61250
678 - * This is the most significant 15 bits of the number of backlight cycles in a
679 - * complete cycle of the modulated backlight control.
680 + * Reads a dword out of the status page, which is written to from the command
681 + * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
682 + * MI_STORE_DATA_IMM.
684 + * The following dwords have a reserved meaning:
685 + * 0: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
686 + * 4: ring 0 head pointer
687 + * 5: ring 1 head pointer (915-class)
688 + * 6: ring 2 head pointer (915-class)
690 - * The actual value is this field multiplied by two.
691 + * The area from dword 0x10 to 0x3ff is available for driver usage.
693 -#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
694 -#define BLM_LEGACY_MODE (1 << 16)
696 - * This is the number of cycles out of the backlight modulation cycle for which
697 - * the backlight is on.
699 - * This field must be no greater than the number of cycles in the complete
700 - * backlight modulation cycle.
702 -#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
703 -#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
705 -#define I915_GCFGC 0xf0
706 -#define I915_LOW_FREQUENCY_ENABLE (1 << 7)
707 -#define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
708 -#define I915_DISPLAY_CLOCK_333_MHZ (4 << 4)
709 -#define I915_DISPLAY_CLOCK_MASK (7 << 4)
711 -#define I855_HPLLCC 0xc0
712 -#define I855_CLOCK_CONTROL_MASK (3 << 0)
713 -#define I855_CLOCK_133_200 (0 << 0)
714 -#define I855_CLOCK_100_200 (1 << 0)
715 -#define I855_CLOCK_100_133 (2 << 0)
716 -#define I855_CLOCK_166_250 (3 << 0)
720 -#define VCLK2_VCO_M 0x6008 /* treat as 16 bit? (includes msbs) */
721 -#define VCLK2_VCO_N 0x600a
722 -#define VCLK2_VCO_DIV_SEL 0x6012
724 -#define VCLK_DIVISOR_VGA0 0x6000
725 -#define VCLK_DIVISOR_VGA1 0x6004
726 -#define VCLK_POST_DIV 0x6010
727 -/** Selects a post divisor of 4 instead of 2. */
728 -# define VGA1_PD_P2_DIV_4 (1 << 15)
729 -/** Overrides the p2 post divisor field */
730 -# define VGA1_PD_P1_DIV_2 (1 << 13)
731 -# define VGA1_PD_P1_SHIFT 8
732 -/** P1 value is 2 greater than this field */
733 -# define VGA1_PD_P1_MASK (0x1f << 8)
734 -/** Selects a post divisor of 4 instead of 2. */
735 -# define VGA0_PD_P2_DIV_4 (1 << 7)
736 -/** Overrides the p2 post divisor field */
737 -# define VGA0_PD_P1_DIV_2 (1 << 5)
738 -# define VGA0_PD_P1_SHIFT 0
739 -/** P1 value is 2 greater than this field */
740 -# define VGA0_PD_P1_MASK (0x1f << 0)
742 -/* PCI D state control register */
743 -#define D_STATE 0x6104
744 -#define DSPCLK_GATE_D 0x6200
746 -/* I830 CRTC registers */
747 -#define HTOTAL_A 0x60000
748 -#define HBLANK_A 0x60004
749 -#define HSYNC_A 0x60008
750 -#define VTOTAL_A 0x6000c
751 -#define VBLANK_A 0x60010
752 -#define VSYNC_A 0x60014
753 -#define PIPEASRC 0x6001c
754 -#define BCLRPAT_A 0x60020
755 -#define VSYNCSHIFT_A 0x60028
757 -#define HTOTAL_B 0x61000
758 -#define HBLANK_B 0x61004
759 -#define HSYNC_B 0x61008
760 -#define VTOTAL_B 0x6100c
761 -#define VBLANK_B 0x61010
762 -#define VSYNC_B 0x61014
763 -#define PIPEBSRC 0x6101c
764 -#define BCLRPAT_B 0x61020
765 -#define VSYNCSHIFT_B 0x61028
767 -#define PP_STATUS 0x61200
768 -# define PP_ON (1 << 31)
770 - * Indicates that all dependencies of the panel are on:
774 - * - LVDS/DVOB/DVOC on
776 -# define PP_READY (1 << 30)
777 -# define PP_SEQUENCE_NONE (0 << 28)
778 -# define PP_SEQUENCE_ON (1 << 28)
779 -# define PP_SEQUENCE_OFF (2 << 28)
780 -# define PP_SEQUENCE_MASK 0x30000000
781 -#define PP_CONTROL 0x61204
782 -# define POWER_TARGET_ON (1 << 0)
784 -#define LVDSPP_ON 0x61208
785 -#define LVDSPP_OFF 0x6120c
786 -#define PP_CYCLE 0x61210
788 -#define PFIT_CONTROL 0x61230
789 -# define PFIT_ENABLE (1 << 31)
790 -# define PFIT_PIPE_MASK (3 << 29)
791 -# define PFIT_PIPE_SHIFT 29
792 -# define VERT_INTERP_DISABLE (0 << 10)
793 -# define VERT_INTERP_BILINEAR (1 << 10)
794 -# define VERT_INTERP_MASK (3 << 10)
795 -# define VERT_AUTO_SCALE (1 << 9)
796 -# define HORIZ_INTERP_DISABLE (0 << 6)
797 -# define HORIZ_INTERP_BILINEAR (1 << 6)
798 -# define HORIZ_INTERP_MASK (3 << 6)
799 -# define HORIZ_AUTO_SCALE (1 << 5)
800 -# define PANEL_8TO6_DITHER_ENABLE (1 << 3)
802 -#define PFIT_PGM_RATIOS 0x61234
803 -# define PFIT_VERT_SCALE_MASK 0xfff00000
804 -# define PFIT_HORIZ_SCALE_MASK 0x0000fff0
806 -#define PFIT_AUTO_RATIOS 0x61238
809 -#define DPLL_A 0x06014
810 -#define DPLL_B 0x06018
811 -# define DPLL_VCO_ENABLE (1 << 31)
812 -# define DPLL_DVO_HIGH_SPEED (1 << 30)
813 -# define DPLL_SYNCLOCK_ENABLE (1 << 29)
814 -# define DPLL_VGA_MODE_DIS (1 << 28)
815 -# define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
816 -# define DPLLB_MODE_LVDS (2 << 26) /* i915 */
817 -# define DPLL_MODE_MASK (3 << 26)
818 -# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
819 -# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
820 -# define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
821 -# define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
822 -# define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
823 -# define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
825 - * The i830 generation, in DAC/serial mode, defines p1 as two plus this
826 - * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set.
828 -# define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
830 - * The i830 generation, in LVDS mode, defines P1 as the bit number set within
831 - * this field (only one bit may be set).
833 -# define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
834 -# define DPLL_FPA01_P1_POST_DIV_SHIFT 16
835 -# define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */
836 -# define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
837 -# define PLL_REF_INPUT_DREFCLK (0 << 13)
838 -# define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
839 -# define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
840 -# define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
841 -# define PLL_REF_INPUT_MASK (3 << 13)
842 -# define PLL_LOAD_PULSE_PHASE_SHIFT 9
844 - * Parallel to Serial Load Pulse phase selection.
845 - * Selects the phase for the 10X DPLL clock for the PCIe
846 - * digital display port. The range is 4 to 13; 10 or more
847 - * is just a flip delay. The default is 6
849 -# define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
850 -# define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
853 - * SDVO multiplier for 945G/GM. Not used on 965.
855 - * \sa DPLL_MD_UDI_MULTIPLIER_MASK
857 -# define SDVO_MULTIPLIER_MASK 0x000000ff
858 -# define SDVO_MULTIPLIER_SHIFT_HIRES 4
859 -# define SDVO_MULTIPLIER_SHIFT_VGA 0
861 -/** @defgroup DPLL_MD
864 -/** Pipe A SDVO/UDI clock multiplier/divider register for G965. */
865 -#define DPLL_A_MD 0x0601c
866 -/** Pipe B SDVO/UDI clock multiplier/divider register for G965. */
867 -#define DPLL_B_MD 0x06020
869 - * UDI pixel divider, controlling how many pixels are stuffed into a packet.
871 - * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
873 -# define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
874 -# define DPLL_MD_UDI_DIVIDER_SHIFT 24
875 -/** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
876 -# define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
877 -# define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
879 - * SDVO/UDI pixel multiplier.
881 - * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
882 - * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
883 - * modes, the bus rate would be below the limits, so SDVO allows for stuffing
884 - * dummy bytes in the datastream at an increased clock rate, with both sides of
885 - * the link knowing how many bytes are fill.
887 - * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
888 - * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
889 - * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
890 - * through an SDVO command.
892 - * This register field has values of multiplication factor minus 1, with
893 - * a maximum multiplier of 5 for SDVO.
895 -# define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
896 -# define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
897 -/** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
898 - * This best be set to the default value (3) or the CRT won't work. No,
899 - * I don't entirely understand what this does...
901 -# define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
902 -# define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
905 -#define DPLL_TEST 0x606c
906 -# define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
907 -# define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
908 -# define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
909 -# define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
910 -# define DPLLB_TEST_N_BYPASS (1 << 19)
911 -# define DPLLB_TEST_M_BYPASS (1 << 18)
912 -# define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
913 -# define DPLLA_TEST_N_BYPASS (1 << 3)
914 -# define DPLLA_TEST_M_BYPASS (1 << 2)
915 -# define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
917 -#define ADPA 0x61100
918 -#define ADPA_DAC_ENABLE (1<<31)
919 -#define ADPA_DAC_DISABLE 0
920 -#define ADPA_PIPE_SELECT_MASK (1<<30)
921 -#define ADPA_PIPE_A_SELECT 0
922 -#define ADPA_PIPE_B_SELECT (1<<30)
923 -#define ADPA_USE_VGA_HVPOLARITY (1<<15)
924 -#define ADPA_SETS_HVPOLARITY 0
925 -#define ADPA_VSYNC_CNTL_DISABLE (1<<11)
926 -#define ADPA_VSYNC_CNTL_ENABLE 0
927 -#define ADPA_HSYNC_CNTL_DISABLE (1<<10)
928 -#define ADPA_HSYNC_CNTL_ENABLE 0
929 -#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
930 -#define ADPA_VSYNC_ACTIVE_LOW 0
931 -#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
932 -#define ADPA_HSYNC_ACTIVE_LOW 0
934 -#define FPA0 0x06040
935 -#define FPA1 0x06044
936 -#define FPB0 0x06048
937 -#define FPB1 0x0604c
938 -# define FP_N_DIV_MASK 0x003f0000
939 -# define FP_N_DIV_SHIFT 16
940 -# define FP_M1_DIV_MASK 0x00003f00
941 -# define FP_M1_DIV_SHIFT 8
942 -# define FP_M2_DIV_MASK 0x0000003f
943 -# define FP_M2_DIV_SHIFT 0
946 -#define PORT_HOTPLUG_EN 0x61110
947 -# define SDVOB_HOTPLUG_INT_EN (1 << 26)
948 -# define SDVOC_HOTPLUG_INT_EN (1 << 25)
949 -# define TV_HOTPLUG_INT_EN (1 << 18)
950 -# define CRT_HOTPLUG_INT_EN (1 << 9)
951 -# define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
953 -#define PORT_HOTPLUG_STAT 0x61114
954 -# define CRT_HOTPLUG_INT_STATUS (1 << 11)
955 -# define TV_HOTPLUG_INT_STATUS (1 << 10)
956 -# define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
957 -# define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
958 -# define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
959 -# define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
960 -# define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
961 -# define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
963 -#define SDVOB 0x61140
964 -#define SDVOC 0x61160
965 -#define SDVO_ENABLE (1 << 31)
966 -#define SDVO_PIPE_B_SELECT (1 << 30)
967 -#define SDVO_STALL_SELECT (1 << 29)
968 -#define SDVO_INTERRUPT_ENABLE (1 << 26)
970 - * 915G/GM SDVO pixel multiplier.
972 - * Programmed value is multiplier - 1, up to 5x.
974 - * \sa DPLL_MD_UDI_MULTIPLIER_MASK
976 -#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
977 -#define SDVO_PORT_MULTIPLY_SHIFT 23
978 -#define SDVO_PHASE_SELECT_MASK (15 << 19)
979 -#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
980 -#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
981 -#define SDVOC_GANG_MODE (1 << 16)
982 -#define SDVO_BORDER_ENABLE (1 << 7)
983 -#define SDVOB_PCIE_CONCURRENCY (1 << 3)
984 -#define SDVO_DETECTED (1 << 2)
985 -/* Bits to be preserved when writing */
986 -#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14))
987 -#define SDVOC_PRESERVE_MASK (1 << 17)
993 - * This register controls the LVDS output enable, pipe selection, and data
994 - * format selection.
996 - * All of the clock/data pairs are force powered down by power sequencing.
998 -#define LVDS 0x61180
1000 - * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
1001 - * the DPLL semantics change when the LVDS is assigned to that pipe.
1003 -# define LVDS_PORT_EN (1 << 31)
1004 -/** Selects pipe B for LVDS data. Must be set on pre-965. */
1005 -# define LVDS_PIPEB_SELECT (1 << 30)
1008 - * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
1011 -# define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
1012 -# define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
1013 -# define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
1015 - * Controls the A3 data pair, which contains the additional LSBs for 24 bit
1016 - * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
1019 -# define LVDS_A3_POWER_MASK (3 << 6)
1020 -# define LVDS_A3_POWER_DOWN (0 << 6)
1021 -# define LVDS_A3_POWER_UP (3 << 6)
1023 - * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
1026 -# define LVDS_CLKB_POWER_MASK (3 << 4)
1027 -# define LVDS_CLKB_POWER_DOWN (0 << 4)
1028 -# define LVDS_CLKB_POWER_UP (3 << 4)
1031 - * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
1032 - * setting for whether we are in dual-channel mode. The B3 pair will
1033 - * additionally only be powered up when LVDS_A3_POWER_UP is set.
1035 -# define LVDS_B0B3_POWER_MASK (3 << 2)
1036 -# define LVDS_B0B3_POWER_DOWN (0 << 2)
1037 -# define LVDS_B0B3_POWER_UP (3 << 2)
1039 -#define PIPEACONF 0x70008
1040 -#define PIPEACONF_ENABLE (1<<31)
1041 -#define PIPEACONF_DISABLE 0
1042 -#define PIPEACONF_DOUBLE_WIDE (1<<30)
1043 -#define I965_PIPECONF_ACTIVE (1<<30)
1044 -#define PIPEACONF_SINGLE_WIDE 0
1045 -#define PIPEACONF_PIPE_UNLOCKED 0
1046 -#define PIPEACONF_PIPE_LOCKED (1<<25)
1047 -#define PIPEACONF_PALETTE 0
1048 -#define PIPEACONF_GAMMA (1<<24)
1049 -#define PIPECONF_FORCE_BORDER (1<<25)
1050 -#define PIPECONF_PROGRESSIVE (0 << 21)
1051 -#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
1052 -#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
1054 -#define DSPARB 0x70030
1055 -#define DSPARB_CSTART_MASK (0x7f << 7)
1056 -#define DSPARB_CSTART_SHIFT 7
1057 -#define DSPARB_BSTART_MASK (0x7f)
1058 -#define DSPARB_BSTART_SHIFT 0
1060 -#define PIPEBCONF 0x71008
1061 -#define PIPEBCONF_ENABLE (1<<31)
1062 -#define PIPEBCONF_DISABLE 0
1063 -#define PIPEBCONF_DOUBLE_WIDE (1<<30)
1064 -#define PIPEBCONF_DISABLE 0
1065 -#define PIPEBCONF_GAMMA (1<<24)
1066 -#define PIPEBCONF_PALETTE 0
1068 -#define PIPEBGCMAXRED 0x71010
1069 -#define PIPEBGCMAXGREEN 0x71014
1070 -#define PIPEBGCMAXBLUE 0x71018
1071 -#define PIPEBSTAT 0x71024
1072 -#define PIPEBFRAMEHIGH 0x71040
1073 -#define PIPEBFRAMEPIXEL 0x71044
1075 -#define DSPACNTR 0x70180
1076 -#define DSPBCNTR 0x71180
1077 -#define DISPLAY_PLANE_ENABLE (1<<31)
1078 -#define DISPLAY_PLANE_DISABLE 0
1079 -#define DISPPLANE_GAMMA_ENABLE (1<<30)
1080 -#define DISPPLANE_GAMMA_DISABLE 0
1081 -#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
1082 -#define DISPPLANE_8BPP (0x2<<26)
1083 -#define DISPPLANE_15_16BPP (0x4<<26)
1084 -#define DISPPLANE_16BPP (0x5<<26)
1085 -#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
1086 -#define DISPPLANE_32BPP (0x7<<26)
1087 -#define DISPPLANE_STEREO_ENABLE (1<<25)
1088 -#define DISPPLANE_STEREO_DISABLE 0
1089 -#define DISPPLANE_SEL_PIPE_MASK (1<<24)
1090 -#define DISPPLANE_SEL_PIPE_A 0
1091 -#define DISPPLANE_SEL_PIPE_B (1<<24)
1092 -#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
1093 -#define DISPPLANE_SRC_KEY_DISABLE 0
1094 -#define DISPPLANE_LINE_DOUBLE (1<<20)
1095 -#define DISPPLANE_NO_LINE_DOUBLE 0
1096 -#define DISPPLANE_STEREO_POLARITY_FIRST 0
1097 -#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
1099 -#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
1100 -#define DISPPLANE_ALPHA_TRANS_DISABLE 0
1101 -#define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0
1102 -#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
1104 -#define DSPABASE 0x70184
1105 -#define DSPASTRIDE 0x70188
1107 -#define DSPBBASE 0x71184
1108 -#define DSPBADDR DSPBBASE
1109 -#define DSPBSTRIDE 0x71188
1111 -#define DSPAKEYVAL 0x70194
1112 -#define DSPAKEYMASK 0x70198
1114 -#define DSPAPOS 0x7018C /* reserved */
1115 -#define DSPASIZE 0x70190
1116 -#define DSPBPOS 0x7118C
1117 -#define DSPBSIZE 0x71190
1119 -#define DSPASURF 0x7019C
1120 -#define DSPATILEOFF 0x701A4
1122 -#define DSPBSURF 0x7119C
1123 -#define DSPBTILEOFF 0x711A4
1125 -#define VGACNTRL 0x71400
1126 -# define VGA_DISP_DISABLE (1 << 31)
1127 -# define VGA_2X_MODE (1 << 30)
1128 -# define VGA_PIPE_B_SELECT (1 << 29)
1131 - * Some BIOS scratch area registers. The 845 (and 830?) store the amount
1132 - * of video memory available to the BIOS in SWF1.
1135 -#define SWF0 0x71410
1138 - * 855 scratch registers.
1140 -#define SWF10 0x70410
1142 -#define SWF30 0x72414
1145 - * Overlay registers. These are overlay registers accessed via MMIO.
1146 - * Those loaded via the overlay register page are defined in i830_video.c.
1148 -#define OVADD 0x30000
1150 -#define DOVSTA 0x30008
1151 -#define OC_BUF (0x3<<20)
1152 +#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
1153 +#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, 5)
1155 -#define OGAMC5 0x30010
1156 -#define OGAMC4 0x30014
1157 -#define OGAMC3 0x30018
1158 -#define OGAMC2 0x3001c
1159 -#define OGAMC1 0x30020
1160 -#define OGAMC0 0x30024
1162 - * Palette registers
1164 -#define PALETTE_A 0x0a000
1165 -#define PALETTE_B 0x0a800
1166 +extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
1168 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1169 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1170 --- a/drivers/gpu/drm/i915/i915_irq.c
1171 +++ b/drivers/gpu/drm/i915/i915_irq.c
1173 #include "i915_drm.h"
1174 #include "i915_drv.h"
1176 -#define USER_INT_FLAG (1<<1)
1177 -#define VSYNC_PIPEB_FLAG (1<<5)
1178 -#define VSYNC_PIPEA_FLAG (1<<7)
1180 #define MAX_NOPID ((u32)~0)
1183 @@ -236,40 +232,43 @@ irqreturn_t i915_driver_irq_handler(DRM_
1185 u32 pipea_stats, pipeb_stats;
1187 - pipea_stats = I915_READ(I915REG_PIPEASTAT);
1188 - pipeb_stats = I915_READ(I915REG_PIPEBSTAT);
1189 + pipea_stats = I915_READ(PIPEASTAT);
1190 + pipeb_stats = I915_READ(PIPEBSTAT);
1192 - temp = I915_READ16(I915REG_INT_IDENTITY_R);
1193 + temp = I915_READ16(IIR);
1195 - temp &= (USER_INT_FLAG | VSYNC_PIPEA_FLAG | VSYNC_PIPEB_FLAG);
1196 + temp &= (I915_USER_INTERRUPT |
1197 + I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1198 + I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT);
1200 DRM_DEBUG("%s flag=%08x\n", __FUNCTION__, temp);
1205 - I915_WRITE16(I915REG_INT_IDENTITY_R, temp);
1206 - (void) I915_READ16(I915REG_INT_IDENTITY_R);
1207 + I915_WRITE16(IIR, temp);
1208 + (void) I915_READ16(IIR);
1209 DRM_READMEMORYBARRIER();
1211 dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1213 - if (temp & USER_INT_FLAG)
1214 + if (temp & I915_USER_INTERRUPT)
1215 DRM_WAKEUP(&dev_priv->irq_queue);
1217 - if (temp & (VSYNC_PIPEA_FLAG | VSYNC_PIPEB_FLAG)) {
1218 + if (temp & (I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1219 + I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT)) {
1220 int vblank_pipe = dev_priv->vblank_pipe;
1223 (DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B))
1224 == (DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B)) {
1225 - if (temp & VSYNC_PIPEA_FLAG)
1226 + if (temp & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT)
1227 atomic_inc(&dev->vbl_received);
1228 - if (temp & VSYNC_PIPEB_FLAG)
1229 + if (temp & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT)
1230 atomic_inc(&dev->vbl_received2);
1231 - } else if (((temp & VSYNC_PIPEA_FLAG) &&
1232 + } else if (((temp & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) &&
1233 (vblank_pipe & DRM_I915_VBLANK_PIPE_A)) ||
1234 - ((temp & VSYNC_PIPEB_FLAG) &&
1235 + ((temp & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) &&
1236 (vblank_pipe & DRM_I915_VBLANK_PIPE_B)))
1237 atomic_inc(&dev->vbl_received);
1239 @@ -278,12 +277,12 @@ irqreturn_t i915_driver_irq_handler(DRM_
1241 if (dev_priv->swaps_pending > 0)
1242 drm_locked_tasklet(dev, i915_vblank_tasklet);
1243 - I915_WRITE(I915REG_PIPEASTAT,
1244 + I915_WRITE(PIPEASTAT,
1245 pipea_stats|I915_VBLANK_INTERRUPT_ENABLE|
1246 - I915_VBLANK_CLEAR);
1247 - I915_WRITE(I915REG_PIPEBSTAT,
1248 + PIPE_VBLANK_INTERRUPT_STATUS);
1249 + I915_WRITE(PIPEBSTAT,
1250 pipeb_stats|I915_VBLANK_INTERRUPT_ENABLE|
1251 - I915_VBLANK_CLEAR);
1252 + PIPE_VBLANK_INTERRUPT_STATUS);
1256 @@ -304,12 +303,12 @@ static int i915_emit_irq(struct drm_devi
1257 dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1;
1260 - OUT_RING(CMD_STORE_DWORD_IDX);
1262 + OUT_RING(MI_STORE_DWORD_INDEX);
1263 + OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
1264 OUT_RING(dev_priv->counter);
1267 - OUT_RING(GFX_OP_USER_INTERRUPT);
1268 + OUT_RING(MI_USER_INTERRUPT);
1271 return dev_priv->counter;
1272 @@ -421,11 +420,11 @@ static void i915_enable_interrupt (struc
1275 if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A)
1276 - flag |= VSYNC_PIPEA_FLAG;
1277 + flag |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1278 if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B)
1279 - flag |= VSYNC_PIPEB_FLAG;
1280 + flag |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1282 - I915_WRITE16(I915REG_INT_ENABLE_R, USER_INT_FLAG | flag);
1283 + I915_WRITE16(IER, I915_USER_INTERRUPT | flag);
1286 /* Set the vblank monitor pipe
1287 @@ -465,11 +464,11 @@ int i915_vblank_pipe_get(struct drm_devi
1291 - flag = I915_READ(I915REG_INT_ENABLE_R);
1292 + flag = I915_READ(IER);
1294 - if (flag & VSYNC_PIPEA_FLAG)
1295 + if (flag & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT)
1296 pipe->pipe |= DRM_I915_VBLANK_PIPE_A;
1297 - if (flag & VSYNC_PIPEB_FLAG)
1298 + if (flag & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT)
1299 pipe->pipe |= DRM_I915_VBLANK_PIPE_B;
1302 @@ -587,9 +586,9 @@ void i915_driver_irq_preinstall(struct d
1304 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1306 - I915_WRITE16(I915REG_HWSTAM, 0xfffe);
1307 - I915_WRITE16(I915REG_INT_MASK_R, 0x0);
1308 - I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);
1309 + I915_WRITE16(HWSTAM, 0xfffe);
1310 + I915_WRITE16(IMR, 0x0);
1311 + I915_WRITE16(IER, 0x0);
1314 void i915_driver_irq_postinstall(struct drm_device * dev)
1315 @@ -614,10 +613,10 @@ void i915_driver_irq_uninstall(struct dr
1319 - I915_WRITE16(I915REG_HWSTAM, 0xffff);
1320 - I915_WRITE16(I915REG_INT_MASK_R, 0xffff);
1321 - I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);
1322 + I915_WRITE16(HWSTAM, 0xffff);
1323 + I915_WRITE16(IMR, 0xffff);
1324 + I915_WRITE16(IER, 0x0);
1326 - temp = I915_READ16(I915REG_INT_IDENTITY_R);
1327 - I915_WRITE16(I915REG_INT_IDENTITY_R, temp);
1328 + temp = I915_READ16(IIR);
1329 + I915_WRITE16(IIR, temp);
1332 +++ b/drivers/gpu/drm/i915/i915_reg.h
1334 +/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
1335 + * All Rights Reserved.
1337 + * Permission is hereby granted, free of charge, to any person obtaining a
1338 + * copy of this software and associated documentation files (the
1339 + * "Software"), to deal in the Software without restriction, including
1340 + * without limitation the rights to use, copy, modify, merge, publish,
1341 + * distribute, sub license, and/or sell copies of the Software, and to
1342 + * permit persons to whom the Software is furnished to do so, subject to
1343 + * the following conditions:
1345 + * The above copyright notice and this permission notice (including the
1346 + * next paragraph) shall be included in all copies or substantial portions
1347 + * of the Software.
1349 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
1350 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
1351 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
1352 + * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
1353 + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
1354 + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
1355 + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
1358 +#ifndef _I915_REG_H_
1359 +#define _I915_REG_H_
1361 +/* MCH MMIO space */
1362 +/** 915-945 and GM965 MCH register controlling DRAM channel access */
1364 +#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
1365 +#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
1366 +#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
1367 +#define DCC_ADDRESSING_MODE_MASK (3 << 0)
1368 +#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
1370 +/** 965 MCH register controlling DRAM channel configuration */
1371 +#define CHDECMISC 0x111
1372 +#define CHDECMISC_FLEXMEMORY (1 << 1)
1375 + * The Bridge device's PCI config space has information about the
1376 + * fb aperture size and the amount of pre-reserved memory.
1378 +#define INTEL_GMCH_CTRL 0x52
1379 +#define INTEL_GMCH_ENABLED 0x4
1380 +#define INTEL_GMCH_MEM_MASK 0x1
1381 +#define INTEL_GMCH_MEM_64M 0x1
1382 +#define INTEL_GMCH_MEM_128M 0
1384 +#define INTEL_855_GMCH_GMS_MASK (0x7 << 4)
1385 +#define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4)
1386 +#define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4)
1387 +#define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4)
1388 +#define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4)
1389 +#define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4)
1390 +#define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4)
1392 +#define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4)
1393 +#define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4)
1395 +/* PCI config space */
1397 +#define HPLLCC 0xc0 /* 855 only */
1398 +#define GC_CLOCK_CONTROL_MASK (3 << 0)
1399 +#define GC_CLOCK_133_200 (0 << 0)
1400 +#define GC_CLOCK_100_200 (1 << 0)
1401 +#define GC_CLOCK_100_133 (2 << 0)
1402 +#define GC_CLOCK_166_250 (3 << 0)
1403 +#define GCFGC 0xf0 /* 915+ only */
1404 +#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
1405 +#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
1406 +#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
1407 +#define GC_DISPLAY_CLOCK_MASK (7 << 4)
1412 +#define VGA_ST01_MDA 0x3ba
1413 +#define VGA_ST01_CGA 0x3da
1415 +#define VGA_MSR_WRITE 0x3c2
1416 +#define VGA_MSR_READ 0x3cc
1417 +#define VGA_MSR_MEM_EN (1<<1)
1418 +#define VGA_MSR_CGA_MODE (1<<0)
1420 +#define VGA_SR_INDEX 0x3c4
1421 +#define VGA_SR_DATA 0x3c5
1423 +#define VGA_AR_INDEX 0x3c0
1424 +#define VGA_AR_VID_EN (1<<5)
1425 +#define VGA_AR_DATA_WRITE 0x3c0
1426 +#define VGA_AR_DATA_READ 0x3c1
1428 +#define VGA_GR_INDEX 0x3ce
1429 +#define VGA_GR_DATA 0x3cf
1431 +#define VGA_GR_MEM_READ_MODE_SHIFT 3
1432 +#define VGA_GR_MEM_READ_MODE_PLANE 1
1434 +#define VGA_GR_MEM_MODE_MASK 0xc
1435 +#define VGA_GR_MEM_MODE_SHIFT 2
1436 +#define VGA_GR_MEM_A0000_AFFFF 0
1437 +#define VGA_GR_MEM_A0000_BFFFF 1
1438 +#define VGA_GR_MEM_B0000_B7FFF 2
1439 +#define VGA_GR_MEM_B0000_BFFFF 3
1441 +#define VGA_DACMASK 0x3c6
1442 +#define VGA_DACRX 0x3c7
1443 +#define VGA_DACWX 0x3c8
1444 +#define VGA_DACDATA 0x3c9
1446 +#define VGA_CR_INDEX_MDA 0x3b4
1447 +#define VGA_CR_DATA_MDA 0x3b5
1448 +#define VGA_CR_INDEX_CGA 0x3d4
1449 +#define VGA_CR_DATA_CGA 0x3d5
1452 + * Memory interface instructions used by the kernel
1454 +#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
1456 +#define MI_NOOP MI_INSTR(0, 0)
1457 +#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
1458 +#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
1459 +#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
1460 +#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
1461 +#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
1462 +#define MI_FLUSH MI_INSTR(0x04, 0)
1463 +#define MI_READ_FLUSH (1 << 0)
1464 +#define MI_EXE_FLUSH (1 << 1)
1465 +#define MI_NO_WRITE_FLUSH (1 << 2)
1466 +#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
1467 +#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
1468 +#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
1469 +#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
1470 +#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
1471 +#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
1472 +#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
1473 +#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
1474 +#define MI_STORE_DWORD_INDEX_SHIFT 2
1475 +#define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1)
1476 +#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
1477 +#define MI_BATCH_NON_SECURE (1)
1478 +#define MI_BATCH_NON_SECURE_I965 (1<<8)
1479 +#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
1482 + * 3D instructions used by the kernel
1484 +#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
1486 +#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
1487 +#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
1488 +#define SC_UPDATE_SCISSOR (0x1<<1)
1489 +#define SC_ENABLE_MASK (0x1<<0)
1490 +#define SC_ENABLE (0x1<<0)
1491 +#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
1492 +#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
1493 +#define SCI_YMIN_MASK (0xffff<<16)
1494 +#define SCI_XMIN_MASK (0xffff<<0)
1495 +#define SCI_YMAX_MASK (0xffff<<16)
1496 +#define SCI_XMAX_MASK (0xffff<<0)
1497 +#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
1498 +#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
1499 +#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
1500 +#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
1501 +#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
1502 +#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
1503 +#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
1504 +#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
1505 +#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
1506 +#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
1507 +#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
1508 +#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
1509 +#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
1510 +#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
1511 +#define BLT_DEPTH_8 (0<<24)
1512 +#define BLT_DEPTH_16_565 (1<<24)
1513 +#define BLT_DEPTH_16_1555 (2<<24)
1514 +#define BLT_DEPTH_32 (3<<24)
1515 +#define BLT_ROP_GXCOPY (0xcc<<16)
1516 +#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
1517 +#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
1518 +#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
1519 +#define ASYNC_FLIP (1<<22)
1520 +#define DISPLAY_PLANE_A (0<<20)
1521 +#define DISPLAY_PLANE_B (1<<20)
1524 + * Instruction and interrupt control regs
1527 +#define PRB0_TAIL 0x02030
1528 +#define PRB0_HEAD 0x02034
1529 +#define PRB0_START 0x02038
1530 +#define PRB0_CTL 0x0203c
1531 +#define TAIL_ADDR 0x001FFFF8
1532 +#define HEAD_WRAP_COUNT 0xFFE00000
1533 +#define HEAD_WRAP_ONE 0x00200000
1534 +#define HEAD_ADDR 0x001FFFFC
1535 +#define RING_NR_PAGES 0x001FF000
1536 +#define RING_REPORT_MASK 0x00000006
1537 +#define RING_REPORT_64K 0x00000002
1538 +#define RING_REPORT_128K 0x00000004
1539 +#define RING_NO_REPORT 0x00000000
1540 +#define RING_VALID_MASK 0x00000001
1541 +#define RING_VALID 0x00000001
1542 +#define RING_INVALID 0x00000000
1543 +#define PRB1_TAIL 0x02040 /* 915+ only */
1544 +#define PRB1_HEAD 0x02044 /* 915+ only */
1545 +#define PRB1_START 0x02048 /* 915+ only */
1546 +#define PRB1_CTL 0x0204c /* 915+ only */
1547 +#define ACTHD_I965 0x02074
1548 +#define HWS_PGA 0x02080
1549 +#define HWS_ADDRESS_MASK 0xfffff000
1550 +#define HWS_START_ADDRESS_SHIFT 4
1551 +#define IPEIR 0x02088
1552 +#define NOPID 0x02094
1553 +#define HWSTAM 0x02098
1554 +#define SCPD0 0x0209c /* 915+ only */
1555 +#define IER 0x020a0
1556 +#define IIR 0x020a4
1557 +#define IMR 0x020a8
1558 +#define ISR 0x020ac
1559 +#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
1560 +#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
1561 +#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
1562 +#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14)
1563 +#define I915_HWB_OOM_INTERRUPT (1<<13)
1564 +#define I915_SYNC_STATUS_INTERRUPT (1<<12)
1565 +#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
1566 +#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
1567 +#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
1568 +#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
1569 +#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
1570 +#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
1571 +#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
1572 +#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
1573 +#define I915_DEBUG_INTERRUPT (1<<2)
1574 +#define I915_USER_INTERRUPT (1<<1)
1575 +#define I915_ASLE_INTERRUPT (1<<0)
1576 +#define EIR 0x020b0
1577 +#define EMR 0x020b4
1578 +#define ESR 0x020b8
1579 +#define INSTPM 0x020c0
1580 +#define ACTHD 0x020c8
1581 +#define FW_BLC 0x020d8
1582 +#define FW_BLC_SELF 0x020e0 /* 915+ only */
1583 +#define MI_ARB_STATE 0x020e4 /* 915+ only */
1584 +#define CACHE_MODE_0 0x02120 /* 915+ only */
1585 +#define CM0_MASK_SHIFT 16
1586 +#define CM0_IZ_OPT_DISABLE (1<<6)
1587 +#define CM0_ZR_OPT_DISABLE (1<<5)
1588 +#define CM0_DEPTH_EVICT_DISABLE (1<<4)
1589 +#define CM0_COLOR_EVICT_DISABLE (1<<3)
1590 +#define CM0_DEPTH_WRITE_DISABLE (1<<1)
1591 +#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
1592 +#define GFX_FLSH_CNTL 0x02170 /* 915+ only */
1595 + * Framebuffer compression (915+ only)
1598 +#define FBC_CFB_BASE 0x03200 /* 4k page aligned */
1599 +#define FBC_LL_BASE 0x03204 /* 4k page aligned */
1600 +#define FBC_CONTROL 0x03208
1601 +#define FBC_CTL_EN (1<<31)
1602 +#define FBC_CTL_PERIODIC (1<<30)
1603 +#define FBC_CTL_INTERVAL_SHIFT (16)
1604 +#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
1605 +#define FBC_CTL_STRIDE_SHIFT (5)
1606 +#define FBC_CTL_FENCENO (1<<0)
1607 +#define FBC_COMMAND 0x0320c
1608 +#define FBC_CMD_COMPRESS (1<<0)
1609 +#define FBC_STATUS 0x03210
1610 +#define FBC_STAT_COMPRESSING (1<<31)
1611 +#define FBC_STAT_COMPRESSED (1<<30)
1612 +#define FBC_STAT_MODIFIED (1<<29)
1613 +#define FBC_STAT_CURRENT_LINE (1<<0)
1614 +#define FBC_CONTROL2 0x03214
1615 +#define FBC_CTL_FENCE_DBL (0<<4)
1616 +#define FBC_CTL_IDLE_IMM (0<<2)
1617 +#define FBC_CTL_IDLE_FULL (1<<2)
1618 +#define FBC_CTL_IDLE_LINE (2<<2)
1619 +#define FBC_CTL_IDLE_DEBUG (3<<2)
1620 +#define FBC_CTL_CPU_FENCE (1<<1)
1621 +#define FBC_CTL_PLANEA (0<<0)
1622 +#define FBC_CTL_PLANEB (1<<0)
1623 +#define FBC_FENCE_OFF 0x0321b
1625 +#define FBC_LL_SIZE (1536)
1630 +#define GPIOA 0x5010
1631 +#define GPIOB 0x5014
1632 +#define GPIOC 0x5018
1633 +#define GPIOD 0x501c
1634 +#define GPIOE 0x5020
1635 +#define GPIOF 0x5024
1636 +#define GPIOG 0x5028
1637 +#define GPIOH 0x502c
1638 +# define GPIO_CLOCK_DIR_MASK (1 << 0)
1639 +# define GPIO_CLOCK_DIR_IN (0 << 1)
1640 +# define GPIO_CLOCK_DIR_OUT (1 << 1)
1641 +# define GPIO_CLOCK_VAL_MASK (1 << 2)
1642 +# define GPIO_CLOCK_VAL_OUT (1 << 3)
1643 +# define GPIO_CLOCK_VAL_IN (1 << 4)
1644 +# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
1645 +# define GPIO_DATA_DIR_MASK (1 << 8)
1646 +# define GPIO_DATA_DIR_IN (0 << 9)
1647 +# define GPIO_DATA_DIR_OUT (1 << 9)
1648 +# define GPIO_DATA_VAL_MASK (1 << 10)
1649 +# define GPIO_DATA_VAL_OUT (1 << 11)
1650 +# define GPIO_DATA_VAL_IN (1 << 12)
1651 +# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
1654 + * Clock control & power management
1657 +#define VGA0 0x6000
1658 +#define VGA1 0x6004
1659 +#define VGA_PD 0x6010
1660 +#define VGA0_PD_P2_DIV_4 (1 << 7)
1661 +#define VGA0_PD_P1_DIV_2 (1 << 5)
1662 +#define VGA0_PD_P1_SHIFT 0
1663 +#define VGA0_PD_P1_MASK (0x1f << 0)
1664 +#define VGA1_PD_P2_DIV_4 (1 << 15)
1665 +#define VGA1_PD_P1_DIV_2 (1 << 13)
1666 +#define VGA1_PD_P1_SHIFT 8
1667 +#define VGA1_PD_P1_MASK (0x1f << 8)
1668 +#define DPLL_A 0x06014
1669 +#define DPLL_B 0x06018
1670 +#define DPLL_VCO_ENABLE (1 << 31)
1671 +#define DPLL_DVO_HIGH_SPEED (1 << 30)
1672 +#define DPLL_SYNCLOCK_ENABLE (1 << 29)
1673 +#define DPLL_VGA_MODE_DIS (1 << 28)
1674 +#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
1675 +#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
1676 +#define DPLL_MODE_MASK (3 << 26)
1677 +#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
1678 +#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
1679 +#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
1680 +#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
1681 +#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
1682 +#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
1684 +#define I915_FIFO_UNDERRUN_STATUS (1UL<<31)
1685 +#define I915_CRC_ERROR_ENABLE (1UL<<29)
1686 +#define I915_CRC_DONE_ENABLE (1UL<<28)
1687 +#define I915_GMBUS_EVENT_ENABLE (1UL<<27)
1688 +#define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25)
1689 +#define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
1690 +#define I915_DPST_EVENT_ENABLE (1UL<<23)
1691 +#define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
1692 +#define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
1693 +#define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
1694 +#define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
1695 +#define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
1696 +#define I915_OVERLAY_UPDATED_ENABLE (1UL<<16)
1697 +#define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
1698 +#define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
1699 +#define I915_GMBUS_INTERRUPT_STATUS (1UL<<11)
1700 +#define I915_VSYNC_INTERRUPT_STATUS (1UL<<9)
1701 +#define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
1702 +#define I915_DPST_EVENT_STATUS (1UL<<7)
1703 +#define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6)
1704 +#define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
1705 +#define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
1706 +#define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
1707 +#define I915_VBLANK_INTERRUPT_STATUS (1UL<<1)
1708 +#define I915_OVERLAY_UPDATED_STATUS (1UL<<0)
1710 +#define SRX_INDEX 0x3c4
1711 +#define SRX_DATA 0x3c5
1713 +#define SR01_SCREEN_OFF (1<<5)
1715 +#define PPCR 0x61204
1716 +#define PPCR_ON (1<<0)
1718 +#define DVOB 0x61140
1719 +#define DVOB_ON (1<<31)
1720 +#define DVOC 0x61160
1721 +#define DVOC_ON (1<<31)
1722 +#define LVDS 0x61180
1723 +#define LVDS_ON (1<<31)
1725 +#define ADPA 0x61100
1726 +#define ADPA_DPMS_MASK (~(3<<10))
1727 +#define ADPA_DPMS_ON (0<<10)
1728 +#define ADPA_DPMS_SUSPEND (1<<10)
1729 +#define ADPA_DPMS_STANDBY (2<<10)
1730 +#define ADPA_DPMS_OFF (3<<10)
1732 +#define RING_TAIL 0x00
1733 +#define TAIL_ADDR 0x001FFFF8
1734 +#define RING_HEAD 0x04
1735 +#define HEAD_WRAP_COUNT 0xFFE00000
1736 +#define HEAD_WRAP_ONE 0x00200000
1737 +#define HEAD_ADDR 0x001FFFFC
1738 +#define RING_START 0x08
1739 +#define START_ADDR 0xFFFFF000
1740 +#define RING_LEN 0x0C
1741 +#define RING_NR_PAGES 0x001FF000
1742 +#define RING_REPORT_MASK 0x00000006
1743 +#define RING_REPORT_64K 0x00000002
1744 +#define RING_REPORT_128K 0x00000004
1745 +#define RING_NO_REPORT 0x00000000
1746 +#define RING_VALID_MASK 0x00000001
1747 +#define RING_VALID 0x00000001
1748 +#define RING_INVALID 0x00000000
1750 +/* Scratch pad debug 0 reg:
1752 +#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
1754 + * The i830 generation, in LVDS mode, defines P1 as the bit number set within
1755 + * this field (only one bit may be set).
1757 +#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
1758 +#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
1759 +/* i830, required in DVO non-gang */
1760 +#define PLL_P2_DIVIDE_BY_4 (1 << 23)
1761 +#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
1762 +#define PLL_REF_INPUT_DREFCLK (0 << 13)
1763 +#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
1764 +#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
1765 +#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
1766 +#define PLL_REF_INPUT_MASK (3 << 13)
1767 +#define PLL_LOAD_PULSE_PHASE_SHIFT 9
1769 + * Parallel to Serial Load Pulse phase selection.
1770 + * Selects the phase for the 10X DPLL clock for the PCIe
1771 + * digital display port. The range is 4 to 13; 10 or more
1772 + * is just a flip delay. The default is 6
1774 +#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
1775 +#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
1777 + * SDVO multiplier for 945G/GM. Not used on 965.
1779 +#define SDVO_MULTIPLIER_MASK 0x000000ff
1780 +#define SDVO_MULTIPLIER_SHIFT_HIRES 4
1781 +#define SDVO_MULTIPLIER_SHIFT_VGA 0
1782 +#define DPLL_A_MD 0x0601c /* 965+ only */
1784 + * UDI pixel divider, controlling how many pixels are stuffed into a packet.
1786 + * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
1788 +#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
1789 +#define DPLL_MD_UDI_DIVIDER_SHIFT 24
1790 +/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
1791 +#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
1792 +#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
1794 + * SDVO/UDI pixel multiplier.
1796 + * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
1797 + * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
1798 + * modes, the bus rate would be below the limits, so SDVO allows for stuffing
1799 + * dummy bytes in the datastream at an increased clock rate, with both sides of
1800 + * the link knowing how many bytes are fill.
1802 + * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
1803 + * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
1804 + * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
1805 + * through an SDVO command.
1807 + * This register field has values of multiplication factor minus 1, with
1808 + * a maximum multiplier of 5 for SDVO.
1810 +#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
1811 +#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
1813 + * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
1814 + * This best be set to the default value (3) or the CRT won't work. No,
1815 + * I don't entirely understand what this does...
1817 +#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
1818 +#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
1819 +#define DPLL_B_MD 0x06020 /* 965+ only */
1820 +#define FPA0 0x06040
1821 +#define FPA1 0x06044
1822 +#define FPB0 0x06048
1823 +#define FPB1 0x0604c
1824 +#define FP_N_DIV_MASK 0x003f0000
1825 +#define FP_N_DIV_SHIFT 16
1826 +#define FP_M1_DIV_MASK 0x00003f00
1827 +#define FP_M1_DIV_SHIFT 8
1828 +#define FP_M2_DIV_MASK 0x0000003f
1829 +#define FP_M2_DIV_SHIFT 0
1830 +#define DPLL_TEST 0x606c
1831 +#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
1832 +#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
1833 +#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
1834 +#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
1835 +#define DPLLB_TEST_N_BYPASS (1 << 19)
1836 +#define DPLLB_TEST_M_BYPASS (1 << 18)
1837 +#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
1838 +#define DPLLA_TEST_N_BYPASS (1 << 3)
1839 +#define DPLLA_TEST_M_BYPASS (1 << 2)
1840 +#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
1841 +#define D_STATE 0x6104
1842 +#define CG_2D_DIS 0x6200
1843 +#define CG_3D_DIS 0x6204
1849 +#define PALETTE_A 0x0a000
1850 +#define PALETTE_B 0x0a800
1856 +#define OVADD 0x30000
1857 +#define DOVSTA 0x30008
1858 +#define OC_BUF (0x3<<20)
1859 +#define OGAMC5 0x30010
1860 +#define OGAMC4 0x30014
1861 +#define OGAMC3 0x30018
1862 +#define OGAMC2 0x3001c
1863 +#define OGAMC1 0x30020
1864 +#define OGAMC0 0x30024
1867 + * Display engine regs
1870 +/* Pipe A timing regs */
1871 +#define HTOTAL_A 0x60000
1872 +#define HBLANK_A 0x60004
1873 +#define HSYNC_A 0x60008
1874 +#define VTOTAL_A 0x6000c
1875 +#define VBLANK_A 0x60010
1876 +#define VSYNC_A 0x60014
1877 +#define PIPEASRC 0x6001c
1878 +#define BCLRPAT_A 0x60020
1880 +/* Pipe B timing regs */
1881 +#define HTOTAL_B 0x61000
1882 +#define HBLANK_B 0x61004
1883 +#define HSYNC_B 0x61008
1884 +#define VTOTAL_B 0x6100c
1885 +#define VBLANK_B 0x61010
1886 +#define VSYNC_B 0x61014
1887 +#define PIPEBSRC 0x6101c
1888 +#define BCLRPAT_B 0x61020
1890 +/* VGA port control */
1891 +#define ADPA 0x61100
1892 +#define ADPA_DAC_ENABLE (1<<31)
1893 +#define ADPA_DAC_DISABLE 0
1894 +#define ADPA_PIPE_SELECT_MASK (1<<30)
1895 +#define ADPA_PIPE_A_SELECT 0
1896 +#define ADPA_PIPE_B_SELECT (1<<30)
1897 +#define ADPA_USE_VGA_HVPOLARITY (1<<15)
1898 +#define ADPA_SETS_HVPOLARITY 0
1899 +#define ADPA_VSYNC_CNTL_DISABLE (1<<11)
1900 +#define ADPA_VSYNC_CNTL_ENABLE 0
1901 +#define ADPA_HSYNC_CNTL_DISABLE (1<<10)
1902 +#define ADPA_HSYNC_CNTL_ENABLE 0
1903 +#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
1904 +#define ADPA_VSYNC_ACTIVE_LOW 0
1905 +#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
1906 +#define ADPA_HSYNC_ACTIVE_LOW 0
1907 +#define ADPA_DPMS_MASK (~(3<<10))
1908 +#define ADPA_DPMS_ON (0<<10)
1909 +#define ADPA_DPMS_SUSPEND (1<<10)
1910 +#define ADPA_DPMS_STANDBY (2<<10)
1911 +#define ADPA_DPMS_OFF (3<<10)
1913 +/* Hotplug control (945+ only) */
1914 +#define PORT_HOTPLUG_EN 0x61110
1915 +#define SDVOB_HOTPLUG_INT_EN (1 << 26)
1916 +#define SDVOC_HOTPLUG_INT_EN (1 << 25)
1917 +#define TV_HOTPLUG_INT_EN (1 << 18)
1918 +#define CRT_HOTPLUG_INT_EN (1 << 9)
1919 +#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
1921 +#define PORT_HOTPLUG_STAT 0x61114
1922 +#define CRT_HOTPLUG_INT_STATUS (1 << 11)
1923 +#define TV_HOTPLUG_INT_STATUS (1 << 10)
1924 +#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
1925 +#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
1926 +#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
1927 +#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
1928 +#define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
1929 +#define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
1931 +/* SDVO port control */
1932 +#define SDVOB 0x61140
1933 +#define SDVOC 0x61160
1934 +#define SDVO_ENABLE (1 << 31)
1935 +#define SDVO_PIPE_B_SELECT (1 << 30)
1936 +#define SDVO_STALL_SELECT (1 << 29)
1937 +#define SDVO_INTERRUPT_ENABLE (1 << 26)
1939 + * 915G/GM SDVO pixel multiplier.
1941 + * Programmed value is multiplier - 1, up to 5x.
1943 + * \sa DPLL_MD_UDI_MULTIPLIER_MASK
1945 +#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
1946 +#define SDVO_PORT_MULTIPLY_SHIFT 23
1947 +#define SDVO_PHASE_SELECT_MASK (15 << 19)
1948 +#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
1949 +#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
1950 +#define SDVOC_GANG_MODE (1 << 16)
1951 +#define SDVO_BORDER_ENABLE (1 << 7)
1952 +#define SDVOB_PCIE_CONCURRENCY (1 << 3)
1953 +#define SDVO_DETECTED (1 << 2)
1954 +/* Bits to be preserved when writing */
1955 +#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
1956 +#define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
1958 +/* DVO port control */
1959 +#define DVOA 0x61120
1960 +#define DVOB 0x61140
1961 +#define DVOC 0x61160
1962 +#define DVO_ENABLE (1 << 31)
1963 +#define DVO_PIPE_B_SELECT (1 << 30)
1964 +#define DVO_PIPE_STALL_UNUSED (0 << 28)
1965 +#define DVO_PIPE_STALL (1 << 28)
1966 +#define DVO_PIPE_STALL_TV (2 << 28)
1967 +#define DVO_PIPE_STALL_MASK (3 << 28)
1968 +#define DVO_USE_VGA_SYNC (1 << 15)
1969 +#define DVO_DATA_ORDER_I740 (0 << 14)
1970 +#define DVO_DATA_ORDER_FP (1 << 14)
1971 +#define DVO_VSYNC_DISABLE (1 << 11)
1972 +#define DVO_HSYNC_DISABLE (1 << 10)
1973 +#define DVO_VSYNC_TRISTATE (1 << 9)
1974 +#define DVO_HSYNC_TRISTATE (1 << 8)
1975 +#define DVO_BORDER_ENABLE (1 << 7)
1976 +#define DVO_DATA_ORDER_GBRG (1 << 6)
1977 +#define DVO_DATA_ORDER_RGGB (0 << 6)
1978 +#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
1979 +#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
1980 +#define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
1981 +#define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
1982 +#define DVO_BLANK_ACTIVE_HIGH (1 << 2)
1983 +#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
1984 +#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
1985 +#define DVO_PRESERVE_MASK (0x7<<24)
1986 +#define DVOA_SRCDIM 0x61124
1987 +#define DVOB_SRCDIM 0x61144
1988 +#define DVOC_SRCDIM 0x61164
1989 +#define DVO_SRCDIM_HORIZONTAL_SHIFT 12
1990 +#define DVO_SRCDIM_VERTICAL_SHIFT 0
1992 +/* LVDS port control */
1993 +#define LVDS 0x61180
1995 + * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
1996 + * the DPLL semantics change when the LVDS is assigned to that pipe.
1998 +#define LVDS_PORT_EN (1 << 31)
1999 +/* Selects pipe B for LVDS data. Must be set on pre-965. */
2000 +#define LVDS_PIPEB_SELECT (1 << 30)
2002 + * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
2005 +#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
2006 +#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
2007 +#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
2009 + * Controls the A3 data pair, which contains the additional LSBs for 24 bit
2010 + * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
2013 +#define LVDS_A3_POWER_MASK (3 << 6)
2014 +#define LVDS_A3_POWER_DOWN (0 << 6)
2015 +#define LVDS_A3_POWER_UP (3 << 6)
2017 + * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
2020 +#define LVDS_CLKB_POWER_MASK (3 << 4)
2021 +#define LVDS_CLKB_POWER_DOWN (0 << 4)
2022 +#define LVDS_CLKB_POWER_UP (3 << 4)
2024 + * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
2025 + * setting for whether we are in dual-channel mode. The B3 pair will
2026 + * additionally only be powered up when LVDS_A3_POWER_UP is set.
2028 +#define LVDS_B0B3_POWER_MASK (3 << 2)
2029 +#define LVDS_B0B3_POWER_DOWN (0 << 2)
2030 +#define LVDS_B0B3_POWER_UP (3 << 2)
2032 +/* Panel power sequencing */
2033 +#define PP_STATUS 0x61200
2034 +#define PP_ON (1 << 31)
2036 + * Indicates that all dependencies of the panel are on:
2040 + * - LVDS/DVOB/DVOC on
2042 +#define PP_READY (1 << 30)
2043 +#define PP_SEQUENCE_NONE (0 << 28)
2044 +#define PP_SEQUENCE_ON (1 << 28)
2045 +#define PP_SEQUENCE_OFF (2 << 28)
2046 +#define PP_SEQUENCE_MASK 0x30000000
2047 +#define PP_CONTROL 0x61204
2048 +#define POWER_TARGET_ON (1 << 0)
2049 +#define PP_ON_DELAYS 0x61208
2050 +#define PP_OFF_DELAYS 0x6120c
2051 +#define PP_DIVISOR 0x61210
2053 +/* Panel fitting */
2054 +#define PFIT_CONTROL 0x61230
2055 +#define PFIT_ENABLE (1 << 31)
2056 +#define PFIT_PIPE_MASK (3 << 29)
2057 +#define PFIT_PIPE_SHIFT 29
2058 +#define VERT_INTERP_DISABLE (0 << 10)
2059 +#define VERT_INTERP_BILINEAR (1 << 10)
2060 +#define VERT_INTERP_MASK (3 << 10)
2061 +#define VERT_AUTO_SCALE (1 << 9)
2062 +#define HORIZ_INTERP_DISABLE (0 << 6)
2063 +#define HORIZ_INTERP_BILINEAR (1 << 6)
2064 +#define HORIZ_INTERP_MASK (3 << 6)
2065 +#define HORIZ_AUTO_SCALE (1 << 5)
2066 +#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
2067 +#define PFIT_PGM_RATIOS 0x61234
2068 +#define PFIT_VERT_SCALE_MASK 0xfff00000
2069 +#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
2070 +#define PFIT_AUTO_RATIOS 0x61238
2072 +/* Backlight control */
2073 +#define BLC_PWM_CTL 0x61254
2074 +#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
2075 +#define BLC_PWM_CTL2 0x61250 /* 965+ only */
2077 + * This is the most significant 15 bits of the number of backlight cycles in a
2078 + * complete cycle of the modulated backlight control.
2080 + * The actual value is this field multiplied by two.
2082 +#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
2083 +#define BLM_LEGACY_MODE (1 << 16)
2085 + * This is the number of cycles out of the backlight modulation cycle for which
2086 + * the backlight is on.
2088 + * This field must be no greater than the number of cycles in the complete
2089 + * backlight modulation cycle.
2091 +#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
2092 +#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
2094 +/* TV port control */
2095 +#define TV_CTL 0x68000
2096 +/** Enables the TV encoder */
2097 +# define TV_ENC_ENABLE (1 << 31)
2098 +/** Sources the TV encoder input from pipe B instead of A. */
2099 +# define TV_ENC_PIPEB_SELECT (1 << 30)
2100 +/** Outputs composite video (DAC A only) */
2101 +# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
2102 +/** Outputs SVideo video (DAC B/C) */
2103 +# define TV_ENC_OUTPUT_SVIDEO (1 << 28)
2104 +/** Outputs Component video (DAC A/B/C) */
2105 +# define TV_ENC_OUTPUT_COMPONENT (2 << 28)
2106 +/** Outputs Composite and SVideo (DAC A/B/C) */
2107 +# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
2108 +# define TV_TRILEVEL_SYNC (1 << 21)
2109 +/** Enables slow sync generation (945GM only) */
2110 +# define TV_SLOW_SYNC (1 << 20)
2111 +/** Selects 4x oversampling for 480i and 576p */
2112 +# define TV_OVERSAMPLE_4X (0 << 18)
2113 +/** Selects 2x oversampling for 720p and 1080i */
2114 +# define TV_OVERSAMPLE_2X (1 << 18)
2115 +/** Selects no oversampling for 1080p */
2116 +# define TV_OVERSAMPLE_NONE (2 << 18)
2117 +/** Selects 8x oversampling */
2118 +# define TV_OVERSAMPLE_8X (3 << 18)
2119 +/** Selects progressive mode rather than interlaced */
2120 +# define TV_PROGRESSIVE (1 << 17)
2121 +/** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
2122 +# define TV_PAL_BURST (1 << 16)
2123 +/** Field for setting delay of Y compared to C */
2124 +# define TV_YC_SKEW_MASK (7 << 12)
2125 +/** Enables a fix for 480p/576p standard definition modes on the 915GM only */
2126 +# define TV_ENC_SDP_FIX (1 << 11)
2128 + * Enables a fix for the 915GM only.
2130 + * Not sure what it does.
2132 +# define TV_ENC_C0_FIX (1 << 10)
2133 +/** Bits that must be preserved by software */
2134 +# define TV_CTL_SAVE ((3 << 8) | (3 << 6))
2135 +# define TV_FUSE_STATE_MASK (3 << 4)
2136 +/** Read-only state that reports all features enabled */
2137 +# define TV_FUSE_STATE_ENABLED (0 << 4)
2138 +/** Read-only state that reports that Macrovision is disabled in hardware*/
2139 +# define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
2140 +/** Read-only state that reports that TV-out is disabled in hardware. */
2141 +# define TV_FUSE_STATE_DISABLED (2 << 4)
2142 +/** Normal operation */
2143 +# define TV_TEST_MODE_NORMAL (0 << 0)
2144 +/** Encoder test pattern 1 - combo pattern */
2145 +# define TV_TEST_MODE_PATTERN_1 (1 << 0)
2146 +/** Encoder test pattern 2 - full screen vertical 75% color bars */
2147 +# define TV_TEST_MODE_PATTERN_2 (2 << 0)
2148 +/** Encoder test pattern 3 - full screen horizontal 75% color bars */
2149 +# define TV_TEST_MODE_PATTERN_3 (3 << 0)
2150 +/** Encoder test pattern 4 - random noise */
2151 +# define TV_TEST_MODE_PATTERN_4 (4 << 0)
2152 +/** Encoder test pattern 5 - linear color ramps */
2153 +# define TV_TEST_MODE_PATTERN_5 (5 << 0)
2155 + * This test mode forces the DACs to 50% of full output.
2157 + * This is used for load detection in combination with TVDAC_SENSE_MASK
2159 +# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
2160 +# define TV_TEST_MODE_MASK (7 << 0)
2162 +#define TV_DAC 0x68004
2164 + * Reports that DAC state change logic has reported change (RO).
2166 + * This gets cleared when TV_DAC_STATE_EN is cleared
2168 +# define TVDAC_STATE_CHG (1 << 31)
2169 +# define TVDAC_SENSE_MASK (7 << 28)
2170 +/** Reports that DAC A voltage is above the detect threshold */
2171 +# define TVDAC_A_SENSE (1 << 30)
2172 +/** Reports that DAC B voltage is above the detect threshold */
2173 +# define TVDAC_B_SENSE (1 << 29)
2174 +/** Reports that DAC C voltage is above the detect threshold */
2175 +# define TVDAC_C_SENSE (1 << 28)
2177 + * Enables DAC state detection logic, for load-based TV detection.
2179 + * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
2180 + * to off, for load detection to work.
2182 +# define TVDAC_STATE_CHG_EN (1 << 27)
2183 +/** Sets the DAC A sense value to high */
2184 +# define TVDAC_A_SENSE_CTL (1 << 26)
2185 +/** Sets the DAC B sense value to high */
2186 +# define TVDAC_B_SENSE_CTL (1 << 25)
2187 +/** Sets the DAC C sense value to high */
2188 +# define TVDAC_C_SENSE_CTL (1 << 24)
2189 +/** Overrides the ENC_ENABLE and DAC voltage levels */
2190 +# define DAC_CTL_OVERRIDE (1 << 7)
2191 +/** Sets the slew rate. Must be preserved in software */
2192 +# define ENC_TVDAC_SLEW_FAST (1 << 6)
2193 +# define DAC_A_1_3_V (0 << 4)
2194 +# define DAC_A_1_1_V (1 << 4)
2195 +# define DAC_A_0_7_V (2 << 4)
2196 +# define DAC_A_OFF (3 << 4)
2197 +# define DAC_B_1_3_V (0 << 2)
2198 +# define DAC_B_1_1_V (1 << 2)
2199 +# define DAC_B_0_7_V (2 << 2)
2200 +# define DAC_B_OFF (3 << 2)
2201 +# define DAC_C_1_3_V (0 << 0)
2202 +# define DAC_C_1_1_V (1 << 0)
2203 +# define DAC_C_0_7_V (2 << 0)
2204 +# define DAC_C_OFF (3 << 0)
2207 + * CSC coefficients are stored in a floating point format with 9 bits of
2208 + * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
2209 + * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
2210 + * -1 (0x3) being the only legal negative value.
2212 +#define TV_CSC_Y 0x68010
2213 +# define TV_RY_MASK 0x07ff0000
2214 +# define TV_RY_SHIFT 16
2215 +# define TV_GY_MASK 0x00000fff
2216 +# define TV_GY_SHIFT 0
2218 +#define TV_CSC_Y2 0x68014
2219 +# define TV_BY_MASK 0x07ff0000
2220 +# define TV_BY_SHIFT 16
2222 + * Y attenuation for component video.
2224 + * Stored in 1.9 fixed point.
2226 +# define TV_AY_MASK 0x000003ff
2227 +# define TV_AY_SHIFT 0
2229 +#define TV_CSC_U 0x68018
2230 +# define TV_RU_MASK 0x07ff0000
2231 +# define TV_RU_SHIFT 16
2232 +# define TV_GU_MASK 0x000007ff
2233 +# define TV_GU_SHIFT 0
2235 +#define TV_CSC_U2 0x6801c
2236 +# define TV_BU_MASK 0x07ff0000
2237 +# define TV_BU_SHIFT 16
2239 + * U attenuation for component video.
2241 + * Stored in 1.9 fixed point.
2243 +# define TV_AU_MASK 0x000003ff
2244 +# define TV_AU_SHIFT 0
2246 +#define TV_CSC_V 0x68020
2247 +# define TV_RV_MASK 0x0fff0000
2248 +# define TV_RV_SHIFT 16
2249 +# define TV_GV_MASK 0x000007ff
2250 +# define TV_GV_SHIFT 0
2252 +#define TV_CSC_V2 0x68024
2253 +# define TV_BV_MASK 0x07ff0000
2254 +# define TV_BV_SHIFT 16
2256 + * V attenuation for component video.
2258 + * Stored in 1.9 fixed point.
2260 +# define TV_AV_MASK 0x000007ff
2261 +# define TV_AV_SHIFT 0
2263 +#define TV_CLR_KNOBS 0x68028
2264 +/** 2s-complement brightness adjustment */
2265 +# define TV_BRIGHTNESS_MASK 0xff000000
2266 +# define TV_BRIGHTNESS_SHIFT 24
2267 +/** Contrast adjustment, as a 2.6 unsigned floating point number */
2268 +# define TV_CONTRAST_MASK 0x00ff0000
2269 +# define TV_CONTRAST_SHIFT 16
2270 +/** Saturation adjustment, as a 2.6 unsigned floating point number */
2271 +# define TV_SATURATION_MASK 0x0000ff00
2272 +# define TV_SATURATION_SHIFT 8
2273 +/** Hue adjustment, as an integer phase angle in degrees */
2274 +# define TV_HUE_MASK 0x000000ff
2275 +# define TV_HUE_SHIFT 0
2277 +#define TV_CLR_LEVEL 0x6802c
2278 +/** Controls the DAC level for black */
2279 +# define TV_BLACK_LEVEL_MASK 0x01ff0000
2280 +# define TV_BLACK_LEVEL_SHIFT 16
2281 +/** Controls the DAC level for blanking */
2282 +# define TV_BLANK_LEVEL_MASK 0x000001ff
2283 +# define TV_BLANK_LEVEL_SHIFT 0
2285 +#define TV_H_CTL_1 0x68030
2286 +/** Number of pixels in the hsync. */
2287 +# define TV_HSYNC_END_MASK 0x1fff0000
2288 +# define TV_HSYNC_END_SHIFT 16
2289 +/** Total number of pixels minus one in the line (display and blanking). */
2290 +# define TV_HTOTAL_MASK 0x00001fff
2291 +# define TV_HTOTAL_SHIFT 0
2293 +#define TV_H_CTL_2 0x68034
2294 +/** Enables the colorburst (needed for non-component color) */
2295 +# define TV_BURST_ENA (1 << 31)
2296 +/** Offset of the colorburst from the start of hsync, in pixels minus one. */
2297 +# define TV_HBURST_START_SHIFT 16
2298 +# define TV_HBURST_START_MASK 0x1fff0000
2299 +/** Length of the colorburst */
2300 +# define TV_HBURST_LEN_SHIFT 0
2301 +# define TV_HBURST_LEN_MASK 0x0001fff
2303 +#define TV_H_CTL_3 0x68038
2304 +/** End of hblank, measured in pixels minus one from start of hsync */
2305 +# define TV_HBLANK_END_SHIFT 16
2306 +# define TV_HBLANK_END_MASK 0x1fff0000
2307 +/** Start of hblank, measured in pixels minus one from start of hsync */
2308 +# define TV_HBLANK_START_SHIFT 0
2309 +# define TV_HBLANK_START_MASK 0x0001fff
2311 +#define TV_V_CTL_1 0x6803c
2313 +# define TV_NBR_END_SHIFT 16
2314 +# define TV_NBR_END_MASK 0x07ff0000
2316 +# define TV_VI_END_F1_SHIFT 8
2317 +# define TV_VI_END_F1_MASK 0x00003f00
2319 +# define TV_VI_END_F2_SHIFT 0
2320 +# define TV_VI_END_F2_MASK 0x0000003f
2322 +#define TV_V_CTL_2 0x68040
2323 +/** Length of vsync, in half lines */
2324 +# define TV_VSYNC_LEN_MASK 0x07ff0000
2325 +# define TV_VSYNC_LEN_SHIFT 16
2326 +/** Offset of the start of vsync in field 1, measured in one less than the
2327 + * number of half lines.
2329 +# define TV_VSYNC_START_F1_MASK 0x00007f00
2330 +# define TV_VSYNC_START_F1_SHIFT 8
2332 + * Offset of the start of vsync in field 2, measured in one less than the
2333 + * number of half lines.
2335 +# define TV_VSYNC_START_F2_MASK 0x0000007f
2336 +# define TV_VSYNC_START_F2_SHIFT 0
2338 +#define TV_V_CTL_3 0x68044
2339 +/** Enables generation of the equalization signal */
2340 +# define TV_EQUAL_ENA (1 << 31)
2341 +/** Length of vsync, in half lines */
2342 +# define TV_VEQ_LEN_MASK 0x007f0000
2343 +# define TV_VEQ_LEN_SHIFT 16
2344 +/** Offset of the start of equalization in field 1, measured in one less than
2345 + * the number of half lines.
2347 +# define TV_VEQ_START_F1_MASK 0x0007f00
2348 +# define TV_VEQ_START_F1_SHIFT 8
2350 + * Offset of the start of equalization in field 2, measured in one less than
2351 + * the number of half lines.
2353 +# define TV_VEQ_START_F2_MASK 0x000007f
2354 +# define TV_VEQ_START_F2_SHIFT 0
2356 +#define TV_V_CTL_4 0x68048
2358 + * Offset to start of vertical colorburst, measured in one less than the
2359 + * number of lines from vertical start.
2361 +# define TV_VBURST_START_F1_MASK 0x003f0000
2362 +# define TV_VBURST_START_F1_SHIFT 16
2364 + * Offset to the end of vertical colorburst, measured in one less than the
2365 + * number of lines from the start of NBR.
2367 +# define TV_VBURST_END_F1_MASK 0x000000ff
2368 +# define TV_VBURST_END_F1_SHIFT 0
2370 +#define TV_V_CTL_5 0x6804c
2372 + * Offset to start of vertical colorburst, measured in one less than the
2373 + * number of lines from vertical start.
2375 +# define TV_VBURST_START_F2_MASK 0x003f0000
2376 +# define TV_VBURST_START_F2_SHIFT 16
2378 + * Offset to the end of vertical colorburst, measured in one less than the
2379 + * number of lines from the start of NBR.
2381 +# define TV_VBURST_END_F2_MASK 0x000000ff
2382 +# define TV_VBURST_END_F2_SHIFT 0
2384 +#define TV_V_CTL_6 0x68050
2386 + * Offset to start of vertical colorburst, measured in one less than the
2387 + * number of lines from vertical start.
2389 +# define TV_VBURST_START_F3_MASK 0x003f0000
2390 +# define TV_VBURST_START_F3_SHIFT 16
2392 + * Offset to the end of vertical colorburst, measured in one less than the
2393 + * number of lines from the start of NBR.
2395 +# define TV_VBURST_END_F3_MASK 0x000000ff
2396 +# define TV_VBURST_END_F3_SHIFT 0
2398 +#define TV_V_CTL_7 0x68054
2400 + * Offset to start of vertical colorburst, measured in one less than the
2401 + * number of lines from vertical start.
2403 +# define TV_VBURST_START_F4_MASK 0x003f0000
2404 +# define TV_VBURST_START_F4_SHIFT 16
2406 + * Offset to the end of vertical colorburst, measured in one less than the
2407 + * number of lines from the start of NBR.
2409 +# define TV_VBURST_END_F4_MASK 0x000000ff
2410 +# define TV_VBURST_END_F4_SHIFT 0
2412 +#define TV_SC_CTL_1 0x68060
2413 +/** Turns on the first subcarrier phase generation DDA */
2414 +# define TV_SC_DDA1_EN (1 << 31)
2415 +/** Turns on the first subcarrier phase generation DDA */
2416 +# define TV_SC_DDA2_EN (1 << 30)
2417 +/** Turns on the first subcarrier phase generation DDA */
2418 +# define TV_SC_DDA3_EN (1 << 29)
2419 +/** Sets the subcarrier DDA to reset frequency every other field */
2420 +# define TV_SC_RESET_EVERY_2 (0 << 24)
2421 +/** Sets the subcarrier DDA to reset frequency every fourth field */
2422 +# define TV_SC_RESET_EVERY_4 (1 << 24)
2423 +/** Sets the subcarrier DDA to reset frequency every eighth field */
2424 +# define TV_SC_RESET_EVERY_8 (2 << 24)
2425 +/** Sets the subcarrier DDA to never reset the frequency */
2426 +# define TV_SC_RESET_NEVER (3 << 24)
2427 +/** Sets the peak amplitude of the colorburst.*/
2428 +# define TV_BURST_LEVEL_MASK 0x00ff0000
2429 +# define TV_BURST_LEVEL_SHIFT 16
2430 +/** Sets the increment of the first subcarrier phase generation DDA */
2431 +# define TV_SCDDA1_INC_MASK 0x00000fff
2432 +# define TV_SCDDA1_INC_SHIFT 0
2434 +#define TV_SC_CTL_2 0x68064
2435 +/** Sets the rollover for the second subcarrier phase generation DDA */
2436 +# define TV_SCDDA2_SIZE_MASK 0x7fff0000
2437 +# define TV_SCDDA2_SIZE_SHIFT 16
2438 +/** Sets the increent of the second subcarrier phase generation DDA */
2439 +# define TV_SCDDA2_INC_MASK 0x00007fff
2440 +# define TV_SCDDA2_INC_SHIFT 0
2442 +#define TV_SC_CTL_3 0x68068
2443 +/** Sets the rollover for the third subcarrier phase generation DDA */
2444 +# define TV_SCDDA3_SIZE_MASK 0x7fff0000
2445 +# define TV_SCDDA3_SIZE_SHIFT 16
2446 +/** Sets the increent of the third subcarrier phase generation DDA */
2447 +# define TV_SCDDA3_INC_MASK 0x00007fff
2448 +# define TV_SCDDA3_INC_SHIFT 0
2450 +#define TV_WIN_POS 0x68070
2451 +/** X coordinate of the display from the start of horizontal active */
2452 +# define TV_XPOS_MASK 0x1fff0000
2453 +# define TV_XPOS_SHIFT 16
2454 +/** Y coordinate of the display from the start of vertical active (NBR) */
2455 +# define TV_YPOS_MASK 0x00000fff
2456 +# define TV_YPOS_SHIFT 0
2458 +#define TV_WIN_SIZE 0x68074
2459 +/** Horizontal size of the display window, measured in pixels*/
2460 +# define TV_XSIZE_MASK 0x1fff0000
2461 +# define TV_XSIZE_SHIFT 16
2463 + * Vertical size of the display window, measured in pixels.
2465 + * Must be even for interlaced modes.
2467 +# define TV_YSIZE_MASK 0x00000fff
2468 +# define TV_YSIZE_SHIFT 0
2470 +#define TV_FILTER_CTL_1 0x68080
2472 + * Enables automatic scaling calculation.
2474 + * If set, the rest of the registers are ignored, and the calculated values can
2475 + * be read back from the register.
2477 +# define TV_AUTO_SCALE (1 << 31)
2479 + * Disables the vertical filter.
2481 + * This is required on modes more than 1024 pixels wide */
2482 +# define TV_V_FILTER_BYPASS (1 << 29)
2483 +/** Enables adaptive vertical filtering */
2484 +# define TV_VADAPT (1 << 28)
2485 +# define TV_VADAPT_MODE_MASK (3 << 26)
2486 +/** Selects the least adaptive vertical filtering mode */
2487 +# define TV_VADAPT_MODE_LEAST (0 << 26)
2488 +/** Selects the moderately adaptive vertical filtering mode */
2489 +# define TV_VADAPT_MODE_MODERATE (1 << 26)
2490 +/** Selects the most adaptive vertical filtering mode */
2491 +# define TV_VADAPT_MODE_MOST (3 << 26)
2493 + * Sets the horizontal scaling factor.
2495 + * This should be the fractional part of the horizontal scaling factor divided
2496 + * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
2498 + * (src width - 1) / ((oversample * dest width) - 1)
2500 +# define TV_HSCALE_FRAC_MASK 0x00003fff
2501 +# define TV_HSCALE_FRAC_SHIFT 0
2503 +#define TV_FILTER_CTL_2 0x68084
2505 + * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2507 + * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
2509 +# define TV_VSCALE_INT_MASK 0x00038000
2510 +# define TV_VSCALE_INT_SHIFT 15
2512 + * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2514 + * \sa TV_VSCALE_INT_MASK
2516 +# define TV_VSCALE_FRAC_MASK 0x00007fff
2517 +# define TV_VSCALE_FRAC_SHIFT 0
2519 +#define TV_FILTER_CTL_3 0x68088
2521 + * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2523 + * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
2525 + * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2527 +# define TV_VSCALE_IP_INT_MASK 0x00038000
2528 +# define TV_VSCALE_IP_INT_SHIFT 15
2530 + * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2532 + * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2534 + * \sa TV_VSCALE_IP_INT_MASK
2536 +# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
2537 +# define TV_VSCALE_IP_FRAC_SHIFT 0
2539 +#define TV_CC_CONTROL 0x68090
2540 +# define TV_CC_ENABLE (1 << 31)
2542 + * Specifies which field to send the CC data in.
2544 + * CC data is usually sent in field 0.
2546 +# define TV_CC_FID_MASK (1 << 27)
2547 +# define TV_CC_FID_SHIFT 27
2548 +/** Sets the horizontal position of the CC data. Usually 135. */
2549 +# define TV_CC_HOFF_MASK 0x03ff0000
2550 +# define TV_CC_HOFF_SHIFT 16
2551 +/** Sets the vertical position of the CC data. Usually 21 */
2552 +# define TV_CC_LINE_MASK 0x0000003f
2553 +# define TV_CC_LINE_SHIFT 0
2555 +#define TV_CC_DATA 0x68094
2556 +# define TV_CC_RDY (1 << 31)
2557 +/** Second word of CC data to be transmitted. */
2558 +# define TV_CC_DATA_2_MASK 0x007f0000
2559 +# define TV_CC_DATA_2_SHIFT 16
2560 +/** First word of CC data to be transmitted. */
2561 +# define TV_CC_DATA_1_MASK 0x0000007f
2562 +# define TV_CC_DATA_1_SHIFT 0
2564 +#define TV_H_LUMA_0 0x68100
2565 +#define TV_H_LUMA_59 0x681ec
2566 +#define TV_H_CHROMA_0 0x68200
2567 +#define TV_H_CHROMA_59 0x682ec
2568 +#define TV_V_LUMA_0 0x68300
2569 +#define TV_V_LUMA_42 0x683a8
2570 +#define TV_V_CHROMA_0 0x68400
2571 +#define TV_V_CHROMA_42 0x684a8
2573 +/* Display & cursor control */
2576 +#define PIPEADSL 0x70000
2577 +#define PIPEACONF 0x70008
2578 +#define PIPEACONF_ENABLE (1<<31)
2579 +#define PIPEACONF_DISABLE 0
2580 +#define PIPEACONF_DOUBLE_WIDE (1<<30)
2581 +#define I965_PIPECONF_ACTIVE (1<<30)
2582 +#define PIPEACONF_SINGLE_WIDE 0
2583 +#define PIPEACONF_PIPE_UNLOCKED 0
2584 +#define PIPEACONF_PIPE_LOCKED (1<<25)
2585 +#define PIPEACONF_PALETTE 0
2586 +#define PIPEACONF_GAMMA (1<<24)
2587 +#define PIPECONF_FORCE_BORDER (1<<25)
2588 +#define PIPECONF_PROGRESSIVE (0 << 21)
2589 +#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
2590 +#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
2591 +#define PIPEASTAT 0x70024
2592 +#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
2593 +#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
2594 +#define PIPE_CRC_DONE_ENABLE (1UL<<28)
2595 +#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
2596 +#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
2597 +#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
2598 +#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
2599 +#define PIPE_DPST_EVENT_ENABLE (1UL<<23)
2600 +#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
2601 +#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
2602 +#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
2603 +#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
2604 +#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
2605 +#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
2606 +#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
2607 +#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
2608 +#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
2609 +#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
2610 +#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
2611 +#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
2612 +#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
2613 +#define PIPE_DPST_EVENT_STATUS (1UL<<7)
2614 +#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
2615 +#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
2616 +#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
2617 +#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
2618 +#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
2619 +#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
2620 +#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
2622 +#define DSPARB 0x70030
2623 +#define DSPARB_CSTART_MASK (0x7f << 7)
2624 +#define DSPARB_CSTART_SHIFT 7
2625 +#define DSPARB_BSTART_MASK (0x7f)
2626 +#define DSPARB_BSTART_SHIFT 0
2628 + * The two pipe frame counter registers are not synchronized, so
2629 + * reading a stable value is somewhat tricky. The following code
2633 + * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2634 + * PIPE_FRAME_HIGH_SHIFT;
2635 + * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
2636 + * PIPE_FRAME_LOW_SHIFT);
2637 + * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2638 + * PIPE_FRAME_HIGH_SHIFT);
2639 + * } while (high1 != high2);
2640 + * frame = (high1 << 8) | low1;
2642 +#define PIPEAFRAMEHIGH 0x70040
2643 +#define PIPE_FRAME_HIGH_MASK 0x0000ffff
2644 +#define PIPE_FRAME_HIGH_SHIFT 0
2645 +#define PIPEAFRAMEPIXEL 0x70044
2646 +#define PIPE_FRAME_LOW_MASK 0xff000000
2647 +#define PIPE_FRAME_LOW_SHIFT 24
2648 +#define PIPE_PIXEL_MASK 0x00ffffff
2649 +#define PIPE_PIXEL_SHIFT 0
2651 +/* Cursor A & B regs */
2652 +#define CURACNTR 0x70080
2653 +#define CURSOR_MODE_DISABLE 0x00
2654 +#define CURSOR_MODE_64_32B_AX 0x07
2655 +#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
2656 +#define MCURSOR_GAMMA_ENABLE (1 << 26)
2657 +#define CURABASE 0x70084
2658 +#define CURAPOS 0x70088
2659 +#define CURSOR_POS_MASK 0x007FF
2660 +#define CURSOR_POS_SIGN 0x8000
2661 +#define CURSOR_X_SHIFT 0
2662 +#define CURSOR_Y_SHIFT 16
2663 +#define CURBCNTR 0x700c0
2664 +#define CURBBASE 0x700c4
2665 +#define CURBPOS 0x700c8
2667 +/* Display A control */
2668 +#define DSPACNTR 0x70180
2669 +#define DISPLAY_PLANE_ENABLE (1<<31)
2670 +#define DISPLAY_PLANE_DISABLE 0
2671 +#define DISPPLANE_GAMMA_ENABLE (1<<30)
2672 +#define DISPPLANE_GAMMA_DISABLE 0
2673 +#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
2674 +#define DISPPLANE_8BPP (0x2<<26)
2675 +#define DISPPLANE_15_16BPP (0x4<<26)
2676 +#define DISPPLANE_16BPP (0x5<<26)
2677 +#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
2678 +#define DISPPLANE_32BPP (0x7<<26)
2679 +#define DISPPLANE_STEREO_ENABLE (1<<25)
2680 +#define DISPPLANE_STEREO_DISABLE 0
2681 +#define DISPPLANE_SEL_PIPE_MASK (1<<24)
2682 +#define DISPPLANE_SEL_PIPE_A 0
2683 +#define DISPPLANE_SEL_PIPE_B (1<<24)
2684 +#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
2685 +#define DISPPLANE_SRC_KEY_DISABLE 0
2686 +#define DISPPLANE_LINE_DOUBLE (1<<20)
2687 +#define DISPPLANE_NO_LINE_DOUBLE 0
2688 +#define DISPPLANE_STEREO_POLARITY_FIRST 0
2689 +#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
2690 +#define DSPAADDR 0x70184
2691 +#define DSPASTRIDE 0x70188
2692 +#define DSPAPOS 0x7018C /* reserved */
2693 +#define DSPASIZE 0x70190
2694 +#define DSPASURF 0x7019C /* 965+ only */
2695 +#define DSPATILEOFF 0x701A4 /* 965+ only */
2698 +#define SWF00 0x71410
2699 +#define SWF01 0x71414
2700 +#define SWF02 0x71418
2701 +#define SWF03 0x7141c
2702 +#define SWF04 0x71420
2703 +#define SWF05 0x71424
2704 +#define SWF06 0x71428
2705 +#define SWF10 0x70410
2706 +#define SWF11 0x70414
2707 +#define SWF14 0x71420
2708 +#define SWF30 0x72414
2709 +#define SWF31 0x72418
2710 +#define SWF32 0x7241c
2713 +#define PIPEBDSL 0x71000
2714 +#define PIPEBCONF 0x71008
2715 +#define PIPEBSTAT 0x71024
2716 +#define PIPEBFRAMEHIGH 0x71040
2717 +#define PIPEBFRAMEPIXEL 0x71044
2719 +/* Display B control */
2720 +#define DSPBCNTR 0x71180
2721 +#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
2722 +#define DISPPLANE_ALPHA_TRANS_DISABLE 0
2723 +#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
2724 +#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
2725 +#define DSPBADDR 0x71184
2726 +#define DSPBSTRIDE 0x71188
2727 +#define DSPBPOS 0x7118C
2728 +#define DSPBSIZE 0x71190
2729 +#define DSPBSURF 0x7119C
2730 +#define DSPBTILEOFF 0x711A4
2733 +#define VGACNTRL 0x71400
2734 +# define VGA_DISP_DISABLE (1 << 31)
2735 +# define VGA_2X_MODE (1 << 30)
2736 +# define VGA_PIPE_B_SELECT (1 << 29)
2738 +#endif /* _I915_REG_H_ */
