code.ossystems Code Review - meta-freescale.git/blob

   1 From 4a7ee25e3f89d77a8ced081b73aebfb7a882302c Mon Sep 17 00:00:00 2001
   2 From: Stefano Babic <sbabic@denx.de>
   3 Date: Wed, 22 Feb 2012 00:24:36 +0000
   4 Subject: [PATCH 01/56] MX5: Add definitions for SATA controller
   5
   6 Add base address and MXC_SATA_CLK to return
   7 the clock used for the SATA controller.
   8
   9 Signed-off-by: Stefano Babic <sbabic@denx.de>
  10 CC: Fabio Estevam <fabio.estevam@freescale.com>
  11 CC: Dirk Behme <dirk.behme@de.bosch.com>
  12 ---
  13  arch/arm/cpu/armv7/mx5/clock.c           |    2 ++
  14  arch/arm/include/asm/arch-mx5/clock.h    |    1 +
  15  arch/arm/include/asm/arch-mx5/imx-regs.h |    1 +
  16  3 files changed, 4 insertions(+)
  17
  18 diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
  19 index e92f106..8f8d01c 100644
  20 --- a/arch/arm/cpu/armv7/mx5/clock.c
  21 +++ b/arch/arm/cpu/armv7/mx5/clock.c
  22 @@ -380,6 +380,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
  23         case MXC_FEC_CLK:
  24                 return decode_pll(mxc_plls[PLL1_CLOCK],
  25                                     CONFIG_SYS_MX5_HCLK);
  26 +       case MXC_SATA_CLK:
  27 +               return get_ahb_clk();
  28         default:
  29                 break;
  30         }
  31 diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h
  32 index ea972a3..f9f82f3 100644
  33 --- a/arch/arm/include/asm/arch-mx5/clock.h
  34 +++ b/arch/arm/include/asm/arch-mx5/clock.h
  35 @@ -32,6 +32,7 @@ enum mxc_clock {
  36         MXC_UART_CLK,
  37         MXC_CSPI_CLK,
  38         MXC_FEC_CLK,
  39 +       MXC_SATA_CLK,
  40  };
  41
  42  unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
  43 diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
  44 index 4fa6658..262517e 100644
  45 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h
  46 +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
  47 @@ -43,6 +43,7 @@
  48  #define NFC_BASE_ADDR_AXI       0xF7FF0000
  49  #define IRAM_BASE_ADDR          0xF8000000
  50  #define CS1_BASE_ADDR           0xF4000000
  51 +#define SATA_BASE_ADDR         0x10000000
  52  #else
  53  #error "CPU_TYPE not defined"
  54  #endif
  55 --
  56 1.7.10
  57