1 From 070bb8e23c0f2eb5106854adbc432c67b3177598 Mon Sep 17 00:00:00 2001
2 From: Marek Vasut <marex@denx.de>
3 Date: Fri, 4 May 2012 01:32:50 +0000
4 Subject: [PATCH 42/56] i.MX28: Add delay after CPU bypass is cleared
6 This solves issues when larger amount of DRAM is used, like 256MB.
7 Behave the same in case of CPU bypass as we do in case of EMI
8 bypass, but wait 15 ms. We need to wait until the clock domain
11 This issue seemed to have been caused by not waiting after frobbing
12 with the CPU bypass, it was unrelated to memory, but had a direct
13 impact, causing trouble. This was yet another X-File of the
14 imx-bootlets, sigh. The conclusion is, trying a semi-random delay
15 (there is delay after the EMI bypass change), the issue is fixed.
17 Another possible explanation is that we do not do the "simple memory
18 test" FSL does in their imx-bootlets (1000 R/W cycles to/from piece of
19 the memory, while also outputing something on the serial port). This
20 might have caused the similar delay in the imx-bootlets and therefore
21 they didn't need to add this explicitly.
23 For now, this seems good fix enough, but to me, whole that memory
24 init code in imx-bootlets is completely flunked and it'd need deeper
27 Signed-off-by: Marek Vasut <marex@denx.de>
28 Cc: Wolfgang Denk <wd@denx.de>
29 Cc: Detlev Zundel <dzu@denx.de>
30 Cc: Stefano Babic <sbabic@denx.de>
31 Cc: Fabio Estevam <festevam@gmail.com>
32 Acked-by: Stefano Babic <sbabic@denx.de>
33 Acked-by: Detlev Zundel <dzu@denx.de>
35 arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c | 2 ++
36 1 file changed, 2 insertions(+)
38 diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
39 index 0f825ed..69c865e 100644
40 --- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
41 +++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
42 @@ -149,6 +149,8 @@ void mx28_mem_setup_cpu_and_hbus(void)
43 /* Disable CPU bypass */
44 writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
45 &clkctrl_regs->hw_clkctrl_clkseq_clr);
50 void mx28_mem_setup_vdda(void)
