1 From b33793cbdf0b24f61398dfb98718ac9377e2b046 Mon Sep 17 00:00:00 2001
2 From: Liu Ying <Ying.Liu@freescale.com>
3 Date: Fri, 30 Sep 2011 16:00:09 +0800
4 Subject: [PATCH] ENGR00158480 IPUv3:Set IDMAC LOCK for SDC display channels
6 Set IDMAC_LOCK_EN_1 to make SDC display channels to generate
7 eight AXI bursts upon the assertion of the DMA request.
8 This change fixes the random garbage lines when showing
9 NV12 frames decoded by VPU with V4L2 output on
10 XGA@60 display's overlay framebuffer. V4L2 output uses
11 MEM_PP_MEM to do 180 degree rotation.
13 The issue can be reproduced by the following VPU unit test
15 /unit_tests/mxc_vpu_test.out -D
16 '-i /1920x1080_H264_AAC5.1ch.2.1ch_track1.h264 -f 2 -w 1024
17 -h 768 -r 180 -u 1 -t 1'
19 Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
20 (cherry picked from commit 50f969030c25bc33cf0f05a6a5cad98c52afd858)
22 drivers/mxc/ipu3/ipu_common.c | 3 +++
23 1 files changed, 3 insertions(+), 0 deletions(-)
25 diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c
26 index 8dfa54f..4b12905 100644
27 --- a/drivers/mxc/ipu3/ipu_common.c
28 +++ b/drivers/mxc/ipu3/ipu_common.c
29 @@ -385,6 +385,9 @@ static int ipu_probe(struct platform_device *pdev)
30 /* Set sync refresh channels and CSI->mem channel as high priority */
31 __raw_writel(0x18800001L, IDMAC_CHA_PRI(0));
33 + /* AXI burst setting for sync refresh channels */
34 + __raw_writel(0x003F0000, IDMAC_CH_LOCK_EN_1);
36 /* Set MCU_T to divide MCU access window into 2 */
37 __raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN);
