code.ossystems Code Review - openembedded-core.git/blob

   1 From a060e4d4a34b0fe17384e2d02e65c74fe73ee4c9 Mon Sep 17 00:00:00 2001
   2 From: Prajwal Mohan <prajwal.karur.mohan@intel.com>
   3 Date: Thu, 6 May 2010 14:29:26 -0700
   4 Subject: [PATCH] Graphics changes for Aava Koski DV1 hardware
   5
   6 Signed-Off-By: Prajwal Mohan <prajwal.karur.mohan@intel.com>
   7 Patch-mainline: 2.6.35?
   8 ---
   9  drivers/gpu/drm/mrst/drv/psb_drv.h                 |    7 +
  10  drivers/gpu/drm/mrst/drv/psb_intel_display.c       |   75 +-
  11  drivers/gpu/drm/mrst/drv/psb_intel_dsi.c           |    9 +
  12  drivers/gpu/drm/mrst/drv/psb_intel_dsi_aava.c      | 1356 ++++++++++----------
  13  .../linux_framebuffer_mrst/mrstlfb_displayclass.c  |   21 +-
  14  5 files changed, 735 insertions(+), 733 deletions(-)
  15
  16 diff --git a/drivers/gpu/drm/mrst/drv/psb_drv.h b/drivers/gpu/drm/mrst/drv/psb_drv.h
  17 index 2ac7934..56c1e90 100644
  18 --- a/drivers/gpu/drm/mrst/drv/psb_drv.h
  19 +++ b/drivers/gpu/drm/mrst/drv/psb_drv.h
  20 @@ -413,6 +413,8 @@ struct drm_psb_private {
  21         uint32_t dspcntr;
  22
  23  /* MRST_DSI private date start */
  24 +       struct work_struct dsi_work;
  25 +
  26         /*
  27          *MRST DSI info
  28          */
  29 @@ -430,6 +432,9 @@ struct drm_psb_private {
  30
  31         enum mipi_panel_type panel_make;
  32
  33 +       /* Set if MIPI encoder wants to control plane/pipe */
  34 +       bool dsi_plane_pipe_control;
  35 +
  36         /* status */
  37         uint32_t videoModeFormat:2;
  38         uint32_t laneCount:3;
  39 @@ -610,6 +615,8 @@ struct drm_psb_private {
  40         uint32_t saveMIPI_CONTROL_REG;
  41         uint32_t saveMIPI;
  42         void (*init_drvIC)(struct drm_device *dev);
  43 +       void (*dsi_prePowerState)(struct drm_device *dev);
  44 +       void (*dsi_postPowerState)(struct drm_device *dev);
  45
  46         /* DPST Register Save */
  47         uint32_t saveHISTOGRAM_INT_CONTROL_REG;
  48 diff --git a/drivers/gpu/drm/mrst/drv/psb_intel_display.c b/drivers/gpu/drm/mrst/drv/psb_intel_display.c
  49 index 10c6dec..72d42eb 100644
  50 --- a/drivers/gpu/drm/mrst/drv/psb_intel_display.c
  51 +++ b/drivers/gpu/drm/mrst/drv/psb_intel_display.c
  52 @@ -2089,6 +2089,7 @@ static void mrst_crtc_dpms(struct drm_crtc *crtc, int mode)
  53  {
  54         struct drm_device *dev = crtc->dev;
  55         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
  56 +       struct drm_psb_private *dev_priv = dev->dev_private;
  57         int pipe = psb_intel_crtc->pipe;
  58         int dpll_reg = (pipe == 0) ? MRST_DPLL_A : DPLL_B;
  59         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
  60 @@ -2130,18 +2131,22 @@ static void mrst_crtc_dpms(struct drm_crtc *crtc, int mode)
  61                         udelay(150);
  62                 }
  63
  64 -               /* Enable the pipe */
  65 -               temp = REG_READ(pipeconf_reg);
  66 -               if ((temp & PIPEACONF_ENABLE) == 0)
  67 -                       REG_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
  68 -
  69 -               /* Enable the plane */
  70 -               temp = REG_READ(dspcntr_reg);
  71 -               if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
  72 -                       REG_WRITE(dspcntr_reg,
  73 -                                 temp | DISPLAY_PLANE_ENABLE);
  74 -                       /* Flush the plane changes */
  75 -                       REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
  76 +               if (dev_priv->iLVDS_enable ||
  77 +                                       !dev_priv->dsi_plane_pipe_control) {
  78 +                       /* Enable the pipe */
  79 +                       temp = REG_READ(pipeconf_reg);
  80 +                       if ((temp & PIPEACONF_ENABLE) == 0)
  81 +                               REG_WRITE(pipeconf_reg,
  82 +                                               temp | PIPEACONF_ENABLE);
  83 +
  84 +                       /* Enable the plane */
  85 +                       temp = REG_READ(dspcntr_reg);
  86 +                       if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
  87 +                               REG_WRITE(dspcntr_reg,
  88 +                                         temp | DISPLAY_PLANE_ENABLE);
  89 +                               /* Flush the plane changes */
  90 +                               REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
  91 +                       }
  92                 }
  93
  94                 psb_intel_crtc_load_lut(crtc);
  95 @@ -2158,30 +2163,34 @@ static void mrst_crtc_dpms(struct drm_crtc *crtc, int mode)
  96                 /* Disable the VGA plane that we never use */
  97                 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
  98
  99 -               /* Disable display plane */
 100 -               temp = REG_READ(dspcntr_reg);
 101 -               if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
 102 -                       REG_WRITE(dspcntr_reg,
 103 -                                 temp & ~DISPLAY_PLANE_ENABLE);
 104 -                       /* Flush the plane changes */
 105 -                       REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
 106 -                       REG_READ(dspbase_reg);
 107 -               }
 108 +               if (dev_priv->iLVDS_enable ||
 109 +                                       !dev_priv->dsi_plane_pipe_control) {
 110 +                       /* Disable display plane */
 111 +                       temp = REG_READ(dspcntr_reg);
 112 +                       if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
 113 +                               REG_WRITE(dspcntr_reg,
 114 +                                         temp & ~DISPLAY_PLANE_ENABLE);
 115 +                               /* Flush the plane changes */
 116 +                               REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
 117 +                               REG_READ(dspbase_reg);
 118 +                       }
 119
 120 -               if (!IS_I9XX(dev)) {
 121 -                       /* Wait for vblank for the disable to take effect */
 122 -                       psb_intel_wait_for_vblank(dev);
 123 -               }
 124 +                       if (!IS_I9XX(dev)) {
 125 +                               /* Wait for vblank for the disable to take effect */
 126 +                               psb_intel_wait_for_vblank(dev);
 127 +                       }
 128
 129 -               /* Next, disable display pipes */
 130 -               temp = REG_READ(pipeconf_reg);
 131 -               if ((temp & PIPEACONF_ENABLE) != 0) {
 132 -                       REG_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
 133 -                       REG_READ(pipeconf_reg);
 134 -               }
 135 +                       /* Next, disable display pipes */
 136 +                       temp = REG_READ(pipeconf_reg);
 137 +                       if ((temp & PIPEACONF_ENABLE) != 0) {
 138 +                               REG_WRITE(pipeconf_reg,
 139 +                                               temp & ~PIPEACONF_ENABLE);
 140 +                               REG_READ(pipeconf_reg);
 141 +                       }
 142
 143 -               /* Wait for for the pipe disable to take effect. */
 144 -               mrstWaitForPipeDisable(dev);
 145 +                       /* Wait for for the pipe disable to take effect. */
 146 +                       mrstWaitForPipeDisable(dev);
 147 +               }
 148
 149                 temp = REG_READ(dpll_reg);
 150                 if ((temp & DPLL_VCO_ENABLE) != 0) {
 151 diff --git a/drivers/gpu/drm/mrst/drv/psb_intel_dsi.c b/drivers/gpu/drm/mrst/drv/psb_intel_dsi.c
 152 index 3d45df8..eb6cb2a 100644
 153 --- a/drivers/gpu/drm/mrst/drv/psb_intel_dsi.c
 154 +++ b/drivers/gpu/drm/mrst/drv/psb_intel_dsi.c
 155 @@ -18,6 +18,11 @@
 156   *     jim liu <jim.liu@intel.com>
 157   */
 158
 159 +#define USE_AAVA_VERSION
 160 +#ifdef USE_AAVA_VERSION
 161 +#include "psb_intel_dsi_aava.c"
 162 +#else
 163 +
 164  #include <linux/backlight.h>
 165  #include <drm/drmP.h>
 166  #include <drm/drm.h>
 167 @@ -2448,3 +2453,7 @@ failed_find:
 168         drm_connector_cleanup(connector);
 169         kfree(connector);
 170  }
 171 +
 172 +#endif /* USE_AAVA_VERSION */
 173 +
 174 +
 175 diff --git a/drivers/gpu/drm/mrst/drv/psb_intel_dsi_aava.c b/drivers/gpu/drm/mrst/drv/psb_intel_dsi_aava.c
 176 index 6c21480..9e761c6 100644
 177 --- a/drivers/gpu/drm/mrst/drv/psb_intel_dsi_aava.c
 178 +++ b/drivers/gpu/drm/mrst/drv/psb_intel_dsi_aava.c
 179 @@ -1,32 +1,4 @@
 180 -/*
 181 - * Copyright © 2006-2007 Intel Corporation
 182 - *
 183 - * Permission is hereby granted, free of charge, to any person obtaining a
 184 - * copy of this software and associated documentation files (the "Software"),
 185 - * to deal in the Software without restriction, including without limitation
 186 - * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 187 - * and/or sell copies of the Software, and to permit persons to whom the
 188 - * Software is furnished to do so, subject to the following conditions:
 189 - *
 190 - * The above copyright notice and this permission notice (including the next
 191 - * paragraph) shall be included in all copies or substantial portions of the
 192 - * Software.
 193 - *
 194 - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 195 - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 196 - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 197 - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 198 - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 199 - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 200 - * DEALINGS IN THE SOFTWARE.
 201 - *
 202 - * Authors:
 203 - *     jim liu <jim.liu@intel.com>
 204 - */
 205 -
 206 -/* This enables setting backlights on with a delay at startup,
 207 -   should be removed after resolving issue with backlights going off
 208 -   after setting them on in initial mrst_dsi_set_power call */
 209 +
 210  #define AAVA_BACKLIGHT_HACK
 211
 212  #include <linux/backlight.h>
 213 @@ -34,26 +6,33 @@
 214  #include <drm/drm.h>
 215  #include <drm/drm_crtc.h>
 216  #include <drm/drm_edid.h>
 217 -
 218  #include <asm/ipc_defs.h>
 219
 220 -#ifdef AAVA_BACKLIGHT_HACK
 221 -#include <linux/workqueue.h>
 222 -#endif /* AAVA_BACKLIGHT_HACK */
 223 -
 224  #include "psb_drv.h"
 225  #include "psb_intel_drv.h"
 226  #include "psb_intel_reg.h"
 227  #include "ospm_power.h"
 228
 229 -#define DRM_MODE_ENCODER_MIPI   5
 230 +#ifdef AAVA_BACKLIGHT_HACK
 231 +#include <linux/workqueue.h>
 232 +#endif /* AAVA_BACKLIGHT_HACK */
 233
 234 -//#define DBG_PRINTS 1
 235 -#define DBG_PRINTS 0
 236 +/* Debug trace definitions */
 237 +#define DBG_LEVEL 1
 238
 239 -#define NEW_CRAP_SAMPLE_SETTINGS
 240 +#if (DBG_LEVEL > 0)
 241 +#define DBG_TRACE(format,args...) printk(KERN_ERR "%s: " format "\n", \
 242 +                                               __FUNCTION__ , ## args)
 243 +#else
 244 +#define DBG_TRACE(format,args...)
 245 +#endif
 246 +
 247 +#define DBG_ERR(format,args...) printk(KERN_ERR "%s: " format "\n", \
 248 +                                               __FUNCTION__ , ## args)
 249
 250 -#define AAVA_EV_0_5
 251 +#define BRIGHTNESS_MAX_LEVEL 100
 252 +
 253 +#define DRM_MODE_ENCODER_MIPI   5
 254
 255  #define VSIZE          480
 256  #define HSIZE          864
 257 @@ -84,686 +63,633 @@
 258  #define DISP_VSYNC_START       (DISP_VBLANK_START + VFP_LINES - 1)
 259  #define DISP_VSYNC_END         (DISP_VSYNC_START + VSYNC_LINES - 1)
 260
 261 -#define BRIGHTNESS_MAX_LEVEL 100
 262 +#define MAX_FIFO_WAIT_MS       100
 263
 264  static unsigned int dphy_reg = 0x0d0a7f06;
 265  static unsigned int mipi_clock = 0x2;
 266
 267  #ifdef AAVA_BACKLIGHT_HACK
 268 -static void bl_work_handler(struct work_struct *work);
 269 -DECLARE_DELAYED_WORK(bl_work, bl_work_handler);
 270 +static void dsi_bl_work_handler(struct work_struct *work);
 271 +DECLARE_DELAYED_WORK(bl_work, dsi_bl_work_handler);
 272  #endif /* AAVA_BACKLIGHT_HACK */
 273
 274  // Temporary access from sysfs begin
 275 -static struct drm_encoder *orig_encoder;
 276 -static void mrst_dsi_prepare(struct drm_encoder *encoder);
 277 -static void mrst_dsi_commit(struct drm_encoder *encoder);
 278 -static void mrst_dsi_mode_set(struct drm_encoder *encoder,
 279 -                             struct drm_display_mode *mode,
 280 -                             struct drm_display_mode *adjusted_mode);
 281 -static void panel_reset(void);
 282 -
 283 -static ssize_t dphy_store(struct class *class, const char *buf, size_t len)
 284 +static struct drm_device *test_dev;
 285 +// Temporary access from sysfs end
 286 +
 287 +
 288 +static int dsi_wait_hs_data_fifo(struct drm_device *dev)
 289  {
 290 -       ssize_t status;
 291 -       unsigned long value;
 292 +       int fifo_wait_time = 0;
 293
 294 -       status = strict_strtoul(buf, 16, &value);
 295 -       dphy_reg = value;
 296 -       printk("!!! dphy_reg = %x, clock = %x\n", dphy_reg, mipi_clock);
 297 +       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_DATA_FIFO_FULL) ==
 298 +                                                       HS_DATA_FIFO_FULL) {
 299 +               if (fifo_wait_time == MAX_FIFO_WAIT_MS) {
 300 +                       DBG_ERR("timeout");
 301 +                       return -1;
 302 +               }
 303 +               udelay(1000);
 304 +               fifo_wait_time++;
 305 +       }
 306 +       return 0;
 307 +}
 308
 309 -       return len;
 310 +static int dsi_wait_hs_ctrl_fifo(struct drm_device *dev)
 311 +{
 312 +       int fifo_wait_time = 0;
 313 +
 314 +       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_CTRL_FIFO_FULL) ==
 315 +                                                       HS_CTRL_FIFO_FULL) {
 316 +               if (fifo_wait_time == MAX_FIFO_WAIT_MS) {
 317 +                       DBG_ERR("timeout");
 318 +                       return -1;
 319 +               }
 320 +               udelay(1000);
 321 +               fifo_wait_time++;
 322 +       }
 323 +       return 0;
 324  }
 325
 326 -static ssize_t clock_store(struct class *class, const char *buf, size_t len)
 327 +static void dsi_set_backlight_state(int state)
 328  {
 329 -       ssize_t status;
 330 -       unsigned long value;
 331 +       struct ipc_pmic_reg_data tmp_reg;
 332
 333 -       status = strict_strtoul(buf, 0, &value);
 334 -       mipi_clock = value;
 335 -       printk("!!! dphy_reg = %x, clock = %x\n", dphy_reg, mipi_clock);
 336 +       DBG_TRACE("%d", state);
 337
 338 -       return len;
 339 +       tmp_reg.ioc = 1;
 340 +       tmp_reg.num_entries = 2;
 341 +       tmp_reg.pmic_reg_data[0].register_address = 0x2a;
 342 +       tmp_reg.pmic_reg_data[1].register_address = 0x28;
 343 +
 344 +       if (state) {
 345 +               tmp_reg.pmic_reg_data[0].value = 0xaa;
 346 +               tmp_reg.pmic_reg_data[1].value = 0x30;
 347 +       } else {
 348 +               tmp_reg.pmic_reg_data[0].value = 0x00;
 349 +               tmp_reg.pmic_reg_data[1].value = 0x00;
 350 +       }
 351 +
 352 +       if (ipc_pmic_register_write(&tmp_reg, TRUE))
 353 +               DBG_ERR("pmic reg write failed");
 354  }
 355
 356 -static ssize_t apply_settings(struct class *class, const char *buf, size_t len)
 357 +
 358 +#ifdef AAVA_BACKLIGHT_HACK
 359 +static void dsi_bl_work_handler(struct work_struct *work)
 360  {
 361 -       ssize_t status;
 362 -       long value;
 363 +       DBG_TRACE("");
 364 +       dsi_set_backlight_state(1);
 365 +}
 366 +#endif /* AAVA_BACKLIGHT_HACK */
 367
 368 -       printk("!!! dphy_reg = %x, clock = %x\n", dphy_reg, mipi_clock);
 369
 370 -       status = strict_strtoul(buf, 0, &value);
 371 -       if (value > 0) {
 372 -               mrst_dsi_prepare(orig_encoder);
 373 -               msleep(500);
 374 -               if (value > 1) {
 375 -                       panel_reset();
 376 -                       msleep(500);
 377 -               }
 378 -               mrst_dsi_mode_set(orig_encoder, NULL, NULL);
 379 -               msleep(500);
 380 -               mrst_dsi_commit(orig_encoder);
 381 +static void dsi_set_panel_reset_state(int state)
 382 +{
 383 +       struct ipc_pmic_reg_data tmp_reg = {0};
 384 +
 385 +       DBG_TRACE("%d", state);
 386 +
 387 +       tmp_reg.ioc = 1;
 388 +       tmp_reg.num_entries = 1;
 389 +       tmp_reg.pmic_reg_data[0].register_address = 0xe6;
 390 +
 391 +       if (state)
 392 +               tmp_reg.pmic_reg_data[0].value = 0x01;
 393 +       else
 394 +               tmp_reg.pmic_reg_data[0].value = 0x09;
 395 +
 396 +       if (ipc_pmic_register_write(&tmp_reg, TRUE)) {
 397 +               DBG_ERR("pmic reg write failed");
 398 +               return;
 399         }
 400
 401 -       return len;
 402 +       if (state) {
 403 +               /* Minimum active time to trigger reset is 10us */
 404 +               udelay(10);
 405 +       } else {
 406 +               /* Maximum startup time from reset is 120ms */
 407 +               msleep(120);
 408 +       }
 409  }
 410 -// Temporary access from sysfs end
 411
 412 -static void panel_init(struct drm_device *dev)
 413 +
 414 +static void dsi_init_panel(struct drm_device *dev)
 415  {
 416 -#if DBG_PRINTS
 417 -       printk("panel_init\n");
 418 -#endif /* DBG_PRINTS */
 419 +       DBG_TRACE("");
 420
 421 -       /* Flip page order */
 422 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_DATA_FIFO_FULL) ==
 423 -                                                       HS_DATA_FIFO_FULL);
 424 +       /* Flip page order to have correct image orientation */
 425 +       if (dsi_wait_hs_data_fifo(dev) < 0)
 426 +               return;
 427         REG_WRITE(0xb068, 0x00008036);
 428 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_CTRL_FIFO_FULL) ==
 429 -                                                       HS_CTRL_FIFO_FULL);
 430 +       if (dsi_wait_hs_ctrl_fifo(dev) < 0)
 431 +               return;
 432         REG_WRITE(0xb070, 0x00000229);
 433
 434 -#ifdef NEW_CRAP_SAMPLE_SETTINGS
 435 -       // 0xF0, for new crap displays
 436 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_DATA_FIFO_FULL) ==
 437 -                                                       HS_DATA_FIFO_FULL);
 438 -       REG_WRITE(0xb068, 0x005a5af0);
 439 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_CTRL_FIFO_FULL) ==
 440 -                                                       HS_CTRL_FIFO_FULL);
 441 +       /* Write protection key to allow DM bit setting */
 442 +       if (dsi_wait_hs_data_fifo(dev) < 0)
 443 +               return;
 444 +       REG_WRITE(0xb068, 0x005a5af1);
 445 +       if (dsi_wait_hs_ctrl_fifo(dev) < 0)
 446 +               return;
 447         REG_WRITE(0xb070, 0x00000329);
 448 -#endif
 449
 450 -       /* Write protection key */
 451 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_DATA_FIFO_FULL) ==
 452 -                                                       HS_DATA_FIFO_FULL);
 453 -       REG_WRITE(0xb068, 0x005a5af1);
 454 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_CTRL_FIFO_FULL) ==
 455 -                                                       HS_CTRL_FIFO_FULL);
 456 +       /* Set DM bit to enable video mode */
 457 +       if (dsi_wait_hs_data_fifo(dev) < 0)
 458 +               return;
 459 +       REG_WRITE(0xb068, 0x000100f7);
 460 +       if (dsi_wait_hs_ctrl_fifo(dev) < 0)
 461 +               return;
 462         REG_WRITE(0xb070, 0x00000329);
 463
 464 -#ifdef NEW_CRAP_SAMPLE_SETTINGS
 465 -       // 0xFC, for new crap displays
 466 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_DATA_FIFO_FULL) ==
 467 -                                                       HS_DATA_FIFO_FULL);
 468 +       /* Write protection keys to allow TCON setting */
 469 +       if (dsi_wait_hs_data_fifo(dev) < 0)
 470 +               return;
 471 +       REG_WRITE(0xb068, 0x005a5af0);
 472 +       if (dsi_wait_hs_ctrl_fifo(dev) < 0)
 473 +               return;
 474 +       REG_WRITE(0xb070, 0x00000329);
 475 +
 476 +       if (dsi_wait_hs_data_fifo(dev) < 0)
 477 +               return;
 478         REG_WRITE(0xb068, 0x005a5afc);
 479 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_CTRL_FIFO_FULL) ==
 480 -                                                       HS_CTRL_FIFO_FULL);
 481 +       if (dsi_wait_hs_ctrl_fifo(dev) < 0)
 482 +               return;
 483         REG_WRITE(0xb070, 0x00000329);
 484
 485 -       // 0xB7, for new crap displays
 486 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_DATA_FIFO_FULL) ==
 487 -                                                       HS_DATA_FIFO_FULL);
 488 -#ifdef DOES_NOT_WORK
 489 -       /* Suggested by TPO, doesn't work as usual */
 490 +       /* Write TCON setting */
 491 +       if (dsi_wait_hs_data_fifo(dev) < 0)
 492 +               return;
 493 +#if 0
 494 +       /* Suggested by TPO, doesn't work */
 495         REG_WRITE(0xb068, 0x110000b7);
 496         REG_WRITE(0xb068, 0x00000044);
 497  #else
 498         REG_WRITE(0xb068, 0x770000b7);
 499         REG_WRITE(0xb068, 0x00000044);
 500  #endif
 501 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_CTRL_FIFO_FULL) ==
 502 -                                                       HS_CTRL_FIFO_FULL);
 503 +       if (dsi_wait_hs_ctrl_fifo(dev) < 0)
 504 +               return;
 505         REG_WRITE(0xb070, 0x00000529);
 506 +}
 507
 508 -       // 0xB6, for new crap displays
 509 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_DATA_FIFO_FULL) ==
 510 -                                                       HS_DATA_FIFO_FULL);
 511 -       REG_WRITE(0xb068, 0x000a0ab6);
 512 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_CTRL_FIFO_FULL) ==
 513 -                                                       HS_CTRL_FIFO_FULL);
 514 -       REG_WRITE(0xb070, 0x00000329);
 515
 516 -       // 0xF2, for new crap displays
 517 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_DATA_FIFO_FULL) ==
 518 -                                                       HS_DATA_FIFO_FULL);
 519 -       REG_WRITE(0xb068, 0x081010f2);
 520 -       REG_WRITE(0xb068, 0x4a070708);
 521 -       REG_WRITE(0xb068, 0x000000c5);
 522 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_CTRL_FIFO_FULL) ==
 523 -                                                       HS_CTRL_FIFO_FULL);
 524 -       REG_WRITE(0xb070, 0x00000929);
 525 +static void dsi_set_ptarget_state(struct drm_device *dev, int state)
 526 +{
 527 +       u32 pp_sts_reg;
 528
 529 -       // 0xF8, for new crap displays
 530 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_DATA_FIFO_FULL) ==
 531 -                                                       HS_DATA_FIFO_FULL);
 532 -       REG_WRITE(0xb068, 0x024003f8);
 533 -       REG_WRITE(0xb068, 0x01030a04);
 534 -       REG_WRITE(0xb068, 0x0e020220);
 535 -       REG_WRITE(0xb068, 0x00000004);
 536 +       DBG_TRACE("%d", state);
 537
 538 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_CTRL_FIFO_FULL) ==
 539 -                                                       HS_CTRL_FIFO_FULL);
 540 -       REG_WRITE(0xb070, 0x00000d29);
 541 +       if (state) {
 542 +               REG_WRITE(PP_CONTROL, (REG_READ(PP_CONTROL) | POWER_TARGET_ON));
 543 +               do {
 544 +                       pp_sts_reg = REG_READ(PP_STATUS);
 545 +               } while ((pp_sts_reg & (PP_ON | PP_READY)) == PP_READY);
 546 +       } else {
 547 +               REG_WRITE(PP_CONTROL,
 548 +                               (REG_READ(PP_CONTROL) & ~POWER_TARGET_ON));
 549 +               do {
 550 +                       pp_sts_reg = REG_READ(PP_STATUS);
 551 +               } while (pp_sts_reg & PP_ON);
 552 +       }
 553 +}
 554
 555 -       // 0xE2, for new crap displays
 556 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_DATA_FIFO_FULL) ==
 557 -                                                       HS_DATA_FIFO_FULL);
 558 -       REG_WRITE(0xb068, 0x398fc3e2);
 559 -       REG_WRITE(0xb068, 0x0000916f);
 560 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_CTRL_FIFO_FULL) ==
 561 -                                                       HS_CTRL_FIFO_FULL);
 562 -       REG_WRITE(0xb070, 0x00000629);
 563
 564 -#ifdef DOES_NOT_WORK
 565 -       /* Suggested by TPO, doesn't work as usual */
 566 -       // 0xE3, for new crap displays
 567 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_DATA_FIFO_FULL) ==
 568 -                                                       HS_DATA_FIFO_FULL);
 569 -       REG_WRITE(0xb068, 0x20f684e3);
 570 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_CTRL_FIFO_FULL) ==
 571 -                                                       HS_CTRL_FIFO_FULL);
 572 -       REG_WRITE(0xb070, 0x00000429);
 573 +static void dsi_send_turn_on_packet(struct drm_device *dev)
 574 +{
 575 +       DBG_TRACE("");
 576
 577 -       msleep(50);
 578 -#endif
 579 +       REG_WRITE(DPI_CONTROL_REG, DPI_TURN_ON);
 580
 581 -       // 0xB0, for new crap displays
 582 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_DATA_FIFO_FULL) ==
 583 -                                                       HS_DATA_FIFO_FULL);
 584 -       REG_WRITE(0xb068, 0x000000b0);
 585 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_CTRL_FIFO_FULL) ==
 586 -                                                       HS_CTRL_FIFO_FULL);
 587 -       REG_WRITE(0xb070, 0x00000229);
 588 +       /* Short delay to wait that display turns on */
 589 +       msleep(10);
 590 +}
 591
 592 -       // 0xF4, for new crap displays
 593 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_DATA_FIFO_FULL) ==
 594 -                                                       HS_DATA_FIFO_FULL);
 595 -       REG_WRITE(0xb068, 0x240242f4);
 596 -       REG_WRITE(0xb068, 0x78ee2002);
 597 -       REG_WRITE(0xb068, 0x2a071050);
 598 -       REG_WRITE(0xb068, 0x507fee10);
 599 -       REG_WRITE(0xb068, 0x10300710);
 600 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_CTRL_FIFO_FULL) ==
 601 -                                                       HS_CTRL_FIFO_FULL);
 602 -       REG_WRITE(0xb070, 0x00001429);
 603
 604 -       // 0xBA, for new crap displays
 605 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_DATA_FIFO_FULL) ==
 606 -                                                       HS_DATA_FIFO_FULL);
 607 -       REG_WRITE(0xb068, 0x19fe07ba);
 608 -       REG_WRITE(0xb068, 0x101c0a31);
 609 -       REG_WRITE(0xb068, 0x00000010);
 610 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_CTRL_FIFO_FULL) ==
 611 -                                                       HS_CTRL_FIFO_FULL);
 612 -       REG_WRITE(0xb070, 0x00000929);
 613 +static void dsi_send_shutdown_packet(struct drm_device *dev)
 614 +{
 615 +       DBG_TRACE("");
 616
 617 -       // 0xBB, for new crap displays
 618 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_DATA_FIFO_FULL) ==
 619 -                                                       HS_DATA_FIFO_FULL);
 620 -       REG_WRITE(0xb068, 0x28ff07bb);
 621 -       REG_WRITE(0xb068, 0x24280a31);
 622 -       REG_WRITE(0xb068, 0x00000034);
 623 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_CTRL_FIFO_FULL) ==
 624 -                                                       HS_CTRL_FIFO_FULL);
 625 -       REG_WRITE(0xb070, 0x00000929);
 626 +       REG_WRITE(DPI_CONTROL_REG, DPI_SHUT_DOWN);
 627 +}
 628
 629 -       // 0xFB, for new crap displays
 630 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_DATA_FIFO_FULL) ==
 631 -                                                       HS_DATA_FIFO_FULL);
 632 -       REG_WRITE(0xb068, 0x535d05fb);
 633 -       REG_WRITE(0xb068, 0x1b1a2130);
 634 -       REG_WRITE(0xb068, 0x221e180e);
 635 -       REG_WRITE(0xb068, 0x131d2120);
 636 -       REG_WRITE(0xb068, 0x535d0508);
 637 -       REG_WRITE(0xb068, 0x1c1a2131);
 638 -       REG_WRITE(0xb068, 0x231f160d);
 639 -       REG_WRITE(0xb068, 0x111b2220);
 640 -       REG_WRITE(0xb068, 0x535c2008);
 641 -       REG_WRITE(0xb068, 0x1f1d2433);
 642 -       REG_WRITE(0xb068, 0x2c251a10);
 643 -       REG_WRITE(0xb068, 0x2c34372d);
 644 -       REG_WRITE(0xb068, 0x00000023);
 645 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_CTRL_FIFO_FULL) ==
 646 -                                                       HS_CTRL_FIFO_FULL);
 647 -       REG_WRITE(0xb070, 0x00003129);
 648
 649 -       // 0xFA, for new crap displays
 650 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_DATA_FIFO_FULL) ==
 651 -                                                       HS_DATA_FIFO_FULL);
 652 -       REG_WRITE(0xb068, 0x525c0bfa);
 653 -       REG_WRITE(0xb068, 0x1c1c232f);
 654 -       REG_WRITE(0xb068, 0x2623190e);
 655 -       REG_WRITE(0xb068, 0x18212625);
 656 -       REG_WRITE(0xb068, 0x545d0d0e);
 657 -       REG_WRITE(0xb068, 0x1e1d2333);
 658 -       REG_WRITE(0xb068, 0x26231a10);
 659 -       REG_WRITE(0xb068, 0x1a222725);
 660 -       REG_WRITE(0xb068, 0x545d280f);
 661 -       REG_WRITE(0xb068, 0x21202635);
 662 -       REG_WRITE(0xb068, 0x31292013);
 663 -       REG_WRITE(0xb068, 0x31393d33);
 664 -       REG_WRITE(0xb068, 0x00000029);
 665 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_CTRL_FIFO_FULL) ==
 666 -                                                       HS_CTRL_FIFO_FULL);
 667 -       REG_WRITE(0xb070, 0x00003129);
 668 -#endif
 669 +static void dsi_set_pipe_plane_enable_state(struct drm_device *dev, int state)
 670 +{
 671 +       u32 temp_reg;
 672
 673 -       /* Set DM */
 674 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_DATA_FIFO_FULL) ==
 675 -                                                       HS_DATA_FIFO_FULL);
 676 -       REG_WRITE(0xb068, 0x000100f7);
 677 -       while ((REG_READ(GEN_FIFO_STAT_REG) & HS_CTRL_FIFO_FULL) ==
 678 -                                                       HS_CTRL_FIFO_FULL);
 679 -       REG_WRITE(0xb070, 0x00000329);
 680 -}
 681 +       DBG_TRACE("%d", state);
 682
 683 +       if (state) {
 684 +               /* Enable pipe */
 685 +               temp_reg = REG_READ(PIPEACONF);
 686 +               temp_reg |= (PIPEACONF_ENABLE);
 687 +               REG_WRITE(PIPEACONF, temp_reg);
 688 +               temp_reg = REG_READ(PIPEACONF);
 689
 690 -static void panel_reset_on(void)
 691 -{
 692 -       struct ipc_pmic_reg_data tmp_reg = {0};
 693 -#if DBG_PRINTS
 694 -       printk("panel_reset_on\n");
 695 -#endif /* DBG_PRINTS */
 696 -       tmp_reg.ioc = 1;
 697 -       tmp_reg.num_entries = 1;
 698 -#ifdef AAVA_EV_0_5
 699 -       tmp_reg.pmic_reg_data[0].register_address = 0xe6;
 700 -       tmp_reg.pmic_reg_data[0].value = 0x01;
 701 -#else /* CDK */
 702 -       tmp_reg.pmic_reg_data[0].register_address = 0xf4;
 703 -       if (ipc_pmic_register_read(&tmp_reg)) {
 704 -               printk("panel_reset_on: failed to read pmic reg 0xf4!\n");
 705 -               return;
 706 -       }
 707 -       tmp_reg.pmic_reg_data[0].value &= 0xbf;
 708 -#endif /* AAVA_EV_0_5 */
 709 -       if (ipc_pmic_register_write(&tmp_reg, TRUE)) {
 710 -               printk("panel_reset_on: failed to write pmic reg 0xe6!\n");
 711 -       }
 712 -}
 713 +               /* Wait for 20ms for the pipe enable to take effect. */
 714 +               msleep(20);
 715
 716 +               /* Enable plane */
 717 +               temp_reg = REG_READ(DSPACNTR);
 718 +               temp_reg |= (DISPLAY_PLANE_ENABLE);
 719 +               REG_WRITE(DSPACNTR, temp_reg);
 720 +               temp_reg = REG_READ(DSPACNTR);
 721
 722 -static void panel_reset_off(void)
 723 -{
 724 -       struct ipc_pmic_reg_data tmp_reg = {0};
 725 -#if DBG_PRINTS
 726 -       printk("panel_reset_off\n");
 727 -#endif /* DBG_PRINTS */
 728 -       tmp_reg.ioc = 1;
 729 -       tmp_reg.num_entries = 1;
 730 -#ifdef AAVA_EV_0_5
 731 -       tmp_reg.pmic_reg_data[0].register_address = 0xe6;
 732 -       tmp_reg.pmic_reg_data[0].value = 0x09;
 733 -#else /* CDK */
 734 -       tmp_reg.pmic_reg_data[0].register_address = 0xf4;
 735 -       if (ipc_pmic_register_read(&tmp_reg)) {
 736 -               printk("panel_reset_off: failed to read pmic reg 0xf4!\n");
 737 -               return;
 738 -       }
 739 -       tmp_reg.pmic_reg_data[0].value |= 0x40;
 740 -#endif /* AAVA_EV_0_5 */
 741 -       if (ipc_pmic_register_write(&tmp_reg, TRUE)) {
 742 -               printk("panel_reset_off: failed to write pmic reg 0xe6!\n");
 743 +               /* Flush plane change by read/write/read of BASE reg */
 744 +               temp_reg = REG_READ(MRST_DSPABASE);
 745 +               REG_WRITE(MRST_DSPABASE, temp_reg);
 746 +               temp_reg = REG_READ(MRST_DSPABASE);
 747 +
 748 +               /* Wait for 20ms for the plane enable to take effect. */
 749 +               msleep(20);
 750 +       } else {
 751 +               /* Disable plane */
 752 +               temp_reg = REG_READ(DSPACNTR);
 753 +               temp_reg &= ~(DISPLAY_PLANE_ENABLE);
 754 +               REG_WRITE(DSPACNTR, temp_reg);
 755 +               temp_reg = REG_READ(DSPACNTR);
 756 +
 757 +               /* Flush plane change by read/write/read of BASE reg */
 758 +               temp_reg = REG_READ(MRST_DSPABASE);
 759 +               REG_WRITE(MRST_DSPABASE, temp_reg);
 760 +               temp_reg = REG_READ(MRST_DSPABASE);
 761 +
 762 +               /* Wait for 20ms for the plane disable to take effect. */
 763 +               msleep(20);
 764 +
 765 +               /* Disable pipe */
 766 +               temp_reg = REG_READ(PIPEACONF);
 767 +               temp_reg &= ~(PIPEACONF_ENABLE);
 768 +               REG_WRITE(PIPEACONF, temp_reg);
 769 +               temp_reg = REG_READ(PIPEACONF);
 770 +
 771 +               /* Wait for 20ms for the pipe disable to take effect. */
 772 +               msleep(20);
 773         }
 774  }
 775
 776
 777 -static void panel_reset(void)
 778 +static void dsi_set_device_ready_state(struct drm_device *dev, int state)
 779  {
 780 -#if DBG_PRINTS
 781 -       printk("panel_reset\n");
 782 -#endif /* DBG_PRINTS */
 783 -
 784 -       panel_reset_on();
 785 -       msleep(20);
 786 -       panel_reset_off();
 787 -       msleep(20);
 788 +       DBG_TRACE("%d", state);
 789 +
 790 +       if (state)
 791 +               REG_WRITE(DEVICE_READY_REG, 0x00000001);
 792 +       else
 793 +               REG_WRITE(DEVICE_READY_REG, 0x00000000);
 794  }
 795
 796
 797 -static void backlight_state(bool on)
 798 +static void dsi_configure_mipi_block(struct drm_device *dev)
 799  {
 800 -       struct ipc_pmic_reg_data tmp_reg;
 801 +       DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
 802 +       u32 color_format = (RGB_888_FMT << FMT_DPI_POS);
 803 +       u32 res = 0;
 804
 805 -#if DBG_PRINTS
 806 -       printk("backlight_state\n");
 807 -#endif /* DBG_PRINTS */
 808 +       DBG_TRACE("");
 809
 810 -       tmp_reg.ioc = 1;
 811 -       tmp_reg.num_entries = 2;
 812 -       tmp_reg.pmic_reg_data[0].register_address = 0x2a;
 813 -       tmp_reg.pmic_reg_data[1].register_address = 0x28;
 814 +       /* MIPI clock ratio 1:1 */
 815 +       //REG_WRITE(MIPI_CONTROL_REG, 0x00000018);
 816 +       //REG_WRITE(0xb080, 0x0b061a02);
 817
 818 -       if( on ) {
 819 -#if DBG_PRINTS
 820 -               printk("backlight_state: ON\n");
 821 -#endif /* DBG_PRINTS */
 822 -               tmp_reg.pmic_reg_data[0].value = 0xaa;
 823 -#ifdef AAVA_EV_0_5
 824 -               tmp_reg.pmic_reg_data[1].value = 0x30;
 825 -#else /* CDK */
 826 -               tmp_reg.pmic_reg_data[1].value = 0x60;
 827 -#endif /* AAVA_EV_0_5 */
 828 -       } else {
 829 -#if DBG_PRINTS
 830 -               printk("backlight_state: OFF\n");
 831 -#endif /* DBG_PRINTS */
 832 -               tmp_reg.pmic_reg_data[0].value = 0x00;
 833 -               tmp_reg.pmic_reg_data[1].value = 0x00;
 834 -       }
 835 +       /* MIPI clock ratio 2:1 */
 836 +       //REG_WRITE(MIPI_CONTROL_REG, 0x00000019);
 837 +       //REG_WRITE(0xb080, 0x3f1f1c04);
 838
 839 -       if (ipc_pmic_register_write(&tmp_reg, TRUE)) {
 840 -               printk("backlight_state: failed to write pmic regs 0x2a and 0x28!\n");
 841 -       }
 842 -}
 843 +       /* MIPI clock ratio 3:1 */
 844 +       //REG_WRITE(MIPI_CONTROL_REG, 0x0000001a);
 845 +       //REG_WRITE(0xb080, 0x091f7f08);
 846
 847 -#ifdef AAVA_BACKLIGHT_HACK
 848 -static void bl_work_handler(struct work_struct *work)
 849 -{
 850 -       backlight_state(true);
 851 +       /* MIPI clock ratio 4:1 */
 852 +       REG_WRITE(MIPI_CONTROL_REG, (0x00000018 | mipi_clock));
 853 +       REG_WRITE(0xb080, dphy_reg);
 854 +
 855 +       /* Enable all interrupts */
 856 +       REG_WRITE(INTR_EN_REG, 0xffffffff);
 857 +
 858 +       REG_WRITE(TURN_AROUND_TIMEOUT_REG, 0x0000000A);
 859 +       REG_WRITE(DEVICE_RESET_REG, 0x000000ff);
 860 +       REG_WRITE(INIT_COUNT_REG, 0x00000fff);
 861 +       REG_WRITE(HS_TX_TIMEOUT_REG, 0x90000);
 862 +       REG_WRITE(LP_RX_TIMEOUT_REG, 0xffff);
 863 +       REG_WRITE(HIGH_LOW_SWITCH_COUNT_REG, 0x46);
 864 +       REG_WRITE(EOT_DISABLE_REG, 0x00000000);
 865 +       REG_WRITE(LP_BYTECLK_REG, 0x00000004);
 866 +
 867 +       REG_WRITE(VIDEO_FMT_REG, dev_priv->videoModeFormat);
 868 +
 869 +       REG_WRITE(DSI_FUNC_PRG_REG, (dev_priv->laneCount | color_format));
 870 +
 871 +       res = dev_priv->HactiveArea | (dev_priv->VactiveArea << RES_V_POS);
 872 +       REG_WRITE(DPI_RESOLUTION_REG, res);
 873 +
 874 +       REG_WRITE(VERT_SYNC_PAD_COUNT_REG, dev_priv->VsyncWidth);
 875 +       REG_WRITE(VERT_BACK_PORCH_COUNT_REG, dev_priv->VbackPorch);
 876 +       REG_WRITE(VERT_FRONT_PORCH_COUNT_REG, dev_priv->VfrontPorch);
 877 +
 878 +       REG_WRITE(HORIZ_SYNC_PAD_COUNT_REG, dev_priv->HsyncWidth);
 879 +       REG_WRITE(HORIZ_BACK_PORCH_COUNT_REG, dev_priv->HbackPorch);
 880 +       REG_WRITE(HORIZ_FRONT_PORCH_COUNT_REG, dev_priv->HfrontPorch);
 881 +       REG_WRITE(HORIZ_ACTIVE_AREA_COUNT_REG, MIPI_HACT);
 882 +
 883 +       /* Enable MIPI Port */
 884 +       REG_WRITE(MIPI, MIPI_PORT_EN);
 885  }
 886 -#endif /* AAVA_BACKLIGHT_HACK */
 887
 888
 889 -/**
 890 - * Sets the power state for the panel.
 891 - */
 892 -static void mrst_dsi_set_power(struct drm_device *dev,
 893 -                              struct psb_intel_output *output, bool on)
 894 +static void dsi_configure_down(struct drm_device *dev)
 895  {
 896         DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
 897 -       u32 pp_status;
 898
 899 -#if DBG_PRINTS
 900 -       printk("mrst_dsi_set_power\n");
 901 -#endif /* DBG_PRINTS */
 902 +       DBG_TRACE("");
 903
 904 -       /*
 905 -        * The DIS device must be ready before we can change power state.
 906 -        */
 907 -       if (!dev_priv->dsi_device_ready)
 908 -       {
 909 -#if DBG_PRINTS
 910 -               printk("mrst_dsi_set_power: !dev_priv->dsi_device_ready!\n");
 911 -#endif /* DBG_PRINTS */
 912 +       if (!dev_priv->dpi_panel_on) {
 913 +               DBG_TRACE("already off");
 914                 return;
 915         }
 916
 917 -       /*
 918 -        * We don't support dual DSI yet. May be in POR in the future.
 919 +       /* Disable backlight */
 920 +       dsi_set_backlight_state(0);
 921 +
 922 +       /* Disable pipe and plane */
 923 +       dsi_set_pipe_plane_enable_state(dev, 0);
 924 +
 925 +       /* Disable PTARGET */
 926 +       dsi_set_ptarget_state(dev, 0);
 927 +
 928 +       /* Send shutdown command, can only be sent if
 929 +        * interface is configured
 930          */
 931 -       if (dev_priv->dual_display)
 932 -       {
 933 -#if DBG_PRINTS
 934 -               printk("mrst_dsi_set_power: dev_priv->dual_display!\n");
 935 -#endif /* DBG_PRINTS */
 936 -       return;
 937 -       }
 938 +       if (dev_priv->dsi_device_ready)
 939 +               dsi_send_shutdown_packet(dev);
 940
 941 -       if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
 942 -                                      OSPM_UHB_FORCE_POWER_ON))
 943 -               return;
 944 +       /* Clear device ready state */
 945 +       dsi_set_device_ready_state(dev, 0);
 946
 947 -       if (on) {
 948 -#if DBG_PRINTS
 949 -               printk("mrst_dsi_set_power: on\n");
 950 -#endif /* DBG_PRINTS */
 951 -               if (dev_priv->dpi && !dev_priv->dpi_panel_on) {
 952 -#if DBG_PRINTS
 953 -                       printk("mrst_dsi_set_power: dpi\n");
 954 -#endif /* DBG_PRINTS */
 955 -                       REG_WRITE(DPI_CONTROL_REG, DPI_TURN_ON);
 956 -                       REG_WRITE(PP_CONTROL,
 957 -                                 (REG_READ(PP_CONTROL) | POWER_TARGET_ON));
 958 -                       do {
 959 -                               pp_status = REG_READ(PP_STATUS);
 960 -                       } while ((pp_status & (PP_ON | PP_READY)) == PP_READY);
 961 -
 962 -                       /* Run TPO display specific initialisations */
 963 -// MiKo TBD, this delay may need to be tuned
 964 -                       msleep(50);
 965 -                       panel_init(dev);
 966 -
 967 -                       /* Set backlights on */
 968 -                       backlight_state( true );
 969 -                       dev_priv->dpi_panel_on = true;
 970 -               }
 971 -       } else {
 972 -#if DBG_PRINTS
 973 -               printk("mrst_dsi_set_power: off\n");
 974 -#endif /* DBG_PRINTS */
 975 -               if (dev_priv->dpi && dev_priv->dpi_panel_on) {
 976 -#if DBG_PRINTS
 977 -                       printk("mrst_dsi_set_power: dpi\n");
 978 -#endif /* DBG_PRINTS */
 979 -                       /* Set backlights off */
 980 -                       backlight_state( false );
 981 -
 982 -// MiKo TBD, something clever could be done here to save power, for example:
 983 -// -Set display to sleep mode, or
 984 -// -Set display to HW reset, or
 985 -// -Shutdown the voltages to display
 986 -
 987 -                       REG_WRITE(PP_CONTROL,
 988 -                                 (REG_READ(PP_CONTROL) & ~POWER_TARGET_ON));
 989 -                       do {
 990 -                               pp_status = REG_READ(PP_STATUS);
 991 -                       } while (pp_status & PP_ON);
 992 -
 993 -                       REG_WRITE(DPI_CONTROL_REG, DPI_SHUT_DOWN);
 994 -
 995 -                       dev_priv->dpi_panel_on = false;
 996 -               }
 997 -       }
 998 +       /* Set panel to reset */
 999 +       dsi_set_panel_reset_state(1);
1000
1001 -       ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
1002 +       dev_priv->dpi_panel_on = false;
1003  }
1004
1005
1006 -static void mrst_dsi_dpms(struct drm_encoder *encoder, int mode)
1007 +static void dsi_configure_up(struct drm_device *dev)
1008  {
1009 -       struct drm_device *dev = encoder->dev;
1010 -       struct psb_intel_output *output = enc_to_psb_intel_output(encoder);
1011 +       DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
1012
1013 -#if DBG_PRINTS
1014 -       printk("mrst_dsi_dpms\n");
1015 -#endif /* DBG_PRINTS */
1016 +       DBG_TRACE("");
1017
1018 -       if (mode == DRM_MODE_DPMS_ON)
1019 -               mrst_dsi_set_power(dev, output, true);
1020 -       else
1021 -               mrst_dsi_set_power(dev, output, false);
1022 +       if (dev_priv->dpi_panel_on) {
1023 +               DBG_TRACE("already on");
1024 +               return;
1025 +       }
1026 +
1027 +       /* Get panel from reset */
1028 +       dsi_set_panel_reset_state(0);
1029 +
1030 +       /* Set device ready state */
1031 +       dsi_set_device_ready_state(dev, 1);
1032 +
1033 +       /* Send turn on command */
1034 +       dsi_send_turn_on_packet(dev);
1035 +
1036 +       /* Enable PTARGET */
1037 +       dsi_set_ptarget_state(dev, 1);
1038 +
1039 +       /* Initialize panel */
1040 +       dsi_init_panel(dev);
1041 +
1042 +       /* Enable plane and pipe */
1043 +       dsi_set_pipe_plane_enable_state(dev, 1);
1044 +
1045 +       /* Enable backlight */
1046 +       dsi_set_backlight_state(1);
1047 +
1048 +       dev_priv->dpi_panel_on = true;
1049  }
1050
1051
1052 -static void mrst_dsi_save(struct drm_connector *connector)
1053 +static void dsi_init_drv_ic(struct drm_device *dev)
1054  {
1055 -#if DBG_PRINTS
1056 -       printk("mrst_dsi_save\n");
1057 -#endif /* DBG_PRINTS */
1058 -       // MiKo TBD
1059 +       DBG_TRACE("");
1060  }
1061
1062
1063 -static void mrst_dsi_restore(struct drm_connector *connector)
1064 +static void dsi_schedule_work(struct drm_device *dev)
1065  {
1066 -#if DBG_PRINTS
1067 -       printk("mrst_dsi_restore\n");
1068 -#endif /* DBG_PRINTS */
1069 -       // MiKo TBD
1070 +       DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
1071 +
1072 +       DBG_TRACE("");
1073 +
1074 +       schedule_work(&dev_priv->dsi_work);
1075  }
1076
1077
1078 -static void mrst_dsi_prepare(struct drm_encoder *encoder)
1079 +static void dsi_work_handler(struct work_struct *work)
1080  {
1081 -       struct drm_device *dev = encoder->dev;
1082 -       struct psb_intel_output *output = enc_to_psb_intel_output(encoder);
1083 +       struct drm_psb_private *dev_priv = container_of(work,
1084 +                                       struct drm_psb_private, dsi_work);
1085
1086 -#if DBG_PRINTS
1087 -       printk("mrst_dsi_prepare\n");
1088 -#endif /* DBG_PRINTS */
1089 +       DBG_TRACE("");
1090
1091 -       if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
1092 -                                      OSPM_UHB_FORCE_POWER_ON))
1093 -               return;
1094 +       dsi_configure_up(dev_priv->dev);
1095 +}
1096
1097 -       mrst_dsi_set_power(dev, output, false);
1098
1099 -       ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
1100 +static void dsi_init_mipi_config(DRM_DRIVER_PRIVATE_T *dev_priv)
1101 +{
1102 +       DBG_TRACE("");
1103 +
1104 +       /* Fixed values for TPO display */
1105 +       dev_priv->pixelClock = 33264;
1106 +       dev_priv->HsyncWidth = MIPI_HSPAD;
1107 +       dev_priv->HbackPorch = MIPI_HBP;
1108 +       dev_priv->HfrontPorch = MIPI_HFP;
1109 +       dev_priv->HactiveArea = HSIZE;
1110 +       dev_priv->VsyncWidth = MIPI_VSPAD;
1111 +       dev_priv->VbackPorch = MIPI_VBP;
1112 +       dev_priv->VfrontPorch = MIPI_VFP;
1113 +       dev_priv->VactiveArea = VSIZE;
1114 +       dev_priv->bpp = 24;
1115 +
1116 +       /* video mode */
1117 +       dev_priv->dpi = true;
1118 +
1119 +       /* Set this true since firmware or kboot has enabled display */
1120 +       dev_priv->dpi_panel_on = true;
1121 +
1122 +       /* Set this false to ensure proper initial configuration */
1123 +       dev_priv->dsi_device_ready = false;
1124 +
1125 +       /* 2 lanes */
1126 +       dev_priv->laneCount = MIPI_LANES;
1127 +
1128 +       /* Burst mode */
1129 +       dev_priv->videoModeFormat = BURST_MODE;
1130 +
1131 +       dev_priv->init_drvIC = dsi_init_drv_ic;
1132 +       dev_priv->dsi_prePowerState = dsi_configure_down;
1133 +       dev_priv->dsi_postPowerState = dsi_schedule_work;
1134  }
1135
1136
1137 -static void mrst_dsi_commit(struct drm_encoder *encoder)
1138 +static struct drm_display_mode *dsi_get_fixed_display_mode(void)
1139  {
1140 -       struct drm_device *dev = encoder->dev;
1141 -       struct psb_intel_output *output = enc_to_psb_intel_output(encoder);
1142 +       struct drm_display_mode *mode;
1143 +
1144 +       DBG_TRACE("");
1145 +
1146 +       mode = kzalloc(sizeof(*mode), GFP_KERNEL);
1147 +       if (!mode) {
1148 +               DBG_ERR("kzalloc failed\n");
1149 +               return NULL;
1150 +       }
1151 +
1152 +       /* Fixed mode for TPO display
1153 +           Note: Using defined values for easier match with ITP scripts
1154 +                 and adding 1 since psb_intel_display.c decreases by 1
1155 +       */
1156 +       mode->hdisplay = (DISP_HPIX + 1);
1157 +       mode->vdisplay = (DISP_VPIX + 1);
1158 +       mode->hsync_start = (DISP_HSYNC_START + 1);
1159 +       mode->hsync_end = (DISP_HSYNC_END + 1);
1160 +       mode->htotal = (DISP_HBLANK_END + 1);
1161 +       mode->vsync_start = (DISP_VSYNC_START + 1);
1162 +       mode->vsync_end = (DISP_VSYNC_END + 1);
1163 +       mode->vtotal = (DISP_VBLANK_END + 1);
1164 +       mode->clock = 33264;
1165
1166 -#if DBG_PRINTS
1167 -       printk("mrst_dsi_commit\n");
1168 -#endif /* DBG_PRINTS */
1169 +       drm_mode_set_name(mode);
1170 +       drm_mode_set_crtcinfo(mode, 0);
1171
1172 -       mrst_dsi_set_power(dev, output, true);
1173 +       return mode;
1174  }
1175
1176
1177 -static void mrst_dsi_mode_set(struct drm_encoder *encoder,
1178 -                             struct drm_display_mode *mode,
1179 -                             struct drm_display_mode *adjusted_mode)
1180 +/* Encoder funcs */
1181 +static void dsi_encoder_mode_set(struct drm_encoder *encoder,
1182 +                                       struct drm_display_mode *mode,
1183 +                                       struct drm_display_mode *adjusted_mode)
1184  {
1185         struct drm_device *dev = encoder->dev;
1186         DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
1187 -       u32 SupportedFormat = 0;
1188 -       u32 resolution = 0;
1189 -       uint64_t curValue = DRM_MODE_SCALE_FULLSCREEN;
1190 +       uint64_t scale_mode = DRM_MODE_SCALE_FULLSCREEN;
1191
1192 -#if DBG_PRINTS
1193 -       printk("mrst_dsi_mode_set\n");
1194 -#endif /* DBG_PRINTS */
1195 +       DBG_TRACE("");
1196
1197         if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
1198 -                                      OSPM_UHB_FORCE_POWER_ON))
1199 +                                               OSPM_UHB_FORCE_POWER_ON)) {
1200 +               DBG_ERR("OSPM_DISPLAY_ISLAND OSPM_UHB_FORCE_POWER_ON failed");
1201                 return;
1202 +       }
1203
1204         /* Sleep to ensure that the graphics engine is ready
1205          * since its mode_set is called before ours
1206          */
1207         msleep(100);
1208
1209 -       switch (dev_priv->bpp)
1210 -       {
1211 -       case 24:
1212 -               SupportedFormat = RGB_888_FMT;
1213 -               break;
1214 -       default:
1215 -               printk("mrst_dsi_mode_set, invalid bpp!\n");
1216 -               break;
1217 -       }
1218 -
1219 -       if (dev_priv->dpi) {
1220 +       /* Only one mode is supported,
1221 +        * so configure only if not yet configured
1222 +        */
1223 +       if (!dev_priv->dsi_device_ready) {
1224                 drm_connector_property_get_value(
1225                                         &enc_to_psb_intel_output(encoder)->base,
1226                                         dev->mode_config.scaling_mode_property,
1227 -                                       &curValue);
1228 -               if (curValue == DRM_MODE_SCALE_CENTER) {
1229 +                                       &scale_mode);
1230 +               if (scale_mode == DRM_MODE_SCALE_CENTER)
1231                         REG_WRITE(PFIT_CONTROL, 0);
1232 -               } else if (curValue == DRM_MODE_SCALE_FULLSCREEN) {
1233 +               else if (scale_mode == DRM_MODE_SCALE_FULLSCREEN)
1234                         REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
1235 -               } else {
1236 -                       printk("mrst_dsi_mode_set, scaling not supported!\n");
1237 +               else {
1238 +                       DBG_ERR("unsupported scaling");
1239                         REG_WRITE(PFIT_CONTROL, 0);
1240                 }
1241 +               dsi_configure_mipi_block(dev);
1242 +               dev_priv->dsi_device_ready = true;
1243 +       }
1244
1245 +       ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
1246 +}
1247
1248 -               /* MIPI clock ratio 1:1 */
1249 -               //REG_WRITE(MIPI_CONTROL_REG, 0x00000018);
1250 -               //REG_WRITE(0xb080, 0x0b061a02);
1251 -
1252 -               /* MIPI clock ratio 2:1 */
1253 -               //REG_WRITE(MIPI_CONTROL_REG, 0x00000019);
1254 -               //REG_WRITE(0xb080, 0x3f1f1c04);
1255
1256 -               /* MIPI clock ratio 3:1 */
1257 -               //REG_WRITE(MIPI_CONTROL_REG, 0x0000001a);
1258 -               //REG_WRITE(0xb080, 0x091f7f08);
1259 +static void dsi_encoder_prepare(struct drm_encoder *encoder)
1260 +{
1261 +       struct drm_device *dev = encoder->dev;
1262
1263 -               /* MIPI clock ratio 4:1 */
1264 -               REG_WRITE(MIPI_CONTROL_REG, (0x00000018 | mipi_clock));
1265 -               REG_WRITE(0xb080, dphy_reg);
1266 +       DBG_TRACE("");
1267
1268 -               /* Enable all interrupts */
1269 -               REG_WRITE(INTR_EN_REG, 0xffffffff);
1270 +       if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
1271 +                                               OSPM_UHB_FORCE_POWER_ON)) {
1272 +               DBG_ERR("OSPM_DISPLAY_ISLAND OSPM_UHB_FORCE_POWER_ON failed");
1273 +               return;
1274 +       }
1275
1276 -               REG_WRITE(TURN_AROUND_TIMEOUT_REG, 0x0000000A);
1277 -               REG_WRITE(DEVICE_RESET_REG, 0x000000ff);
1278 -               REG_WRITE(INIT_COUNT_REG, 0x00000fff);
1279 -               REG_WRITE(HS_TX_TIMEOUT_REG, 0x90000);
1280 -               REG_WRITE(LP_RX_TIMEOUT_REG, 0xffff);
1281 -               REG_WRITE(HIGH_LOW_SWITCH_COUNT_REG, 0x46);
1282 -               REG_WRITE(EOT_DISABLE_REG, 0x00000000);
1283 -               REG_WRITE(LP_BYTECLK_REG, 0x00000004);
1284 +       dsi_configure_down(dev);
1285
1286 -               REG_WRITE(VIDEO_FMT_REG, dev_priv->videoModeFormat);
1287 +       ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
1288 +}
1289
1290 -               SupportedFormat <<= FMT_DPI_POS;
1291 -               REG_WRITE(DSI_FUNC_PRG_REG,
1292 -                               (dev_priv->laneCount | SupportedFormat));
1293
1294 -               resolution = dev_priv->HactiveArea |
1295 -                               (dev_priv->VactiveArea << RES_V_POS);
1296 -               REG_WRITE(DPI_RESOLUTION_REG, resolution);
1297 +static void dsi_encoder_commit(struct drm_encoder *encoder)
1298 +{
1299 +       struct drm_device *dev = encoder->dev;
1300 +       DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
1301
1302 -               REG_WRITE(VERT_SYNC_PAD_COUNT_REG, dev_priv->VsyncWidth);
1303 -               REG_WRITE(VERT_BACK_PORCH_COUNT_REG, dev_priv->VbackPorch);
1304 -               REG_WRITE(VERT_FRONT_PORCH_COUNT_REG, dev_priv->VfrontPorch);
1305 +       DBG_TRACE("");
1306
1307 -               REG_WRITE(HORIZ_SYNC_PAD_COUNT_REG, dev_priv->HsyncWidth);
1308 -               REG_WRITE(HORIZ_BACK_PORCH_COUNT_REG, dev_priv->HbackPorch);
1309 -               REG_WRITE(HORIZ_FRONT_PORCH_COUNT_REG, dev_priv->HfrontPorch);
1310 -               REG_WRITE(HORIZ_ACTIVE_AREA_COUNT_REG, MIPI_HACT);
1311 +       if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
1312 +                                               OSPM_UHB_FORCE_POWER_ON)) {
1313 +               DBG_ERR("OSPM_DISPLAY_ISLAND OSPM_UHB_FORCE_POWER_ON failed");
1314 +               return;
1315         }
1316
1317 -       /* Enable MIPI Port */
1318 -       REG_WRITE(MIPI, MIPI_PORT_EN);
1319 +       if (!work_pending(&dev_priv->dsi_work))
1320 +               dsi_configure_up(dev);
1321
1322 -       REG_WRITE(DEVICE_READY_REG, 0x00000001);
1323 -       REG_WRITE(DPI_CONTROL_REG, 0x00000002); /* Turn On */
1324 +       ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
1325 +}
1326
1327 -       dev_priv->dsi_device_ready = true;
1328
1329 -       /* Enable pipe */
1330 -       REG_WRITE(PIPEACONF, dev_priv->pipeconf);
1331 -       REG_READ(PIPEACONF);
1332 +static void dsi_encoder_dpms(struct drm_encoder *encoder, int mode)
1333 +{
1334 +       struct drm_device *dev = encoder->dev;
1335 +       DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
1336
1337 -       /* Wait for 20ms for the pipe enable to take effect. */
1338 -       udelay(20000);
1339 +       DBG_TRACE("%s", ((mode == DRM_MODE_DPMS_ON) ? "ON" : "OFF"));
1340
1341 -       /* Enable plane */
1342 -       REG_WRITE(DSPACNTR, dev_priv->dspcntr);
1343 +       if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
1344 +                                               OSPM_UHB_FORCE_POWER_ON)) {
1345 +               DBG_ERR("OSPM_DISPLAY_ISLAND OSPM_UHB_FORCE_POWER_ON failed");
1346 +               return;
1347 +       }
1348
1349 -       /* Wait for 20ms for the plane enable to take effect. */
1350 -       udelay(20000);
1351 +       if (mode == DRM_MODE_DPMS_ON) {
1352 +               if (!work_pending(&dev_priv->dsi_work))
1353 +                       dsi_configure_up(dev);
1354 +       } else
1355 +               dsi_configure_down(dev);
1356
1357         ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
1358  }
1359
1360
1361 -/**
1362 - * Detect the MIPI connection.
1363 - *
1364 - * This always returns CONNECTOR_STATUS_CONNECTED.
1365 - * This connector should only have
1366 - * been set up if the MIPI was actually connected anyway.
1367 - */
1368 -static enum drm_connector_status mrst_dsi_detect(struct drm_connector
1369 -                                                *connector)
1370 +/* Connector funcs */
1371 +static enum drm_connector_status dsi_connector_detect(struct drm_connector
1372 +                                                               *connector)
1373  {
1374 -#if DBG_PRINTS
1375 -       printk("mrst_dsi_detect\n");
1376 -#endif /* DBG_PRINTS */
1377 +       DBG_TRACE("");
1378         return connector_status_connected;
1379  }
1380
1381
1382 -/**
1383 - * Return the list of MIPI DDB modes if available.
1384 - */
1385 -static int mrst_dsi_get_modes(struct drm_connector *connector)
1386 +static int dsi_connector_get_modes(struct drm_connector *connector)
1387  {
1388         struct drm_device *dev = connector->dev;
1389 -       struct psb_intel_output *psb_intel_output = to_psb_intel_output(connector);
1390 -       struct psb_intel_mode_device *mode_dev = psb_intel_output->mode_dev;
1391 +       struct psb_intel_output *psb_output = to_psb_intel_output(connector);
1392 +       struct psb_intel_mode_device *mode_dev = psb_output->mode_dev;
1393 +       struct drm_display_mode *mode;
1394 +
1395 +       DBG_TRACE("");
1396
1397         /* Didn't get an DDB, so
1398          * Set wide sync ranges so we get all modes
1399 @@ -775,8 +701,7 @@ static int mrst_dsi_get_modes(struct drm_connector *connector)
1400         connector->display_info.max_hfreq = 200;
1401
1402         if (mode_dev->panel_fixed_mode != NULL) {
1403 -               struct drm_display_mode *mode =
1404 -                       drm_mode_duplicate(dev, mode_dev->panel_fixed_mode);
1405 +               mode = drm_mode_duplicate(dev, mode_dev->panel_fixed_mode);
1406                 drm_mode_probed_add(connector, mode);
1407                 return 1;
1408         }
1409 @@ -784,180 +709,116 @@ static int mrst_dsi_get_modes(struct drm_connector *connector)
1410  }
1411
1412
1413 -static const struct drm_encoder_helper_funcs mrst_dsi_helper_funcs = {
1414 -       .dpms           = mrst_dsi_dpms,
1415 +static void dsi_connector_save(struct drm_connector *connector)
1416 +{
1417 +       DBG_TRACE("");
1418 +}
1419 +
1420 +
1421 +static void dsi_connector_restore(struct drm_connector *connector)
1422 +{
1423 +       DBG_TRACE("");
1424 +}
1425 +
1426 +
1427 +static const struct drm_encoder_helper_funcs encoder_helper_funcs = {
1428 +       .dpms           = dsi_encoder_dpms,
1429         .mode_fixup     = psb_intel_lvds_mode_fixup,
1430 -       .prepare        = mrst_dsi_prepare,
1431 -       .mode_set       = mrst_dsi_mode_set,
1432 -       .commit = mrst_dsi_commit,
1433 +       .prepare        = dsi_encoder_prepare,
1434 +       .mode_set       = dsi_encoder_mode_set,
1435 +       .commit         = dsi_encoder_commit,
1436  };
1437
1438 -
1439 -static const struct drm_connector_helper_funcs
1440 -       mrst_dsi_connector_helper_funcs = {
1441 -               .get_modes      = mrst_dsi_get_modes,
1442 -               .mode_valid     = psb_intel_lvds_mode_valid,
1443 -               .best_encoder   = psb_intel_best_encoder,
1444 +static const struct drm_connector_helper_funcs connector_helper_funcs = {
1445 +       .get_modes      = dsi_connector_get_modes,
1446 +       .mode_valid     = psb_intel_lvds_mode_valid,
1447 +       .best_encoder   = psb_intel_best_encoder,
1448  };
1449
1450
1451 -static const struct drm_connector_funcs mrst_dsi_connector_funcs = {
1452 +static const struct drm_connector_funcs connector_funcs = {
1453         .dpms           = drm_helper_connector_dpms,
1454 -       .save           = mrst_dsi_save,
1455 -       .restore        = mrst_dsi_restore,
1456 -       .detect         = mrst_dsi_detect,
1457 +       .save           = dsi_connector_save,
1458 +       .restore        = dsi_connector_restore,
1459 +       .detect         = dsi_connector_detect,
1460         .fill_modes     = drm_helper_probe_single_connector_modes,
1461         .set_property   = psb_intel_lvds_set_property,
1462         .destroy        = psb_intel_lvds_destroy,
1463  };
1464
1465
1466 -/** Returns the panel fixed mode from configuration. */
1467 -struct drm_display_mode *mrst_dsi_get_configuration_mode(struct drm_device *dev)
1468 -{
1469 -       struct drm_display_mode *mode;
1470 -
1471 -       mode = kzalloc(sizeof(*mode), GFP_KERNEL);
1472 -       if (!mode)
1473 -               return NULL;
1474 -
1475 -       /* MiKo, fixed mode for TPO display
1476 -           Note: Using defined values for easier match with ITP scripts
1477 -                 and adding 1 since psb_intel_display.c decreases by 1
1478 -       */
1479 -       mode->hdisplay = (DISP_HPIX + 1);
1480 -       mode->vdisplay = (DISP_VPIX + 1);
1481 -       mode->hsync_start = (DISP_HSYNC_START + 1);
1482 -       mode->hsync_end = (DISP_HSYNC_END + 1);
1483 -       mode->htotal = (DISP_HBLANK_END + 1);
1484 -       mode->vsync_start = (DISP_VSYNC_START + 1);
1485 -       mode->vsync_end = (DISP_VSYNC_END + 1);
1486 -       mode->vtotal = (DISP_VBLANK_END + 1);
1487 -       mode->clock = 33264;
1488 -
1489 -       drm_mode_set_name(mode);
1490 -       drm_mode_set_crtcinfo(mode, 0);
1491 -
1492 -       return mode;
1493 -}
1494 -
1495 -
1496 -/* ************************************************************************* *\
1497 -FUNCTION: mrst_mipi_settings_init
1498 -                                                                                                                               `
1499 -DESCRIPTION:
1500 -
1501 -\* ************************************************************************* */
1502 -static bool mrst_mipi_settings_init(DRM_DRIVER_PRIVATE_T *dev_priv)
1503 -{
1504 -       /* MiKo, fixed values for TPO display */
1505 -       dev_priv->pixelClock = 33264;
1506 -       dev_priv->HsyncWidth = MIPI_HSPAD;
1507 -       dev_priv->HbackPorch = MIPI_HBP;
1508 -       dev_priv->HfrontPorch = MIPI_HFP;
1509 -       dev_priv->HactiveArea = HSIZE;
1510 -       dev_priv->VsyncWidth = MIPI_VSPAD;
1511 -       dev_priv->VbackPorch = MIPI_VBP;
1512 -       dev_priv->VfrontPorch = MIPI_VFP;
1513 -       dev_priv->VactiveArea = VSIZE;
1514 -       dev_priv->bpp = 24;
1515 -
1516 -       /* video mode */
1517 -       dev_priv->dpi = true;
1518 -
1519 -       /* MiKo, set these true by default to ensure that first mode set is done
1520 -                cleanly
1521 -       */
1522 -       dev_priv->dpi_panel_on = true;
1523 -       dev_priv->dsi_device_ready = true;
1524 -
1525 -       /* 2 lanes */
1526 -       dev_priv->laneCount = MIPI_LANES;
1527 -
1528 -       /* Burst mode */
1529 -       dev_priv->videoModeFormat = BURST_MODE;
1530 -
1531 -       return true;
1532 -}
1533 -
1534 -
1535 -/**
1536 - * mrst_dsi_init - setup MIPI connectors on this device
1537 - * @dev: drm device
1538 - *
1539 - * Create the connector, try to figure out what
1540 - * modes we can display on the MIPI panel (if present).
1541 - */
1542  void mrst_dsi_init(struct drm_device *dev,
1543 -                   struct psb_intel_mode_device *mode_dev)
1544 +                                       struct psb_intel_mode_device *mode_dev)
1545  {
1546         DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
1547 -       struct psb_intel_output *psb_intel_output;
1548 +       struct psb_intel_output *psb_output;
1549         struct drm_connector *connector;
1550         struct drm_encoder *encoder;
1551
1552 -#if DBG_PRINTS
1553 -       printk("mrst_dsi_init\n");
1554 -#endif /* DBG_PRINTS */
1555 +       DBG_TRACE("");
1556
1557 -       psb_intel_output = kzalloc(sizeof(struct psb_intel_output), GFP_KERNEL);
1558 -       if (!psb_intel_output)
1559 +       psb_output = kzalloc(sizeof(struct psb_intel_output), GFP_KERNEL);
1560 +       if (!psb_output) {
1561 +               DBG_ERR("kzalloc failed\n");
1562                 return;
1563 -
1564 -       panel_reset();
1565 +       }
1566
1567  #ifdef AAVA_BACKLIGHT_HACK
1568         schedule_delayed_work(&bl_work, 2*HZ);
1569  #endif /* AAVA_BACKLIGHT_HACK */
1570
1571 -       psb_intel_output->mode_dev = mode_dev;
1572 -       connector = &psb_intel_output->base;
1573 -       encoder = &psb_intel_output->enc;
1574 -       drm_connector_init(dev,
1575 -                          &psb_intel_output->base,
1576 -                          &mrst_dsi_connector_funcs,
1577 -                          DRM_MODE_CONNECTOR_MIPI);
1578 -
1579 -       drm_encoder_init(dev,
1580 -                        &psb_intel_output->enc,
1581 -                        &psb_intel_lvds_enc_funcs,
1582 -                        DRM_MODE_ENCODER_MIPI);
1583 -
1584 -       drm_mode_connector_attach_encoder(&psb_intel_output->base,
1585 -                                         &psb_intel_output->enc);
1586 -       psb_intel_output->type = INTEL_OUTPUT_MIPI;
1587 -
1588 -       drm_encoder_helper_add(encoder, &mrst_dsi_helper_funcs);
1589 -       drm_connector_helper_add(connector, &mrst_dsi_connector_helper_funcs);
1590 +       psb_output->mode_dev = mode_dev;
1591 +       connector = &psb_output->base;
1592 +       encoder = &psb_output->enc;
1593 +       drm_connector_init(dev, &psb_output->base, &connector_funcs,
1594 +                                               DRM_MODE_CONNECTOR_MIPI);
1595 +
1596 +       drm_encoder_init(dev, &psb_output->enc, &psb_intel_lvds_enc_funcs,
1597 +                                                       DRM_MODE_ENCODER_MIPI);
1598 +
1599 +       drm_mode_connector_attach_encoder(&psb_output->base, &psb_output->enc);
1600 +       psb_output->type = INTEL_OUTPUT_MIPI;
1601 +
1602 +       drm_encoder_helper_add(encoder, &encoder_helper_funcs);
1603 +       drm_connector_helper_add(connector, &connector_helper_funcs);
1604         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1605         connector->interlace_allowed = false;
1606         connector->doublescan_allowed = false;
1607
1608         drm_connector_attach_property(connector,
1609 -                                     dev->mode_config.scaling_mode_property,
1610 -                                     DRM_MODE_SCALE_FULLSCREEN);
1611 -       drm_connector_attach_property(connector,
1612 -                                     dev_priv->backlight_property,
1613 -                                     BRIGHTNESS_MAX_LEVEL);
1614 +                                       dev->mode_config.scaling_mode_property,
1615 +                                               DRM_MODE_SCALE_FULLSCREEN);
1616 +       drm_connector_attach_property(connector, dev_priv->backlight_property,
1617 +                                                       BRIGHTNESS_MAX_LEVEL);
1618
1619 -       if (!mrst_mipi_settings_init(dev_priv))
1620 -               printk("Can't initialize MIPI settings\n");
1621 +       mode_dev->panel_wants_dither = false;
1622 +
1623 +       dsi_init_mipi_config(dev_priv);
1624
1625         /* No config phase */
1626         dev_priv->config_phase = false;
1627
1628         /* Get the fixed mode */
1629 -       mode_dev->panel_fixed_mode = mrst_dsi_get_configuration_mode(dev);
1630 -       if (mode_dev->panel_fixed_mode) {
1631 +       mode_dev->panel_fixed_mode = dsi_get_fixed_display_mode();
1632 +       if (mode_dev->panel_fixed_mode)
1633                 mode_dev->panel_fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
1634 -       } else {
1635 -               printk("Found no modes for MIPI!\n");
1636 +       else {
1637 +               DBG_ERR("Fixed mode not available!\n");
1638                 goto failed_find;
1639         }
1640 +
1641 +       /* Set this true since we enable/disable plane and pipe */
1642 +       dev_priv->dsi_plane_pipe_control = true;
1643 +
1644 +       drm_sysfs_connector_add(connector);
1645 +
1646 +       /* Initialize work queue */
1647 +       INIT_WORK(&dev_priv->dsi_work, dsi_work_handler);
1648 +
1649  // Temporary access from sysfs begin
1650 -       orig_encoder = encoder;
1651 +       test_dev = dev;
1652  // Temporary access from sysfs end
1653 -       drm_sysfs_connector_add(connector);
1654 +
1655         return;
1656
1657  failed_find:
1658 @@ -966,31 +827,140 @@ failed_find:
1659         kfree(connector);
1660  }
1661
1662 +
1663  // Temporary access from sysfs begin
1664 -static struct class_attribute miko_class_attrs[] = {
1665 -       __ATTR(dphy, 0644, NULL, dphy_store),
1666 -       __ATTR(clock, 0644, NULL, clock_store),
1667 -       __ATTR(apply, 0200, NULL, apply_settings),
1668 +static ssize_t dsi_run_test(struct class *class, const char *buf, size_t len)
1669 +{
1670 +       struct drm_device *dev = test_dev;
1671 +       ssize_t status;
1672 +       long test_id;
1673 +       int i;
1674 +
1675 +       status = strict_strtoul(buf, 0, &test_id);
1676 +
1677 +       DBG_TRACE("test_id %li", test_id);
1678 +
1679 +       switch(test_id) {
1680 +       case 1:
1681 +               /* BL on */
1682 +               dsi_set_backlight_state(1);
1683 +               break;
1684 +       case 2:
1685 +               /* BL off */
1686 +               dsi_set_backlight_state(0);
1687 +               break;
1688 +       case 3:
1689 +               /* Reset off */
1690 +               dsi_set_panel_reset_state(0);
1691 +               break;
1692 +       case 4:
1693 +               /* Reset on */
1694 +               dsi_set_panel_reset_state(1);
1695 +               break;
1696 +       case 5:
1697 +               /* Set device ready state */
1698 +               dsi_set_device_ready_state(dev, 1);
1699 +               break;
1700 +       case 6:
1701 +               /* Clear device ready state */
1702 +               dsi_set_device_ready_state(dev, 0);
1703 +               break;
1704 +       case 7:
1705 +               /* Send turn on command */
1706 +               dsi_send_turn_on_packet(dev);
1707 +               break;
1708 +       case 8:
1709 +               /* Send shutdown command */
1710 +               dsi_send_shutdown_packet(dev);
1711 +               break;
1712 +       case 9:
1713 +               /* Enable PTARGET */
1714 +               dsi_set_ptarget_state(dev, 1);
1715 +               break;
1716 +       case 10:
1717 +               /* Disable PTARGET */
1718 +               dsi_set_ptarget_state(dev, 0);
1719 +               break;
1720 +       case 11:
1721 +               /* Initialize panel */
1722 +               dsi_init_panel(dev);
1723 +               break;
1724 +       case 12:
1725 +               /* Enable plane and pipe */
1726 +               dsi_set_pipe_plane_enable_state(dev, 1);
1727 +               break;
1728 +       case 13:
1729 +               /* Disable plane and pipe */
1730 +               dsi_set_pipe_plane_enable_state(dev, 0);
1731 +               break;
1732 +       case 14:
1733 +               /* configure up */
1734 +               dsi_configure_up(dev);
1735 +               break;
1736 +       case 15:
1737 +               /* configure down */
1738 +               dsi_configure_down(dev);
1739 +               break;
1740 +       case 16:
1741 +               /* Draw pixels */
1742 +               for (i = 0 ; i < (864*40) ; i++) {
1743 +                       if (dsi_wait_hs_data_fifo(dev) < 0)
1744 +                               break;
1745 +                       if (i == 0)
1746 +                               REG_WRITE(0xb068, 0x0f0f0f2c);
1747 +                       else
1748 +                               REG_WRITE(0xb068, 0x0f0f0f3c);
1749 +                       if (dsi_wait_hs_ctrl_fifo(dev) < 0)
1750 +                               break;
1751 +                       REG_WRITE(0xb070, 0x00000429);
1752 +               }
1753 +       case 17:
1754 +               /* Sleep out command */
1755 +               if (dsi_wait_hs_data_fifo(dev) < 0)
1756 +                       break;
1757 +               REG_WRITE(0xb068, 0x00000011);
1758 +               if (dsi_wait_hs_ctrl_fifo(dev) < 0)
1759 +                       break;
1760 +               REG_WRITE(0xb070, 0x00000129);
1761 +               break;
1762 +       case 18:
1763 +               /* Display on command */
1764 +               if (dsi_wait_hs_data_fifo(dev) < 0)
1765 +                       break;
1766 +               REG_WRITE(0xb068, 0x00000029);
1767 +               if (dsi_wait_hs_ctrl_fifo(dev) < 0)
1768 +                       break;
1769 +               REG_WRITE(0xb070, 0x00000129);
1770 +               break;
1771 +       default:
1772 +               break;
1773 +       }
1774 +       return len;
1775 +}
1776 +
1777 +
1778 +
1779 +static struct class_attribute tpo_class_attrs[] = {
1780 +       __ATTR(test, 0200, NULL, dsi_run_test),
1781         __ATTR_NULL,
1782  };
1783
1784 -static struct class miko_class = {
1785 -       .name =         "miko",
1786 +static struct class tpo_class = {
1787 +       .name =         "tpo",
1788         .owner =        THIS_MODULE,
1789
1790 -       .class_attrs =  miko_class_attrs,
1791 +       .class_attrs =  tpo_class_attrs,
1792  };
1793
1794 -static int __init miko_sysfs_init(void)
1795 +static int __init tpo_sysfs_init(void)
1796  {
1797 -       int             status;
1798 +       int status;
1799
1800 -       status = class_register(&miko_class);
1801 +       status = class_register(&tpo_class);
1802         if (status < 0)
1803                 return status;
1804
1805         return status;
1806  }
1807 -postcore_initcall(miko_sysfs_init);
1808 +postcore_initcall(tpo_sysfs_init);
1809  // Temporary access from sysfs end
1810 -
1811 diff --git a/drivers/gpu/drm/mrst/pvr/services4/3rdparty/linux_framebuffer_mrst/mrstlfb_displayclass.c b/drivers/gpu/drm/mrst/pvr/services4/3rdparty/linux_framebuffer_mrst/mrstlfb_displayclass.c
1812 index adca7e2..7831183 100644
1813 --- a/drivers/gpu/drm/mrst/pvr/services4/3rdparty/linux_framebuffer_mrst/mrstlfb_displayclass.c
1814 +++ b/drivers/gpu/drm/mrst/pvr/services4/3rdparty/linux_framebuffer_mrst/mrstlfb_displayclass.c
1815 @@ -1977,6 +1977,9 @@ PVRSRV_ERROR MRSTLFBPrePowerState(IMG_HANDLE               hDevHandle,
1816             (eNewPowerState == PVRSRV_DEV_POWER_STATE_ON))
1817                 return PVRSRV_OK;
1818
1819 +       if (!dev_priv->iLVDS_enable && dev_priv->dsi_prePowerState != NULL)
1820 +               dev_priv->dsi_prePowerState(dev);
1821 +
1822         save_display_registers(dev);
1823
1824         if (dev_priv->iLVDS_enable) {
1825 @@ -1999,14 +2002,15 @@ PVRSRV_ERROR MRSTLFBPrePowerState(IMG_HANDLE             hDevHandle,
1826                 /*turn off PLLs*/
1827                 PSB_WVDC32(0, MRST_DPLL_A);
1828         } else {
1829 -               PSB_WVDC32(DPI_SHUT_DOWN, DPI_CONTROL_REG);
1830 -               PSB_WVDC32(0x0, PIPEACONF);
1831 -               PSB_WVDC32(0x2faf0000, BLC_PWM_CTL);
1832 -               while (REG_READ(0x70008) & 0x40000000);
1833 -               while ((PSB_RVDC32(GEN_FIFO_STAT_REG) & DPI_FIFO_EMPTY)
1834 +               if (dev_priv->dsi_prePowerState == NULL) {
1835 +                       PSB_WVDC32(DPI_SHUT_DOWN, DPI_CONTROL_REG);
1836 +                       PSB_WVDC32(0x0, PIPEACONF);
1837 +                       PSB_WVDC32(0x2faf0000, BLC_PWM_CTL);
1838 +                       while (REG_READ(0x70008) & 0x40000000);
1839 +                       while ((PSB_RVDC32(GEN_FIFO_STAT_REG) & DPI_FIFO_EMPTY)
1840                                                         != DPI_FIFO_EMPTY);
1841 -               PSB_WVDC32(0, DEVICE_READY_REG);
1842 -
1843 +                       PSB_WVDC32(0, DEVICE_READY_REG);
1844 +               }
1845                 /* turn off mipi panel power */
1846                 ret = lnw_ipc_single_cmd(IPC_MSG_PANEL_ON_OFF, IPC_CMD_PANEL_OFF, 0, 0);
1847                 if (ret)
1848 @@ -2052,5 +2056,8 @@ PVRSRV_ERROR MRSTLFBPostPowerState(IMG_HANDLE               hDevHandle,
1849
1850         restore_display_registers(dev);
1851
1852 +       if (!dev_priv->iLVDS_enable && dev_priv->dsi_postPowerState != NULL)
1853 +               dev_priv->dsi_postPowerState(dev);
1854 +
1855         return PVRSRV_OK;
1856  }
1857 --
1858 1.6.2.5
1859