code.ossystems Code Review - openembedded-core.git/blob

   1 commit 930469634910fa87c21f0a7423c98b270d35d8c6
   2 Author: Eric Anholt <eric@anholt.net>
   3 Date:   Mon Sep 15 13:13:34 2008 -0700
   4
   5     drm: G33-class hardware has a newer 965-style MCH (no DCC register).
   6
   7     Fixes bad software fallback rendering in Mesa in dual-channel configurations.
   8
   9     d9a2470012588dc5313a5ac8bb2f03575af00e99
  10
  11 diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
  12 index 0c1b3a0..6b3f1e4 100644
  13 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c
  14 +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
  15 @@ -96,7 +96,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
  16                  */
  17                 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
  18                 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
  19 -       } else if (!IS_I965G(dev) || IS_I965GM(dev)) {
  20 +       } else if ((!IS_I965G(dev) && !IS_G33(dev)) || IS_I965GM(dev)) {
  21                 uint32_t dcc;
  22
  23                 /* On 915-945 and GM965, channel interleave by the CPU is