1 commit 573e91575687018b4307f53a50f4da0084dbdf3d
2 Author: Jesse Barnes <jbarnes@virtuousgeek.org>
3 Date: Tue Jul 29 11:54:06 2008 -0700
5 i915: Use more consistent names for regs, and store them in a separate file.
7 Signed-off-by: Eric Anholt <eric@anholt.net>
8 Signed-off-by: Dave Airlie <airlied@redhat.com>
10 diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
11 index 01a869b..7be580b 100644
12 --- a/drivers/gpu/drm/i915/i915_dma.c
13 +++ b/drivers/gpu/drm/i915/i915_dma.c
14 @@ -40,11 +40,11 @@ int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
16 drm_i915_private_t *dev_priv = dev->dev_private;
17 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
18 - u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
19 + u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
22 for (i = 0; i < 10000; i++) {
23 - ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
24 + ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
25 ring->space = ring->head - (ring->tail + 8);
27 ring->space += ring->Size;
28 @@ -67,8 +67,8 @@ void i915_kernel_lost_context(struct drm_device * dev)
29 drm_i915_private_t *dev_priv = dev->dev_private;
30 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
32 - ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
33 - ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
34 + ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
35 + ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
36 ring->space = ring->head - (ring->tail + 8);
38 ring->space += ring->Size;
39 @@ -98,13 +98,13 @@ static int i915_dma_cleanup(struct drm_device * dev)
40 drm_pci_free(dev, dev_priv->status_page_dmah);
41 dev_priv->status_page_dmah = NULL;
42 /* Need to rewrite hardware status page */
43 - I915_WRITE(0x02080, 0x1ffff000);
44 + I915_WRITE(HWS_PGA, 0x1ffff000);
47 if (dev_priv->status_gfx_addr) {
48 dev_priv->status_gfx_addr = 0;
49 drm_core_ioremapfree(&dev_priv->hws_map, dev);
50 - I915_WRITE(0x2080, 0x1ffff000);
51 + I915_WRITE(HWS_PGA, 0x1ffff000);
55 @@ -170,7 +170,7 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
56 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
58 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
59 - I915_WRITE(0x02080, dev_priv->dma_status_page);
60 + I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
62 DRM_DEBUG("Enabled hardware status page\n");
64 @@ -201,9 +201,9 @@ static int i915_dma_resume(struct drm_device * dev)
65 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
67 if (dev_priv->status_gfx_addr != 0)
68 - I915_WRITE(0x02080, dev_priv->status_gfx_addr);
69 + I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
71 - I915_WRITE(0x02080, dev_priv->dma_status_page);
72 + I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
73 DRM_DEBUG("Enabled hardware status page\n");
76 @@ -402,8 +402,8 @@ static void i915_emit_breadcrumb(struct drm_device *dev)
77 dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1;
80 - OUT_RING(CMD_STORE_DWORD_IDX);
82 + OUT_RING(MI_STORE_DWORD_INDEX);
83 + OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
84 OUT_RING(dev_priv->counter);
87 @@ -505,7 +505,7 @@ static int i915_dispatch_flip(struct drm_device * dev)
88 i915_kernel_lost_context(dev);
91 - OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
92 + OUT_RING(MI_FLUSH | MI_READ_FLUSH);
96 @@ -530,8 +530,8 @@ static int i915_dispatch_flip(struct drm_device * dev)
97 dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
100 - OUT_RING(CMD_STORE_DWORD_IDX);
102 + OUT_RING(MI_STORE_DWORD_INDEX);
103 + OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
104 OUT_RING(dev_priv->counter);
107 @@ -728,8 +728,8 @@ static int i915_set_status_page(struct drm_device *dev, void *data,
108 dev_priv->hw_status_page = dev_priv->hws_map.handle;
110 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
111 - I915_WRITE(0x02080, dev_priv->status_gfx_addr);
112 - DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n",
113 + I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
114 + DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
115 dev_priv->status_gfx_addr);
116 DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
118 diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
119 index 93aed1c..6c99aab 100644
120 --- a/drivers/gpu/drm/i915/i915_drv.c
121 +++ b/drivers/gpu/drm/i915/i915_drv.c
122 @@ -279,13 +279,13 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
123 dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
124 dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
125 dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
126 - dev_priv->saveDSPABASE = I915_READ(DSPABASE);
127 + dev_priv->saveDSPAADDR = I915_READ(DSPAADDR);
129 dev_priv->saveDSPASURF = I915_READ(DSPASURF);
130 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
132 i915_save_palette(dev, PIPE_A);
133 - dev_priv->savePIPEASTAT = I915_READ(I915REG_PIPEASTAT);
134 + dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT);
136 /* Pipe & plane B info */
137 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
138 @@ -307,13 +307,13 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
139 dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
140 dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
141 dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
142 - dev_priv->saveDSPBBASE = I915_READ(DSPBBASE);
143 + dev_priv->saveDSPBADDR = I915_READ(DSPBADDR);
144 if (IS_I965GM(dev) || IS_IGD_GM(dev)) {
145 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
146 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
148 i915_save_palette(dev, PIPE_B);
149 - dev_priv->savePIPEBSTAT = I915_READ(I915REG_PIPEBSTAT);
150 + dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);
153 dev_priv->saveADPA = I915_READ(ADPA);
154 @@ -328,9 +328,9 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
155 dev_priv->saveLVDS = I915_READ(LVDS);
156 if (!IS_I830(dev) && !IS_845G(dev))
157 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
158 - dev_priv->saveLVDSPP_ON = I915_READ(LVDSPP_ON);
159 - dev_priv->saveLVDSPP_OFF = I915_READ(LVDSPP_OFF);
160 - dev_priv->savePP_CYCLE = I915_READ(PP_CYCLE);
161 + dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
162 + dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
163 + dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
165 /* FIXME: save TV & SDVO state */
167 @@ -341,19 +341,19 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
168 dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
170 /* Interrupt state */
171 - dev_priv->saveIIR = I915_READ(I915REG_INT_IDENTITY_R);
172 - dev_priv->saveIER = I915_READ(I915REG_INT_ENABLE_R);
173 - dev_priv->saveIMR = I915_READ(I915REG_INT_MASK_R);
174 + dev_priv->saveIIR = I915_READ(IIR);
175 + dev_priv->saveIER = I915_READ(IER);
176 + dev_priv->saveIMR = I915_READ(IMR);
179 - dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0);
180 - dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1);
181 - dev_priv->saveVCLK_POST_DIV = I915_READ(VCLK_POST_DIV);
182 + dev_priv->saveVGA0 = I915_READ(VGA0);
183 + dev_priv->saveVGA1 = I915_READ(VGA1);
184 + dev_priv->saveVGA_PD = I915_READ(VGA_PD);
185 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
187 /* Clock gating state */
188 dev_priv->saveD_STATE = I915_READ(D_STATE);
189 - dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D);
190 + dev_priv->saveCG_2D_DIS = I915_READ(CG_2D_DIS);
192 /* Cache mode state */
193 dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
194 @@ -363,7 +363,7 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
197 for (i = 0; i < 16; i++) {
198 - dev_priv->saveSWF0[i] = I915_READ(SWF0 + (i << 2));
199 + dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));
200 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
202 for (i = 0; i < 3; i++)
203 @@ -424,7 +424,7 @@ static int i915_resume(struct drm_device *dev)
204 I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
205 I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
206 I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
207 - I915_WRITE(DSPABASE, dev_priv->saveDSPABASE);
208 + I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR);
209 I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
211 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
212 @@ -436,7 +436,7 @@ static int i915_resume(struct drm_device *dev)
213 i915_restore_palette(dev, PIPE_A);
214 /* Enable the plane */
215 I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
216 - I915_WRITE(DSPABASE, I915_READ(DSPABASE));
217 + I915_WRITE(DSPAADDR, I915_READ(DSPAADDR));
219 /* Pipe & plane B info */
220 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
221 @@ -466,7 +466,7 @@ static int i915_resume(struct drm_device *dev)
222 I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
223 I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
224 I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
225 - I915_WRITE(DSPBBASE, dev_priv->saveDSPBBASE);
226 + I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR);
227 I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
229 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
230 @@ -478,7 +478,7 @@ static int i915_resume(struct drm_device *dev)
231 i915_restore_palette(dev, PIPE_B);
232 /* Enable the plane */
233 I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
234 - I915_WRITE(DSPBBASE, I915_READ(DSPBBASE));
235 + I915_WRITE(DSPBADDR, I915_READ(DSPBADDR));
238 I915_WRITE(ADPA, dev_priv->saveADPA);
239 @@ -493,9 +493,9 @@ static int i915_resume(struct drm_device *dev)
241 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
242 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
243 - I915_WRITE(LVDSPP_ON, dev_priv->saveLVDSPP_ON);
244 - I915_WRITE(LVDSPP_OFF, dev_priv->saveLVDSPP_OFF);
245 - I915_WRITE(PP_CYCLE, dev_priv->savePP_CYCLE);
246 + I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
247 + I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
248 + I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
249 I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
251 /* FIXME: restore TV & SDVO state */
252 @@ -508,14 +508,14 @@ static int i915_resume(struct drm_device *dev)
255 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
256 - I915_WRITE(VCLK_DIVISOR_VGA0, dev_priv->saveVCLK_DIVISOR_VGA0);
257 - I915_WRITE(VCLK_DIVISOR_VGA1, dev_priv->saveVCLK_DIVISOR_VGA1);
258 - I915_WRITE(VCLK_POST_DIV, dev_priv->saveVCLK_POST_DIV);
259 + I915_WRITE(VGA0, dev_priv->saveVGA0);
260 + I915_WRITE(VGA1, dev_priv->saveVGA1);
261 + I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
264 /* Clock gating state */
265 I915_WRITE (D_STATE, dev_priv->saveD_STATE);
266 - I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
267 + I915_WRITE(CG_2D_DIS, dev_priv->saveCG_2D_DIS);
269 /* Cache mode state */
270 I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
271 @@ -524,7 +524,7 @@ static int i915_resume(struct drm_device *dev)
272 I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
274 for (i = 0; i < 16; i++) {
275 - I915_WRITE(SWF0 + (i << 2), dev_priv->saveSWF0[i]);
276 + I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);
277 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]);
279 for (i = 0; i < 3; i++)
280 diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
281 index 2d441d3..afb51a3 100644
282 --- a/drivers/gpu/drm/i915/i915_drv.h
283 +++ b/drivers/gpu/drm/i915/i915_drv.h
288 +#include "i915_reg.h"
290 /* General customization:
293 @@ -138,7 +140,7 @@ typedef struct drm_i915_private {
301 u32 savePFIT_PGM_RATIOS;
302 @@ -159,24 +161,24 @@ typedef struct drm_i915_private {
310 - u32 saveVCLK_DIVISOR_VGA0;
311 - u32 saveVCLK_DIVISOR_VGA1;
312 - u32 saveVCLK_POST_DIV;
320 - u32 saveLVDSPP_OFF;
321 + u32 savePP_ON_DELAYS;
322 + u32 savePP_OFF_DELAYS;
330 + u32 savePP_DIVISOR;
331 u32 savePFIT_CONTROL;
332 u32 save_palette_a[256];
333 u32 save_palette_b[256];
334 @@ -189,7 +191,7 @@ typedef struct drm_i915_private {
336 u32 saveCACHE_MODE_0;
338 - u32 saveDSPCLK_GATE_D;
340 u32 saveMI_ARB_STATE;
343 @@ -283,816 +285,26 @@ extern void i915_mem_release(struct drm_device * dev,
344 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
345 dev_priv->ring.tail = outring; \
346 dev_priv->ring.space -= outcount * 4; \
347 - I915_WRITE(LP_RING + RING_TAIL, outring); \
348 + I915_WRITE(PRB0_TAIL, outring); \
351 -extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
353 -/* Extended config space */
358 -#define VGA_ST01_MDA 0x3ba
359 -#define VGA_ST01_CGA 0x3da
361 -#define VGA_MSR_WRITE 0x3c2
362 -#define VGA_MSR_READ 0x3cc
363 -#define VGA_MSR_MEM_EN (1<<1)
364 -#define VGA_MSR_CGA_MODE (1<<0)
366 -#define VGA_SR_INDEX 0x3c4
367 -#define VGA_SR_DATA 0x3c5
369 -#define VGA_AR_INDEX 0x3c0
370 -#define VGA_AR_VID_EN (1<<5)
371 -#define VGA_AR_DATA_WRITE 0x3c0
372 -#define VGA_AR_DATA_READ 0x3c1
374 -#define VGA_GR_INDEX 0x3ce
375 -#define VGA_GR_DATA 0x3cf
377 -#define VGA_GR_MEM_READ_MODE_SHIFT 3
378 -#define VGA_GR_MEM_READ_MODE_PLANE 1
380 -#define VGA_GR_MEM_MODE_MASK 0xc
381 -#define VGA_GR_MEM_MODE_SHIFT 2
382 -#define VGA_GR_MEM_A0000_AFFFF 0
383 -#define VGA_GR_MEM_A0000_BFFFF 1
384 -#define VGA_GR_MEM_B0000_B7FFF 2
385 -#define VGA_GR_MEM_B0000_BFFFF 3
387 -#define VGA_DACMASK 0x3c6
388 -#define VGA_DACRX 0x3c7
389 -#define VGA_DACWX 0x3c8
390 -#define VGA_DACDATA 0x3c9
392 -#define VGA_CR_INDEX_MDA 0x3b4
393 -#define VGA_CR_DATA_MDA 0x3b5
394 -#define VGA_CR_INDEX_CGA 0x3d4
395 -#define VGA_CR_DATA_CGA 0x3d5
397 -#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
398 -#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
399 -#define CMD_REPORT_HEAD (7<<23)
400 -#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
401 -#define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)
403 -#define INST_PARSER_CLIENT 0x00000000
404 -#define INST_OP_FLUSH 0x02000000
405 -#define INST_FLUSH_MAP_CACHE 0x00000001
407 -#define BB1_START_ADDR_MASK (~0x7)
408 -#define BB1_PROTECTED (1<<0)
409 -#define BB1_UNPROTECTED (0<<0)
410 -#define BB2_END_ADDR_MASK (~0x7)
412 -/* Framebuffer compression */
413 -#define FBC_CFB_BASE 0x03200 /* 4k page aligned */
414 -#define FBC_LL_BASE 0x03204 /* 4k page aligned */
415 -#define FBC_CONTROL 0x03208
416 -#define FBC_CTL_EN (1<<31)
417 -#define FBC_CTL_PERIODIC (1<<30)
418 -#define FBC_CTL_INTERVAL_SHIFT (16)
419 -#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
420 -#define FBC_CTL_STRIDE_SHIFT (5)
421 -#define FBC_CTL_FENCENO (1<<0)
422 -#define FBC_COMMAND 0x0320c
423 -#define FBC_CMD_COMPRESS (1<<0)
424 -#define FBC_STATUS 0x03210
425 -#define FBC_STAT_COMPRESSING (1<<31)
426 -#define FBC_STAT_COMPRESSED (1<<30)
427 -#define FBC_STAT_MODIFIED (1<<29)
428 -#define FBC_STAT_CURRENT_LINE (1<<0)
429 -#define FBC_CONTROL2 0x03214
430 -#define FBC_CTL_FENCE_DBL (0<<4)
431 -#define FBC_CTL_IDLE_IMM (0<<2)
432 -#define FBC_CTL_IDLE_FULL (1<<2)
433 -#define FBC_CTL_IDLE_LINE (2<<2)
434 -#define FBC_CTL_IDLE_DEBUG (3<<2)
435 -#define FBC_CTL_CPU_FENCE (1<<1)
436 -#define FBC_CTL_PLANEA (0<<0)
437 -#define FBC_CTL_PLANEB (1<<0)
438 -#define FBC_FENCE_OFF 0x0321b
440 -#define FBC_LL_SIZE (1536)
441 -#define FBC_LL_PAD (32)
445 -#define USER_INT_FLAG (1<<1)
446 -#define VSYNC_PIPEB_FLAG (1<<5)
447 -#define VSYNC_PIPEA_FLAG (1<<7)
448 -#define HWB_OOM_FLAG (1<<13) /* binner out of memory */
450 -#define I915REG_HWSTAM 0x02098
451 -#define I915REG_INT_IDENTITY_R 0x020a4
452 -#define I915REG_INT_MASK_R 0x020a8
453 -#define I915REG_INT_ENABLE_R 0x020a0
455 -#define I915REG_PIPEASTAT 0x70024
456 -#define I915REG_PIPEBSTAT 0x71024
458 -#define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
459 -#define I915_VBLANK_CLEAR (1UL<<1)
461 -#define SRX_INDEX 0x3c4
462 -#define SRX_DATA 0x3c5
464 -#define SR01_SCREEN_OFF (1<<5)
466 -#define PPCR 0x61204
467 -#define PPCR_ON (1<<0)
469 -#define DVOB 0x61140
470 -#define DVOB_ON (1<<31)
471 -#define DVOC 0x61160
472 -#define DVOC_ON (1<<31)
473 -#define LVDS 0x61180
474 -#define LVDS_ON (1<<31)
476 -#define ADPA 0x61100
477 -#define ADPA_DPMS_MASK (~(3<<10))
478 -#define ADPA_DPMS_ON (0<<10)
479 -#define ADPA_DPMS_SUSPEND (1<<10)
480 -#define ADPA_DPMS_STANDBY (2<<10)
481 -#define ADPA_DPMS_OFF (3<<10)
483 -#define NOPID 0x2094
484 -#define LP_RING 0x2030
485 -#define HP_RING 0x2040
486 -/* The binner has its own ring buffer:
488 -#define HWB_RING 0x2400
490 -#define RING_TAIL 0x00
491 -#define TAIL_ADDR 0x001FFFF8
492 -#define RING_HEAD 0x04
493 -#define HEAD_WRAP_COUNT 0xFFE00000
494 -#define HEAD_WRAP_ONE 0x00200000
495 -#define HEAD_ADDR 0x001FFFFC
496 -#define RING_START 0x08
497 -#define START_ADDR 0x0xFFFFF000
498 -#define RING_LEN 0x0C
499 -#define RING_NR_PAGES 0x001FF000
500 -#define RING_REPORT_MASK 0x00000006
501 -#define RING_REPORT_64K 0x00000002
502 -#define RING_REPORT_128K 0x00000004
503 -#define RING_NO_REPORT 0x00000000
504 -#define RING_VALID_MASK 0x00000001
505 -#define RING_VALID 0x00000001
506 -#define RING_INVALID 0x00000000
508 -/* Instruction parser error reg:
510 -#define IPEIR 0x2088
512 -/* Scratch pad debug 0 reg:
514 -#define SCPD0 0x209c
516 -/* Error status reg:
520 -/* Secondary DMA fetch address debug reg:
522 -#define DMA_FADD_S 0x20d4
524 -/* Memory Interface Arbitration State
526 -#define MI_ARB_STATE 0x20e4
528 -/* Cache mode 0 reg.
529 - * - Manipulating render cache behaviour is central
530 - * to the concept of zone rendering, tuning this reg can help avoid
531 - * unnecessary render cache reads and even writes (for z/stencil)
532 - * at beginning and end of scene.
534 - * - To change a bit, write to this reg with a mask bit set and the
535 - * bit of interest either set or cleared. EG: (BIT<<16) | BIT to set.
537 -#define Cache_Mode_0 0x2120
538 -#define CACHE_MODE_0 0x2120
539 -#define CM0_MASK_SHIFT 16
540 -#define CM0_IZ_OPT_DISABLE (1<<6)
541 -#define CM0_ZR_OPT_DISABLE (1<<5)
542 -#define CM0_DEPTH_EVICT_DISABLE (1<<4)
543 -#define CM0_COLOR_EVICT_DISABLE (1<<3)
544 -#define CM0_DEPTH_WRITE_DISABLE (1<<1)
545 -#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
548 -/* Graphics flush control. A CPU write flushes the GWB of all writes.
549 - * The data is discarded.
551 -#define GFX_FLSH_CNTL 0x2170
553 -/* Binner control. Defines the location of the bin pointer list:
555 -#define BINCTL 0x2420
556 -#define BC_MASK (1 << 9)
558 -/* Binned scene info.
560 -#define BINSCENE 0x2428
561 -#define BS_OP_LOAD (1 << 8)
562 -#define BS_MASK (1 << 22)
564 -/* Bin command parser debug reg:
568 -/* Bin memory control debug reg:
572 -/* Bin data cache debug reg:
576 -/* Binner pointer cache debug reg:
580 -/* Binner scratch pad debug reg:
582 -#define BINSKPD 0x24f0
584 -/* HWB scratch pad debug reg:
586 -#define HWBSKPD 0x24f4
588 -/* Binner memory pool reg:
590 -#define BMP_BUFFER 0x2430
591 -#define BMP_PAGE_SIZE_4K (0 << 10)
592 -#define BMP_BUFFER_SIZE_SHIFT 1
593 -#define BMP_ENABLE (1 << 0)
595 -/* Get/put memory from the binner memory pool:
597 -#define BMP_GET 0x2438
598 -#define BMP_PUT 0x2440
599 -#define BMP_OFFSET_SHIFT 5
601 -/* 3D state packets:
603 -#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
605 -#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
606 -#define SC_UPDATE_SCISSOR (0x1<<1)
607 -#define SC_ENABLE_MASK (0x1<<0)
608 -#define SC_ENABLE (0x1<<0)
610 -#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
612 -#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
613 -#define SCI_YMIN_MASK (0xffff<<16)
614 -#define SCI_XMIN_MASK (0xffff<<0)
615 -#define SCI_YMAX_MASK (0xffff<<16)
616 -#define SCI_XMAX_MASK (0xffff<<0)
618 -#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
619 -#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
620 -#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
621 -#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
622 -#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
623 -#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
624 -#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
626 -#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
628 -#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
629 -#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
630 -#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
631 -#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
632 -#define XY_SRC_COPY_BLT_SRC_TILED (1<<15)
633 -#define XY_SRC_COPY_BLT_DST_TILED (1<<11)
635 -#define MI_BATCH_BUFFER ((0x30<<23)|1)
636 -#define MI_BATCH_BUFFER_START (0x31<<23)
637 -#define MI_BATCH_BUFFER_END (0xA<<23)
638 -#define MI_BATCH_NON_SECURE (1)
639 -#define MI_BATCH_NON_SECURE_I965 (1<<8)
641 -#define MI_WAIT_FOR_EVENT ((0x3<<23))
642 -#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
643 -#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
644 -#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
646 -#define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))
648 -#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
649 -#define ASYNC_FLIP (1<<22)
650 -#define DISPLAY_PLANE_A (0<<20)
651 -#define DISPLAY_PLANE_B (1<<20)
654 -#define DSPACNTR 0x70180
655 -#define DSPBCNTR 0x71180
656 -#define DISPPLANE_SEL_PIPE_MASK (1<<24)
658 -/* Define the region of interest for the binner:
660 -#define CMD_OP_BIN_CONTROL ((0x3<<29)|(0x1d<<24)|(0x84<<16)|4)
662 -#define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
664 -#define CMD_MI_FLUSH (0x04 << 23)
665 -#define MI_NO_WRITE_FLUSH (1 << 2)
666 -#define MI_READ_FLUSH (1 << 0)
667 -#define MI_EXE_FLUSH (1 << 1)
668 -#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
669 -#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
671 -#define BREADCRUMB_BITS 31
672 -#define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1)
674 -#define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[5])
675 -#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
677 -#define BLC_PWM_CTL 0x61254
678 -#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
680 -#define BLC_PWM_CTL2 0x61250
682 - * This is the most significant 15 bits of the number of backlight cycles in a
683 - * complete cycle of the modulated backlight control.
684 + * Reads a dword out of the status page, which is written to from the command
685 + * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
686 + * MI_STORE_DATA_IMM.
688 - * The actual value is this field multiplied by two.
690 -#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
691 -#define BLM_LEGACY_MODE (1 << 16)
693 - * This is the number of cycles out of the backlight modulation cycle for which
694 - * the backlight is on.
695 + * The following dwords have a reserved meaning:
696 + * 0: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
697 + * 4: ring 0 head pointer
698 + * 5: ring 1 head pointer (915-class)
699 + * 6: ring 2 head pointer (915-class)
701 - * This field must be no greater than the number of cycles in the complete
702 - * backlight modulation cycle.
704 -#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
705 -#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
707 -#define I915_GCFGC 0xf0
708 -#define I915_LOW_FREQUENCY_ENABLE (1 << 7)
709 -#define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
710 -#define I915_DISPLAY_CLOCK_333_MHZ (4 << 4)
711 -#define I915_DISPLAY_CLOCK_MASK (7 << 4)
713 -#define I855_HPLLCC 0xc0
714 -#define I855_CLOCK_CONTROL_MASK (3 << 0)
715 -#define I855_CLOCK_133_200 (0 << 0)
716 -#define I855_CLOCK_100_200 (1 << 0)
717 -#define I855_CLOCK_100_133 (2 << 0)
718 -#define I855_CLOCK_166_250 (3 << 0)
721 + * The area from dword 0x10 to 0x3ff is available for driver usage.
723 -#define VCLK2_VCO_M 0x6008 /* treat as 16 bit? (includes msbs) */
724 -#define VCLK2_VCO_N 0x600a
725 -#define VCLK2_VCO_DIV_SEL 0x6012
727 -#define VCLK_DIVISOR_VGA0 0x6000
728 -#define VCLK_DIVISOR_VGA1 0x6004
729 -#define VCLK_POST_DIV 0x6010
730 -/** Selects a post divisor of 4 instead of 2. */
731 -# define VGA1_PD_P2_DIV_4 (1 << 15)
732 -/** Overrides the p2 post divisor field */
733 -# define VGA1_PD_P1_DIV_2 (1 << 13)
734 -# define VGA1_PD_P1_SHIFT 8
735 -/** P1 value is 2 greater than this field */
736 -# define VGA1_PD_P1_MASK (0x1f << 8)
737 -/** Selects a post divisor of 4 instead of 2. */
738 -# define VGA0_PD_P2_DIV_4 (1 << 7)
739 -/** Overrides the p2 post divisor field */
740 -# define VGA0_PD_P1_DIV_2 (1 << 5)
741 -# define VGA0_PD_P1_SHIFT 0
742 -/** P1 value is 2 greater than this field */
743 -# define VGA0_PD_P1_MASK (0x1f << 0)
745 -/* PCI D state control register */
746 -#define D_STATE 0x6104
747 -#define DSPCLK_GATE_D 0x6200
749 -/* I830 CRTC registers */
750 -#define HTOTAL_A 0x60000
751 -#define HBLANK_A 0x60004
752 -#define HSYNC_A 0x60008
753 -#define VTOTAL_A 0x6000c
754 -#define VBLANK_A 0x60010
755 -#define VSYNC_A 0x60014
756 -#define PIPEASRC 0x6001c
757 -#define BCLRPAT_A 0x60020
758 -#define VSYNCSHIFT_A 0x60028
760 -#define HTOTAL_B 0x61000
761 -#define HBLANK_B 0x61004
762 -#define HSYNC_B 0x61008
763 -#define VTOTAL_B 0x6100c
764 -#define VBLANK_B 0x61010
765 -#define VSYNC_B 0x61014
766 -#define PIPEBSRC 0x6101c
767 -#define BCLRPAT_B 0x61020
768 -#define VSYNCSHIFT_B 0x61028
770 -#define PP_STATUS 0x61200
771 -# define PP_ON (1 << 31)
773 - * Indicates that all dependencies of the panel are on:
777 - * - LVDS/DVOB/DVOC on
779 -# define PP_READY (1 << 30)
780 -# define PP_SEQUENCE_NONE (0 << 28)
781 -# define PP_SEQUENCE_ON (1 << 28)
782 -# define PP_SEQUENCE_OFF (2 << 28)
783 -# define PP_SEQUENCE_MASK 0x30000000
784 -#define PP_CONTROL 0x61204
785 -# define POWER_TARGET_ON (1 << 0)
787 -#define LVDSPP_ON 0x61208
788 -#define LVDSPP_OFF 0x6120c
789 -#define PP_CYCLE 0x61210
791 -#define PFIT_CONTROL 0x61230
792 -# define PFIT_ENABLE (1 << 31)
793 -# define PFIT_PIPE_MASK (3 << 29)
794 -# define PFIT_PIPE_SHIFT 29
795 -# define VERT_INTERP_DISABLE (0 << 10)
796 -# define VERT_INTERP_BILINEAR (1 << 10)
797 -# define VERT_INTERP_MASK (3 << 10)
798 -# define VERT_AUTO_SCALE (1 << 9)
799 -# define HORIZ_INTERP_DISABLE (0 << 6)
800 -# define HORIZ_INTERP_BILINEAR (1 << 6)
801 -# define HORIZ_INTERP_MASK (3 << 6)
802 -# define HORIZ_AUTO_SCALE (1 << 5)
803 -# define PANEL_8TO6_DITHER_ENABLE (1 << 3)
805 -#define PFIT_PGM_RATIOS 0x61234
806 -# define PFIT_VERT_SCALE_MASK 0xfff00000
807 -# define PFIT_HORIZ_SCALE_MASK 0x0000fff0
809 -#define PFIT_AUTO_RATIOS 0x61238
812 -#define DPLL_A 0x06014
813 -#define DPLL_B 0x06018
814 -# define DPLL_VCO_ENABLE (1 << 31)
815 -# define DPLL_DVO_HIGH_SPEED (1 << 30)
816 -# define DPLL_SYNCLOCK_ENABLE (1 << 29)
817 -# define DPLL_VGA_MODE_DIS (1 << 28)
818 -# define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
819 -# define DPLLB_MODE_LVDS (2 << 26) /* i915 */
820 -# define DPLL_MODE_MASK (3 << 26)
821 -# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
822 -# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
823 -# define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
824 -# define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
825 -# define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
826 -# define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
828 - * The i830 generation, in DAC/serial mode, defines p1 as two plus this
829 - * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set.
831 -# define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
833 - * The i830 generation, in LVDS mode, defines P1 as the bit number set within
834 - * this field (only one bit may be set).
836 -# define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
837 -# define DPLL_FPA01_P1_POST_DIV_SHIFT 16
838 -# define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */
839 -# define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
840 -# define PLL_REF_INPUT_DREFCLK (0 << 13)
841 -# define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
842 -# define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
843 -# define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
844 -# define PLL_REF_INPUT_MASK (3 << 13)
845 -# define PLL_LOAD_PULSE_PHASE_SHIFT 9
847 - * Parallel to Serial Load Pulse phase selection.
848 - * Selects the phase for the 10X DPLL clock for the PCIe
849 - * digital display port. The range is 4 to 13; 10 or more
850 - * is just a flip delay. The default is 6
852 -# define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
853 -# define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
856 - * SDVO multiplier for 945G/GM. Not used on 965.
858 - * \sa DPLL_MD_UDI_MULTIPLIER_MASK
860 -# define SDVO_MULTIPLIER_MASK 0x000000ff
861 -# define SDVO_MULTIPLIER_SHIFT_HIRES 4
862 -# define SDVO_MULTIPLIER_SHIFT_VGA 0
864 -/** @defgroup DPLL_MD
867 -/** Pipe A SDVO/UDI clock multiplier/divider register for G965. */
868 -#define DPLL_A_MD 0x0601c
869 -/** Pipe B SDVO/UDI clock multiplier/divider register for G965. */
870 -#define DPLL_B_MD 0x06020
872 - * UDI pixel divider, controlling how many pixels are stuffed into a packet.
874 - * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
876 -# define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
877 -# define DPLL_MD_UDI_DIVIDER_SHIFT 24
878 -/** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
879 -# define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
880 -# define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
882 - * SDVO/UDI pixel multiplier.
884 - * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
885 - * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
886 - * modes, the bus rate would be below the limits, so SDVO allows for stuffing
887 - * dummy bytes in the datastream at an increased clock rate, with both sides of
888 - * the link knowing how many bytes are fill.
890 - * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
891 - * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
892 - * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
893 - * through an SDVO command.
895 - * This register field has values of multiplication factor minus 1, with
896 - * a maximum multiplier of 5 for SDVO.
898 -# define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
899 -# define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
900 -/** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
901 - * This best be set to the default value (3) or the CRT won't work. No,
902 - * I don't entirely understand what this does...
904 -# define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
905 -# define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
908 -#define DPLL_TEST 0x606c
909 -# define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
910 -# define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
911 -# define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
912 -# define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
913 -# define DPLLB_TEST_N_BYPASS (1 << 19)
914 -# define DPLLB_TEST_M_BYPASS (1 << 18)
915 -# define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
916 -# define DPLLA_TEST_N_BYPASS (1 << 3)
917 -# define DPLLA_TEST_M_BYPASS (1 << 2)
918 -# define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
920 -#define ADPA 0x61100
921 -#define ADPA_DAC_ENABLE (1<<31)
922 -#define ADPA_DAC_DISABLE 0
923 -#define ADPA_PIPE_SELECT_MASK (1<<30)
924 -#define ADPA_PIPE_A_SELECT 0
925 -#define ADPA_PIPE_B_SELECT (1<<30)
926 -#define ADPA_USE_VGA_HVPOLARITY (1<<15)
927 -#define ADPA_SETS_HVPOLARITY 0
928 -#define ADPA_VSYNC_CNTL_DISABLE (1<<11)
929 -#define ADPA_VSYNC_CNTL_ENABLE 0
930 -#define ADPA_HSYNC_CNTL_DISABLE (1<<10)
931 -#define ADPA_HSYNC_CNTL_ENABLE 0
932 -#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
933 -#define ADPA_VSYNC_ACTIVE_LOW 0
934 -#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
935 -#define ADPA_HSYNC_ACTIVE_LOW 0
937 -#define FPA0 0x06040
938 -#define FPA1 0x06044
939 -#define FPB0 0x06048
940 -#define FPB1 0x0604c
941 -# define FP_N_DIV_MASK 0x003f0000
942 -# define FP_N_DIV_SHIFT 16
943 -# define FP_M1_DIV_MASK 0x00003f00
944 -# define FP_M1_DIV_SHIFT 8
945 -# define FP_M2_DIV_MASK 0x0000003f
946 -# define FP_M2_DIV_SHIFT 0
949 -#define PORT_HOTPLUG_EN 0x61110
950 -# define SDVOB_HOTPLUG_INT_EN (1 << 26)
951 -# define SDVOC_HOTPLUG_INT_EN (1 << 25)
952 -# define TV_HOTPLUG_INT_EN (1 << 18)
953 -# define CRT_HOTPLUG_INT_EN (1 << 9)
954 -# define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
956 -#define PORT_HOTPLUG_STAT 0x61114
957 -# define CRT_HOTPLUG_INT_STATUS (1 << 11)
958 -# define TV_HOTPLUG_INT_STATUS (1 << 10)
959 -# define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
960 -# define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
961 -# define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
962 -# define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
963 -# define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
964 -# define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
966 -#define SDVOB 0x61140
967 -#define SDVOC 0x61160
968 -#define SDVO_ENABLE (1 << 31)
969 -#define SDVO_PIPE_B_SELECT (1 << 30)
970 -#define SDVO_STALL_SELECT (1 << 29)
971 -#define SDVO_INTERRUPT_ENABLE (1 << 26)
973 - * 915G/GM SDVO pixel multiplier.
975 - * Programmed value is multiplier - 1, up to 5x.
977 - * \sa DPLL_MD_UDI_MULTIPLIER_MASK
979 -#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
980 -#define SDVO_PORT_MULTIPLY_SHIFT 23
981 -#define SDVO_PHASE_SELECT_MASK (15 << 19)
982 -#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
983 -#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
984 -#define SDVOC_GANG_MODE (1 << 16)
985 -#define SDVO_BORDER_ENABLE (1 << 7)
986 -#define SDVOB_PCIE_CONCURRENCY (1 << 3)
987 -#define SDVO_DETECTED (1 << 2)
988 -/* Bits to be preserved when writing */
989 -#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14))
990 -#define SDVOC_PRESERVE_MASK (1 << 17)
996 - * This register controls the LVDS output enable, pipe selection, and data
997 - * format selection.
999 - * All of the clock/data pairs are force powered down by power sequencing.
1001 -#define LVDS 0x61180
1003 - * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
1004 - * the DPLL semantics change when the LVDS is assigned to that pipe.
1006 -# define LVDS_PORT_EN (1 << 31)
1007 -/** Selects pipe B for LVDS data. Must be set on pre-965. */
1008 -# define LVDS_PIPEB_SELECT (1 << 30)
1011 - * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
1014 -# define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
1015 -# define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
1016 -# define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
1018 - * Controls the A3 data pair, which contains the additional LSBs for 24 bit
1019 - * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
1022 -# define LVDS_A3_POWER_MASK (3 << 6)
1023 -# define LVDS_A3_POWER_DOWN (0 << 6)
1024 -# define LVDS_A3_POWER_UP (3 << 6)
1026 - * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
1029 -# define LVDS_CLKB_POWER_MASK (3 << 4)
1030 -# define LVDS_CLKB_POWER_DOWN (0 << 4)
1031 -# define LVDS_CLKB_POWER_UP (3 << 4)
1034 - * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
1035 - * setting for whether we are in dual-channel mode. The B3 pair will
1036 - * additionally only be powered up when LVDS_A3_POWER_UP is set.
1038 -# define LVDS_B0B3_POWER_MASK (3 << 2)
1039 -# define LVDS_B0B3_POWER_DOWN (0 << 2)
1040 -# define LVDS_B0B3_POWER_UP (3 << 2)
1042 -#define PIPEACONF 0x70008
1043 -#define PIPEACONF_ENABLE (1<<31)
1044 -#define PIPEACONF_DISABLE 0
1045 -#define PIPEACONF_DOUBLE_WIDE (1<<30)
1046 -#define I965_PIPECONF_ACTIVE (1<<30)
1047 -#define PIPEACONF_SINGLE_WIDE 0
1048 -#define PIPEACONF_PIPE_UNLOCKED 0
1049 -#define PIPEACONF_PIPE_LOCKED (1<<25)
1050 -#define PIPEACONF_PALETTE 0
1051 -#define PIPEACONF_GAMMA (1<<24)
1052 -#define PIPECONF_FORCE_BORDER (1<<25)
1053 -#define PIPECONF_PROGRESSIVE (0 << 21)
1054 -#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
1055 -#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
1057 -#define DSPARB 0x70030
1058 -#define DSPARB_CSTART_MASK (0x7f << 7)
1059 -#define DSPARB_CSTART_SHIFT 7
1060 -#define DSPARB_BSTART_MASK (0x7f)
1061 -#define DSPARB_BSTART_SHIFT 0
1063 -#define PIPEBCONF 0x71008
1064 -#define PIPEBCONF_ENABLE (1<<31)
1065 -#define PIPEBCONF_DISABLE 0
1066 -#define PIPEBCONF_DOUBLE_WIDE (1<<30)
1067 -#define PIPEBCONF_DISABLE 0
1068 -#define PIPEBCONF_GAMMA (1<<24)
1069 -#define PIPEBCONF_PALETTE 0
1071 -#define PIPEBGCMAXRED 0x71010
1072 -#define PIPEBGCMAXGREEN 0x71014
1073 -#define PIPEBGCMAXBLUE 0x71018
1074 -#define PIPEBSTAT 0x71024
1075 -#define PIPEBFRAMEHIGH 0x71040
1076 -#define PIPEBFRAMEPIXEL 0x71044
1078 -#define DSPACNTR 0x70180
1079 -#define DSPBCNTR 0x71180
1080 -#define DISPLAY_PLANE_ENABLE (1<<31)
1081 -#define DISPLAY_PLANE_DISABLE 0
1082 -#define DISPPLANE_GAMMA_ENABLE (1<<30)
1083 -#define DISPPLANE_GAMMA_DISABLE 0
1084 -#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
1085 -#define DISPPLANE_8BPP (0x2<<26)
1086 -#define DISPPLANE_15_16BPP (0x4<<26)
1087 -#define DISPPLANE_16BPP (0x5<<26)
1088 -#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
1089 -#define DISPPLANE_32BPP (0x7<<26)
1090 -#define DISPPLANE_STEREO_ENABLE (1<<25)
1091 -#define DISPPLANE_STEREO_DISABLE 0
1092 -#define DISPPLANE_SEL_PIPE_MASK (1<<24)
1093 -#define DISPPLANE_SEL_PIPE_A 0
1094 -#define DISPPLANE_SEL_PIPE_B (1<<24)
1095 -#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
1096 -#define DISPPLANE_SRC_KEY_DISABLE 0
1097 -#define DISPPLANE_LINE_DOUBLE (1<<20)
1098 -#define DISPPLANE_NO_LINE_DOUBLE 0
1099 -#define DISPPLANE_STEREO_POLARITY_FIRST 0
1100 -#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
1102 -#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
1103 -#define DISPPLANE_ALPHA_TRANS_DISABLE 0
1104 -#define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0
1105 -#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
1107 -#define DSPABASE 0x70184
1108 -#define DSPASTRIDE 0x70188
1110 -#define DSPBBASE 0x71184
1111 -#define DSPBADDR DSPBBASE
1112 -#define DSPBSTRIDE 0x71188
1114 -#define DSPAKEYVAL 0x70194
1115 -#define DSPAKEYMASK 0x70198
1117 -#define DSPAPOS 0x7018C /* reserved */
1118 -#define DSPASIZE 0x70190
1119 -#define DSPBPOS 0x7118C
1120 -#define DSPBSIZE 0x71190
1122 -#define DSPASURF 0x7019C
1123 -#define DSPATILEOFF 0x701A4
1125 -#define DSPBSURF 0x7119C
1126 -#define DSPBTILEOFF 0x711A4
1128 -#define VGACNTRL 0x71400
1129 -# define VGA_DISP_DISABLE (1 << 31)
1130 -# define VGA_2X_MODE (1 << 30)
1131 -# define VGA_PIPE_B_SELECT (1 << 29)
1134 - * Some BIOS scratch area registers. The 845 (and 830?) store the amount
1135 - * of video memory available to the BIOS in SWF1.
1138 -#define SWF0 0x71410
1141 - * 855 scratch registers.
1143 -#define SWF10 0x70410
1145 -#define SWF30 0x72414
1148 - * Overlay registers. These are overlay registers accessed via MMIO.
1149 - * Those loaded via the overlay register page are defined in i830_video.c.
1151 -#define OVADD 0x30000
1153 -#define DOVSTA 0x30008
1154 -#define OC_BUF (0x3<<20)
1155 +#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
1156 +#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, 5)
1158 -#define OGAMC5 0x30010
1159 -#define OGAMC4 0x30014
1160 -#define OGAMC3 0x30018
1161 -#define OGAMC2 0x3001c
1162 -#define OGAMC1 0x30020
1163 -#define OGAMC0 0x30024
1165 - * Palette registers
1167 -#define PALETTE_A 0x0a000
1168 -#define PALETTE_B 0x0a800
1169 +extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
1171 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1172 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1173 diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
1174 index df03611..4a2de78 100644
1175 --- a/drivers/gpu/drm/i915/i915_irq.c
1176 +++ b/drivers/gpu/drm/i915/i915_irq.c
1178 #include "i915_drm.h"
1179 #include "i915_drv.h"
1181 -#define USER_INT_FLAG (1<<1)
1182 -#define VSYNC_PIPEB_FLAG (1<<5)
1183 -#define VSYNC_PIPEA_FLAG (1<<7)
1185 #define MAX_NOPID ((u32)~0)
1188 @@ -236,40 +232,43 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1190 u32 pipea_stats, pipeb_stats;
1192 - pipea_stats = I915_READ(I915REG_PIPEASTAT);
1193 - pipeb_stats = I915_READ(I915REG_PIPEBSTAT);
1194 + pipea_stats = I915_READ(PIPEASTAT);
1195 + pipeb_stats = I915_READ(PIPEBSTAT);
1197 - temp = I915_READ16(I915REG_INT_IDENTITY_R);
1198 + temp = I915_READ16(IIR);
1200 - temp &= (USER_INT_FLAG | VSYNC_PIPEA_FLAG | VSYNC_PIPEB_FLAG);
1201 + temp &= (I915_USER_INTERRUPT |
1202 + I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1203 + I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT);
1205 DRM_DEBUG("%s flag=%08x\n", __FUNCTION__, temp);
1210 - I915_WRITE16(I915REG_INT_IDENTITY_R, temp);
1211 - (void) I915_READ16(I915REG_INT_IDENTITY_R);
1212 + I915_WRITE16(IIR, temp);
1213 + (void) I915_READ16(IIR);
1214 DRM_READMEMORYBARRIER();
1216 dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1218 - if (temp & USER_INT_FLAG)
1219 + if (temp & I915_USER_INTERRUPT)
1220 DRM_WAKEUP(&dev_priv->irq_queue);
1222 - if (temp & (VSYNC_PIPEA_FLAG | VSYNC_PIPEB_FLAG)) {
1223 + if (temp & (I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1224 + I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT)) {
1225 int vblank_pipe = dev_priv->vblank_pipe;
1228 (DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B))
1229 == (DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B)) {
1230 - if (temp & VSYNC_PIPEA_FLAG)
1231 + if (temp & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT)
1232 atomic_inc(&dev->vbl_received);
1233 - if (temp & VSYNC_PIPEB_FLAG)
1234 + if (temp & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT)
1235 atomic_inc(&dev->vbl_received2);
1236 - } else if (((temp & VSYNC_PIPEA_FLAG) &&
1237 + } else if (((temp & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) &&
1238 (vblank_pipe & DRM_I915_VBLANK_PIPE_A)) ||
1239 - ((temp & VSYNC_PIPEB_FLAG) &&
1240 + ((temp & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) &&
1241 (vblank_pipe & DRM_I915_VBLANK_PIPE_B)))
1242 atomic_inc(&dev->vbl_received);
1244 @@ -278,12 +277,12 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1246 if (dev_priv->swaps_pending > 0)
1247 drm_locked_tasklet(dev, i915_vblank_tasklet);
1248 - I915_WRITE(I915REG_PIPEASTAT,
1249 + I915_WRITE(PIPEASTAT,
1250 pipea_stats|I915_VBLANK_INTERRUPT_ENABLE|
1251 - I915_VBLANK_CLEAR);
1252 - I915_WRITE(I915REG_PIPEBSTAT,
1253 + PIPE_VBLANK_INTERRUPT_STATUS);
1254 + I915_WRITE(PIPEBSTAT,
1255 pipeb_stats|I915_VBLANK_INTERRUPT_ENABLE|
1256 - I915_VBLANK_CLEAR);
1257 + PIPE_VBLANK_INTERRUPT_STATUS);
1261 @@ -304,12 +303,12 @@ static int i915_emit_irq(struct drm_device * dev)
1262 dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1;
1265 - OUT_RING(CMD_STORE_DWORD_IDX);
1267 + OUT_RING(MI_STORE_DWORD_INDEX);
1268 + OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
1269 OUT_RING(dev_priv->counter);
1272 - OUT_RING(GFX_OP_USER_INTERRUPT);
1273 + OUT_RING(MI_USER_INTERRUPT);
1276 return dev_priv->counter;
1277 @@ -421,11 +420,11 @@ static void i915_enable_interrupt (struct drm_device *dev)
1280 if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A)
1281 - flag |= VSYNC_PIPEA_FLAG;
1282 + flag |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1283 if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B)
1284 - flag |= VSYNC_PIPEB_FLAG;
1285 + flag |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1287 - I915_WRITE16(I915REG_INT_ENABLE_R, USER_INT_FLAG | flag);
1288 + I915_WRITE16(IER, I915_USER_INTERRUPT | flag);
1291 /* Set the vblank monitor pipe
1292 @@ -465,11 +464,11 @@ int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1296 - flag = I915_READ(I915REG_INT_ENABLE_R);
1297 + flag = I915_READ(IER);
1299 - if (flag & VSYNC_PIPEA_FLAG)
1300 + if (flag & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT)
1301 pipe->pipe |= DRM_I915_VBLANK_PIPE_A;
1302 - if (flag & VSYNC_PIPEB_FLAG)
1303 + if (flag & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT)
1304 pipe->pipe |= DRM_I915_VBLANK_PIPE_B;
1307 @@ -587,9 +586,9 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
1309 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1311 - I915_WRITE16(I915REG_HWSTAM, 0xfffe);
1312 - I915_WRITE16(I915REG_INT_MASK_R, 0x0);
1313 - I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);
1314 + I915_WRITE16(HWSTAM, 0xfffe);
1315 + I915_WRITE16(IMR, 0x0);
1316 + I915_WRITE16(IER, 0x0);
1319 void i915_driver_irq_postinstall(struct drm_device * dev)
1320 @@ -614,10 +613,10 @@ void i915_driver_irq_uninstall(struct drm_device * dev)
1324 - I915_WRITE16(I915REG_HWSTAM, 0xffff);
1325 - I915_WRITE16(I915REG_INT_MASK_R, 0xffff);
1326 - I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);
1327 + I915_WRITE16(HWSTAM, 0xffff);
1328 + I915_WRITE16(IMR, 0xffff);
1329 + I915_WRITE16(IER, 0x0);
1331 - temp = I915_READ16(I915REG_INT_IDENTITY_R);
1332 - I915_WRITE16(I915REG_INT_IDENTITY_R, temp);
1333 + temp = I915_READ16(IIR);
1334 + I915_WRITE16(IIR, temp);
1336 diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
1337 new file mode 100644
1338 index 0000000..477c64e
1340 +++ b/drivers/gpu/drm/i915/i915_reg.h
1342 +/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
1343 + * All Rights Reserved.
1345 + * Permission is hereby granted, free of charge, to any person obtaining a
1346 + * copy of this software and associated documentation files (the
1347 + * "Software"), to deal in the Software without restriction, including
1348 + * without limitation the rights to use, copy, modify, merge, publish,
1349 + * distribute, sub license, and/or sell copies of the Software, and to
1350 + * permit persons to whom the Software is furnished to do so, subject to
1351 + * the following conditions:
1353 + * The above copyright notice and this permission notice (including the
1354 + * next paragraph) shall be included in all copies or substantial portions
1355 + * of the Software.
1357 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
1358 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
1359 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
1360 + * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
1361 + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
1362 + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
1363 + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
1366 +#ifndef _I915_REG_H_
1367 +#define _I915_REG_H_
1369 +/* MCH MMIO space */
1370 +/** 915-945 and GM965 MCH register controlling DRAM channel access */
1372 +#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
1373 +#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
1374 +#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
1375 +#define DCC_ADDRESSING_MODE_MASK (3 << 0)
1376 +#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
1378 +/** 965 MCH register controlling DRAM channel configuration */
1379 +#define CHDECMISC 0x111
1380 +#define CHDECMISC_FLEXMEMORY (1 << 1)
1383 + * The Bridge device's PCI config space has information about the
1384 + * fb aperture size and the amount of pre-reserved memory.
1386 +#define INTEL_GMCH_CTRL 0x52
1387 +#define INTEL_GMCH_ENABLED 0x4
1388 +#define INTEL_GMCH_MEM_MASK 0x1
1389 +#define INTEL_GMCH_MEM_64M 0x1
1390 +#define INTEL_GMCH_MEM_128M 0
1392 +#define INTEL_855_GMCH_GMS_MASK (0x7 << 4)
1393 +#define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4)
1394 +#define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4)
1395 +#define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4)
1396 +#define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4)
1397 +#define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4)
1398 +#define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4)
1400 +#define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4)
1401 +#define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4)
1403 +/* PCI config space */
1405 +#define HPLLCC 0xc0 /* 855 only */
1406 +#define GC_CLOCK_CONTROL_MASK (3 << 0)
1407 +#define GC_CLOCK_133_200 (0 << 0)
1408 +#define GC_CLOCK_100_200 (1 << 0)
1409 +#define GC_CLOCK_100_133 (2 << 0)
1410 +#define GC_CLOCK_166_250 (3 << 0)
1411 +#define GCFGC 0xf0 /* 915+ only */
1412 +#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
1413 +#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
1414 +#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
1415 +#define GC_DISPLAY_CLOCK_MASK (7 << 4)
1420 +#define VGA_ST01_MDA 0x3ba
1421 +#define VGA_ST01_CGA 0x3da
1423 +#define VGA_MSR_WRITE 0x3c2
1424 +#define VGA_MSR_READ 0x3cc
1425 +#define VGA_MSR_MEM_EN (1<<1)
1426 +#define VGA_MSR_CGA_MODE (1<<0)
1428 +#define VGA_SR_INDEX 0x3c4
1429 +#define VGA_SR_DATA 0x3c5
1431 +#define VGA_AR_INDEX 0x3c0
1432 +#define VGA_AR_VID_EN (1<<5)
1433 +#define VGA_AR_DATA_WRITE 0x3c0
1434 +#define VGA_AR_DATA_READ 0x3c1
1436 +#define VGA_GR_INDEX 0x3ce
1437 +#define VGA_GR_DATA 0x3cf
1439 +#define VGA_GR_MEM_READ_MODE_SHIFT 3
1440 +#define VGA_GR_MEM_READ_MODE_PLANE 1
1442 +#define VGA_GR_MEM_MODE_MASK 0xc
1443 +#define VGA_GR_MEM_MODE_SHIFT 2
1444 +#define VGA_GR_MEM_A0000_AFFFF 0
1445 +#define VGA_GR_MEM_A0000_BFFFF 1
1446 +#define VGA_GR_MEM_B0000_B7FFF 2
1447 +#define VGA_GR_MEM_B0000_BFFFF 3
1449 +#define VGA_DACMASK 0x3c6
1450 +#define VGA_DACRX 0x3c7
1451 +#define VGA_DACWX 0x3c8
1452 +#define VGA_DACDATA 0x3c9
1454 +#define VGA_CR_INDEX_MDA 0x3b4
1455 +#define VGA_CR_DATA_MDA 0x3b5
1456 +#define VGA_CR_INDEX_CGA 0x3d4
1457 +#define VGA_CR_DATA_CGA 0x3d5
1460 + * Memory interface instructions used by the kernel
1462 +#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
1464 +#define MI_NOOP MI_INSTR(0, 0)
1465 +#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
1466 +#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
1467 +#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
1468 +#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
1469 +#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
1470 +#define MI_FLUSH MI_INSTR(0x04, 0)
1471 +#define MI_READ_FLUSH (1 << 0)
1472 +#define MI_EXE_FLUSH (1 << 1)
1473 +#define MI_NO_WRITE_FLUSH (1 << 2)
1474 +#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
1475 +#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
1476 +#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
1477 +#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
1478 +#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
1479 +#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
1480 +#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
1481 +#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
1482 +#define MI_STORE_DWORD_INDEX_SHIFT 2
1483 +#define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1)
1484 +#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
1485 +#define MI_BATCH_NON_SECURE (1)
1486 +#define MI_BATCH_NON_SECURE_I965 (1<<8)
1487 +#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
1490 + * 3D instructions used by the kernel
1492 +#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
1494 +#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
1495 +#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
1496 +#define SC_UPDATE_SCISSOR (0x1<<1)
1497 +#define SC_ENABLE_MASK (0x1<<0)
1498 +#define SC_ENABLE (0x1<<0)
1499 +#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
1500 +#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
1501 +#define SCI_YMIN_MASK (0xffff<<16)
1502 +#define SCI_XMIN_MASK (0xffff<<0)
1503 +#define SCI_YMAX_MASK (0xffff<<16)
1504 +#define SCI_XMAX_MASK (0xffff<<0)
1505 +#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
1506 +#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
1507 +#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
1508 +#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
1509 +#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
1510 +#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
1511 +#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
1512 +#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
1513 +#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
1514 +#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
1515 +#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
1516 +#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
1517 +#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
1518 +#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
1519 +#define BLT_DEPTH_8 (0<<24)
1520 +#define BLT_DEPTH_16_565 (1<<24)
1521 +#define BLT_DEPTH_16_1555 (2<<24)
1522 +#define BLT_DEPTH_32 (3<<24)
1523 +#define BLT_ROP_GXCOPY (0xcc<<16)
1524 +#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
1525 +#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
1526 +#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
1527 +#define ASYNC_FLIP (1<<22)
1528 +#define DISPLAY_PLANE_A (0<<20)
1529 +#define DISPLAY_PLANE_B (1<<20)
1532 + * Instruction and interrupt control regs
1535 +#define PRB0_TAIL 0x02030
1536 +#define PRB0_HEAD 0x02034
1537 +#define PRB0_START 0x02038
1538 +#define PRB0_CTL 0x0203c
1539 +#define TAIL_ADDR 0x001FFFF8
1540 +#define HEAD_WRAP_COUNT 0xFFE00000
1541 +#define HEAD_WRAP_ONE 0x00200000
1542 +#define HEAD_ADDR 0x001FFFFC
1543 +#define RING_NR_PAGES 0x001FF000
1544 +#define RING_REPORT_MASK 0x00000006
1545 +#define RING_REPORT_64K 0x00000002
1546 +#define RING_REPORT_128K 0x00000004
1547 +#define RING_NO_REPORT 0x00000000
1548 +#define RING_VALID_MASK 0x00000001
1549 +#define RING_VALID 0x00000001
1550 +#define RING_INVALID 0x00000000
1551 +#define PRB1_TAIL 0x02040 /* 915+ only */
1552 +#define PRB1_HEAD 0x02044 /* 915+ only */
1553 +#define PRB1_START 0x02048 /* 915+ only */
1554 +#define PRB1_CTL 0x0204c /* 915+ only */
1555 +#define ACTHD_I965 0x02074
1556 +#define HWS_PGA 0x02080
1557 +#define HWS_ADDRESS_MASK 0xfffff000
1558 +#define HWS_START_ADDRESS_SHIFT 4
1559 +#define IPEIR 0x02088
1560 +#define NOPID 0x02094
1561 +#define HWSTAM 0x02098
1562 +#define SCPD0 0x0209c /* 915+ only */
1563 +#define IER 0x020a0
1564 +#define IIR 0x020a4
1565 +#define IMR 0x020a8
1566 +#define ISR 0x020ac
1567 +#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
1568 +#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
1569 +#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
1570 +#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14)
1571 +#define I915_HWB_OOM_INTERRUPT (1<<13)
1572 +#define I915_SYNC_STATUS_INTERRUPT (1<<12)
1573 +#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
1574 +#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
1575 +#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
1576 +#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
1577 +#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
1578 +#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
1579 +#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
1580 +#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
1581 +#define I915_DEBUG_INTERRUPT (1<<2)
1582 +#define I915_USER_INTERRUPT (1<<1)
1583 +#define I915_ASLE_INTERRUPT (1<<0)
1584 +#define EIR 0x020b0
1585 +#define EMR 0x020b4
1586 +#define ESR 0x020b8
1587 +#define INSTPM 0x020c0
1588 +#define ACTHD 0x020c8
1589 +#define FW_BLC 0x020d8
1590 +#define FW_BLC_SELF 0x020e0 /* 915+ only */
1591 +#define MI_ARB_STATE 0x020e4 /* 915+ only */
1592 +#define CACHE_MODE_0 0x02120 /* 915+ only */
1593 +#define CM0_MASK_SHIFT 16
1594 +#define CM0_IZ_OPT_DISABLE (1<<6)
1595 +#define CM0_ZR_OPT_DISABLE (1<<5)
1596 +#define CM0_DEPTH_EVICT_DISABLE (1<<4)
1597 +#define CM0_COLOR_EVICT_DISABLE (1<<3)
1598 +#define CM0_DEPTH_WRITE_DISABLE (1<<1)
1599 +#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
1600 +#define GFX_FLSH_CNTL 0x02170 /* 915+ only */
1603 + * Framebuffer compression (915+ only)
1606 +#define FBC_CFB_BASE 0x03200 /* 4k page aligned */
1607 +#define FBC_LL_BASE 0x03204 /* 4k page aligned */
1608 +#define FBC_CONTROL 0x03208
1609 +#define FBC_CTL_EN (1<<31)
1610 +#define FBC_CTL_PERIODIC (1<<30)
1611 +#define FBC_CTL_INTERVAL_SHIFT (16)
1612 +#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
1613 +#define FBC_CTL_STRIDE_SHIFT (5)
1614 +#define FBC_CTL_FENCENO (1<<0)
1615 +#define FBC_COMMAND 0x0320c
1616 +#define FBC_CMD_COMPRESS (1<<0)
1617 +#define FBC_STATUS 0x03210
1618 +#define FBC_STAT_COMPRESSING (1<<31)
1619 +#define FBC_STAT_COMPRESSED (1<<30)
1620 +#define FBC_STAT_MODIFIED (1<<29)
1621 +#define FBC_STAT_CURRENT_LINE (1<<0)
1622 +#define FBC_CONTROL2 0x03214
1623 +#define FBC_CTL_FENCE_DBL (0<<4)
1624 +#define FBC_CTL_IDLE_IMM (0<<2)
1625 +#define FBC_CTL_IDLE_FULL (1<<2)
1626 +#define FBC_CTL_IDLE_LINE (2<<2)
1627 +#define FBC_CTL_IDLE_DEBUG (3<<2)
1628 +#define FBC_CTL_CPU_FENCE (1<<1)
1629 +#define FBC_CTL_PLANEA (0<<0)
1630 +#define FBC_CTL_PLANEB (1<<0)
1631 +#define FBC_FENCE_OFF 0x0321b
1633 +#define FBC_LL_SIZE (1536)
1638 +#define GPIOA 0x5010
1639 +#define GPIOB 0x5014
1640 +#define GPIOC 0x5018
1641 +#define GPIOD 0x501c
1642 +#define GPIOE 0x5020
1643 +#define GPIOF 0x5024
1644 +#define GPIOG 0x5028
1645 +#define GPIOH 0x502c
1646 +# define GPIO_CLOCK_DIR_MASK (1 << 0)
1647 +# define GPIO_CLOCK_DIR_IN (0 << 1)
1648 +# define GPIO_CLOCK_DIR_OUT (1 << 1)
1649 +# define GPIO_CLOCK_VAL_MASK (1 << 2)
1650 +# define GPIO_CLOCK_VAL_OUT (1 << 3)
1651 +# define GPIO_CLOCK_VAL_IN (1 << 4)
1652 +# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
1653 +# define GPIO_DATA_DIR_MASK (1 << 8)
1654 +# define GPIO_DATA_DIR_IN (0 << 9)
1655 +# define GPIO_DATA_DIR_OUT (1 << 9)
1656 +# define GPIO_DATA_VAL_MASK (1 << 10)
1657 +# define GPIO_DATA_VAL_OUT (1 << 11)
1658 +# define GPIO_DATA_VAL_IN (1 << 12)
1659 +# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
1662 + * Clock control & power management
1665 +#define VGA0 0x6000
1666 +#define VGA1 0x6004
1667 +#define VGA_PD 0x6010
1668 +#define VGA0_PD_P2_DIV_4 (1 << 7)
1669 +#define VGA0_PD_P1_DIV_2 (1 << 5)
1670 +#define VGA0_PD_P1_SHIFT 0
1671 +#define VGA0_PD_P1_MASK (0x1f << 0)
1672 +#define VGA1_PD_P2_DIV_4 (1 << 15)
1673 +#define VGA1_PD_P1_DIV_2 (1 << 13)
1674 +#define VGA1_PD_P1_SHIFT 8
1675 +#define VGA1_PD_P1_MASK (0x1f << 8)
1676 +#define DPLL_A 0x06014
1677 +#define DPLL_B 0x06018
1678 +#define DPLL_VCO_ENABLE (1 << 31)
1679 +#define DPLL_DVO_HIGH_SPEED (1 << 30)
1680 +#define DPLL_SYNCLOCK_ENABLE (1 << 29)
1681 +#define DPLL_VGA_MODE_DIS (1 << 28)
1682 +#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
1683 +#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
1684 +#define DPLL_MODE_MASK (3 << 26)
1685 +#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
1686 +#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
1687 +#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
1688 +#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
1689 +#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
1690 +#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
1692 +#define I915_FIFO_UNDERRUN_STATUS (1UL<<31)
1693 +#define I915_CRC_ERROR_ENABLE (1UL<<29)
1694 +#define I915_CRC_DONE_ENABLE (1UL<<28)
1695 +#define I915_GMBUS_EVENT_ENABLE (1UL<<27)
1696 +#define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25)
1697 +#define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
1698 +#define I915_DPST_EVENT_ENABLE (1UL<<23)
1699 +#define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
1700 +#define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
1701 +#define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
1702 +#define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
1703 +#define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
1704 +#define I915_OVERLAY_UPDATED_ENABLE (1UL<<16)
1705 +#define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
1706 +#define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
1707 +#define I915_GMBUS_INTERRUPT_STATUS (1UL<<11)
1708 +#define I915_VSYNC_INTERRUPT_STATUS (1UL<<9)
1709 +#define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
1710 +#define I915_DPST_EVENT_STATUS (1UL<<7)
1711 +#define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6)
1712 +#define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
1713 +#define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
1714 +#define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
1715 +#define I915_VBLANK_INTERRUPT_STATUS (1UL<<1)
1716 +#define I915_OVERLAY_UPDATED_STATUS (1UL<<0)
1718 +#define SRX_INDEX 0x3c4
1719 +#define SRX_DATA 0x3c5
1721 +#define SR01_SCREEN_OFF (1<<5)
1723 +#define PPCR 0x61204
1724 +#define PPCR_ON (1<<0)
1726 +#define DVOB 0x61140
1727 +#define DVOB_ON (1<<31)
1728 +#define DVOC 0x61160
1729 +#define DVOC_ON (1<<31)
1730 +#define LVDS 0x61180
1731 +#define LVDS_ON (1<<31)
1733 +#define ADPA 0x61100
1734 +#define ADPA_DPMS_MASK (~(3<<10))
1735 +#define ADPA_DPMS_ON (0<<10)
1736 +#define ADPA_DPMS_SUSPEND (1<<10)
1737 +#define ADPA_DPMS_STANDBY (2<<10)
1738 +#define ADPA_DPMS_OFF (3<<10)
1740 +#define RING_TAIL 0x00
1741 +#define TAIL_ADDR 0x001FFFF8
1742 +#define RING_HEAD 0x04
1743 +#define HEAD_WRAP_COUNT 0xFFE00000
1744 +#define HEAD_WRAP_ONE 0x00200000
1745 +#define HEAD_ADDR 0x001FFFFC
1746 +#define RING_START 0x08
1747 +#define START_ADDR 0xFFFFF000
1748 +#define RING_LEN 0x0C
1749 +#define RING_NR_PAGES 0x001FF000
1750 +#define RING_REPORT_MASK 0x00000006
1751 +#define RING_REPORT_64K 0x00000002
1752 +#define RING_REPORT_128K 0x00000004
1753 +#define RING_NO_REPORT 0x00000000
1754 +#define RING_VALID_MASK 0x00000001
1755 +#define RING_VALID 0x00000001
1756 +#define RING_INVALID 0x00000000
1758 +/* Scratch pad debug 0 reg:
1760 +#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
1762 + * The i830 generation, in LVDS mode, defines P1 as the bit number set within
1763 + * this field (only one bit may be set).
1765 +#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
1766 +#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
1767 +/* i830, required in DVO non-gang */
1768 +#define PLL_P2_DIVIDE_BY_4 (1 << 23)
1769 +#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
1770 +#define PLL_REF_INPUT_DREFCLK (0 << 13)
1771 +#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
1772 +#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
1773 +#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
1774 +#define PLL_REF_INPUT_MASK (3 << 13)
1775 +#define PLL_LOAD_PULSE_PHASE_SHIFT 9
1777 + * Parallel to Serial Load Pulse phase selection.
1778 + * Selects the phase for the 10X DPLL clock for the PCIe
1779 + * digital display port. The range is 4 to 13; 10 or more
1780 + * is just a flip delay. The default is 6
1782 +#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
1783 +#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
1785 + * SDVO multiplier for 945G/GM. Not used on 965.
1787 +#define SDVO_MULTIPLIER_MASK 0x000000ff
1788 +#define SDVO_MULTIPLIER_SHIFT_HIRES 4
1789 +#define SDVO_MULTIPLIER_SHIFT_VGA 0
1790 +#define DPLL_A_MD 0x0601c /* 965+ only */
1792 + * UDI pixel divider, controlling how many pixels are stuffed into a packet.
1794 + * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
1796 +#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
1797 +#define DPLL_MD_UDI_DIVIDER_SHIFT 24
1798 +/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
1799 +#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
1800 +#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
1802 + * SDVO/UDI pixel multiplier.
1804 + * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
1805 + * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
1806 + * modes, the bus rate would be below the limits, so SDVO allows for stuffing
1807 + * dummy bytes in the datastream at an increased clock rate, with both sides of
1808 + * the link knowing how many bytes are fill.
1810 + * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
1811 + * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
1812 + * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
1813 + * through an SDVO command.
1815 + * This register field has values of multiplication factor minus 1, with
1816 + * a maximum multiplier of 5 for SDVO.
1818 +#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
1819 +#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
1821 + * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
1822 + * This best be set to the default value (3) or the CRT won't work. No,
1823 + * I don't entirely understand what this does...
1825 +#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
1826 +#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
1827 +#define DPLL_B_MD 0x06020 /* 965+ only */
1828 +#define FPA0 0x06040
1829 +#define FPA1 0x06044
1830 +#define FPB0 0x06048
1831 +#define FPB1 0x0604c
1832 +#define FP_N_DIV_MASK 0x003f0000
1833 +#define FP_N_DIV_SHIFT 16
1834 +#define FP_M1_DIV_MASK 0x00003f00
1835 +#define FP_M1_DIV_SHIFT 8
1836 +#define FP_M2_DIV_MASK 0x0000003f
1837 +#define FP_M2_DIV_SHIFT 0
1838 +#define DPLL_TEST 0x606c
1839 +#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
1840 +#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
1841 +#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
1842 +#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
1843 +#define DPLLB_TEST_N_BYPASS (1 << 19)
1844 +#define DPLLB_TEST_M_BYPASS (1 << 18)
1845 +#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
1846 +#define DPLLA_TEST_N_BYPASS (1 << 3)
1847 +#define DPLLA_TEST_M_BYPASS (1 << 2)
1848 +#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
1849 +#define D_STATE 0x6104
1850 +#define CG_2D_DIS 0x6200
1851 +#define CG_3D_DIS 0x6204
1857 +#define PALETTE_A 0x0a000
1858 +#define PALETTE_B 0x0a800
1864 +#define OVADD 0x30000
1865 +#define DOVSTA 0x30008
1866 +#define OC_BUF (0x3<<20)
1867 +#define OGAMC5 0x30010
1868 +#define OGAMC4 0x30014
1869 +#define OGAMC3 0x30018
1870 +#define OGAMC2 0x3001c
1871 +#define OGAMC1 0x30020
1872 +#define OGAMC0 0x30024
1875 + * Display engine regs
1878 +/* Pipe A timing regs */
1879 +#define HTOTAL_A 0x60000
1880 +#define HBLANK_A 0x60004
1881 +#define HSYNC_A 0x60008
1882 +#define VTOTAL_A 0x6000c
1883 +#define VBLANK_A 0x60010
1884 +#define VSYNC_A 0x60014
1885 +#define PIPEASRC 0x6001c
1886 +#define BCLRPAT_A 0x60020
1888 +/* Pipe B timing regs */
1889 +#define HTOTAL_B 0x61000
1890 +#define HBLANK_B 0x61004
1891 +#define HSYNC_B 0x61008
1892 +#define VTOTAL_B 0x6100c
1893 +#define VBLANK_B 0x61010
1894 +#define VSYNC_B 0x61014
1895 +#define PIPEBSRC 0x6101c
1896 +#define BCLRPAT_B 0x61020
1898 +/* VGA port control */
1899 +#define ADPA 0x61100
1900 +#define ADPA_DAC_ENABLE (1<<31)
1901 +#define ADPA_DAC_DISABLE 0
1902 +#define ADPA_PIPE_SELECT_MASK (1<<30)
1903 +#define ADPA_PIPE_A_SELECT 0
1904 +#define ADPA_PIPE_B_SELECT (1<<30)
1905 +#define ADPA_USE_VGA_HVPOLARITY (1<<15)
1906 +#define ADPA_SETS_HVPOLARITY 0
1907 +#define ADPA_VSYNC_CNTL_DISABLE (1<<11)
1908 +#define ADPA_VSYNC_CNTL_ENABLE 0
1909 +#define ADPA_HSYNC_CNTL_DISABLE (1<<10)
1910 +#define ADPA_HSYNC_CNTL_ENABLE 0
1911 +#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
1912 +#define ADPA_VSYNC_ACTIVE_LOW 0
1913 +#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
1914 +#define ADPA_HSYNC_ACTIVE_LOW 0
1915 +#define ADPA_DPMS_MASK (~(3<<10))
1916 +#define ADPA_DPMS_ON (0<<10)
1917 +#define ADPA_DPMS_SUSPEND (1<<10)
1918 +#define ADPA_DPMS_STANDBY (2<<10)
1919 +#define ADPA_DPMS_OFF (3<<10)
1921 +/* Hotplug control (945+ only) */
1922 +#define PORT_HOTPLUG_EN 0x61110
1923 +#define SDVOB_HOTPLUG_INT_EN (1 << 26)
1924 +#define SDVOC_HOTPLUG_INT_EN (1 << 25)
1925 +#define TV_HOTPLUG_INT_EN (1 << 18)
1926 +#define CRT_HOTPLUG_INT_EN (1 << 9)
1927 +#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
1929 +#define PORT_HOTPLUG_STAT 0x61114
1930 +#define CRT_HOTPLUG_INT_STATUS (1 << 11)
1931 +#define TV_HOTPLUG_INT_STATUS (1 << 10)
1932 +#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
1933 +#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
1934 +#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
1935 +#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
1936 +#define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
1937 +#define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
1939 +/* SDVO port control */
1940 +#define SDVOB 0x61140
1941 +#define SDVOC 0x61160
1942 +#define SDVO_ENABLE (1 << 31)
1943 +#define SDVO_PIPE_B_SELECT (1 << 30)
1944 +#define SDVO_STALL_SELECT (1 << 29)
1945 +#define SDVO_INTERRUPT_ENABLE (1 << 26)
1947 + * 915G/GM SDVO pixel multiplier.
1949 + * Programmed value is multiplier - 1, up to 5x.
1951 + * \sa DPLL_MD_UDI_MULTIPLIER_MASK
1953 +#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
1954 +#define SDVO_PORT_MULTIPLY_SHIFT 23
1955 +#define SDVO_PHASE_SELECT_MASK (15 << 19)
1956 +#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
1957 +#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
1958 +#define SDVOC_GANG_MODE (1 << 16)
1959 +#define SDVO_BORDER_ENABLE (1 << 7)
1960 +#define SDVOB_PCIE_CONCURRENCY (1 << 3)
1961 +#define SDVO_DETECTED (1 << 2)
1962 +/* Bits to be preserved when writing */
1963 +#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
1964 +#define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
1966 +/* DVO port control */
1967 +#define DVOA 0x61120
1968 +#define DVOB 0x61140
1969 +#define DVOC 0x61160
1970 +#define DVO_ENABLE (1 << 31)
1971 +#define DVO_PIPE_B_SELECT (1 << 30)
1972 +#define DVO_PIPE_STALL_UNUSED (0 << 28)
1973 +#define DVO_PIPE_STALL (1 << 28)
1974 +#define DVO_PIPE_STALL_TV (2 << 28)
1975 +#define DVO_PIPE_STALL_MASK (3 << 28)
1976 +#define DVO_USE_VGA_SYNC (1 << 15)
1977 +#define DVO_DATA_ORDER_I740 (0 << 14)
1978 +#define DVO_DATA_ORDER_FP (1 << 14)
1979 +#define DVO_VSYNC_DISABLE (1 << 11)
1980 +#define DVO_HSYNC_DISABLE (1 << 10)
1981 +#define DVO_VSYNC_TRISTATE (1 << 9)
1982 +#define DVO_HSYNC_TRISTATE (1 << 8)
1983 +#define DVO_BORDER_ENABLE (1 << 7)
1984 +#define DVO_DATA_ORDER_GBRG (1 << 6)
1985 +#define DVO_DATA_ORDER_RGGB (0 << 6)
1986 +#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
1987 +#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
1988 +#define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
1989 +#define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
1990 +#define DVO_BLANK_ACTIVE_HIGH (1 << 2)
1991 +#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
1992 +#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
1993 +#define DVO_PRESERVE_MASK (0x7<<24)
1994 +#define DVOA_SRCDIM 0x61124
1995 +#define DVOB_SRCDIM 0x61144
1996 +#define DVOC_SRCDIM 0x61164
1997 +#define DVO_SRCDIM_HORIZONTAL_SHIFT 12
1998 +#define DVO_SRCDIM_VERTICAL_SHIFT 0
2000 +/* LVDS port control */
2001 +#define LVDS 0x61180
2003 + * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
2004 + * the DPLL semantics change when the LVDS is assigned to that pipe.
2006 +#define LVDS_PORT_EN (1 << 31)
2007 +/* Selects pipe B for LVDS data. Must be set on pre-965. */
2008 +#define LVDS_PIPEB_SELECT (1 << 30)
2010 + * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
2013 +#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
2014 +#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
2015 +#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
2017 + * Controls the A3 data pair, which contains the additional LSBs for 24 bit
2018 + * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
2021 +#define LVDS_A3_POWER_MASK (3 << 6)
2022 +#define LVDS_A3_POWER_DOWN (0 << 6)
2023 +#define LVDS_A3_POWER_UP (3 << 6)
2025 + * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
2028 +#define LVDS_CLKB_POWER_MASK (3 << 4)
2029 +#define LVDS_CLKB_POWER_DOWN (0 << 4)
2030 +#define LVDS_CLKB_POWER_UP (3 << 4)
2032 + * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
2033 + * setting for whether we are in dual-channel mode. The B3 pair will
2034 + * additionally only be powered up when LVDS_A3_POWER_UP is set.
2036 +#define LVDS_B0B3_POWER_MASK (3 << 2)
2037 +#define LVDS_B0B3_POWER_DOWN (0 << 2)
2038 +#define LVDS_B0B3_POWER_UP (3 << 2)
2040 +/* Panel power sequencing */
2041 +#define PP_STATUS 0x61200
2042 +#define PP_ON (1 << 31)
2044 + * Indicates that all dependencies of the panel are on:
2048 + * - LVDS/DVOB/DVOC on
2050 +#define PP_READY (1 << 30)
2051 +#define PP_SEQUENCE_NONE (0 << 28)
2052 +#define PP_SEQUENCE_ON (1 << 28)
2053 +#define PP_SEQUENCE_OFF (2 << 28)
2054 +#define PP_SEQUENCE_MASK 0x30000000
2055 +#define PP_CONTROL 0x61204
2056 +#define POWER_TARGET_ON (1 << 0)
2057 +#define PP_ON_DELAYS 0x61208
2058 +#define PP_OFF_DELAYS 0x6120c
2059 +#define PP_DIVISOR 0x61210
2061 +/* Panel fitting */
2062 +#define PFIT_CONTROL 0x61230
2063 +#define PFIT_ENABLE (1 << 31)
2064 +#define PFIT_PIPE_MASK (3 << 29)
2065 +#define PFIT_PIPE_SHIFT 29
2066 +#define VERT_INTERP_DISABLE (0 << 10)
2067 +#define VERT_INTERP_BILINEAR (1 << 10)
2068 +#define VERT_INTERP_MASK (3 << 10)
2069 +#define VERT_AUTO_SCALE (1 << 9)
2070 +#define HORIZ_INTERP_DISABLE (0 << 6)
2071 +#define HORIZ_INTERP_BILINEAR (1 << 6)
2072 +#define HORIZ_INTERP_MASK (3 << 6)
2073 +#define HORIZ_AUTO_SCALE (1 << 5)
2074 +#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
2075 +#define PFIT_PGM_RATIOS 0x61234
2076 +#define PFIT_VERT_SCALE_MASK 0xfff00000
2077 +#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
2078 +#define PFIT_AUTO_RATIOS 0x61238
2080 +/* Backlight control */
2081 +#define BLC_PWM_CTL 0x61254
2082 +#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
2083 +#define BLC_PWM_CTL2 0x61250 /* 965+ only */
2085 + * This is the most significant 15 bits of the number of backlight cycles in a
2086 + * complete cycle of the modulated backlight control.
2088 + * The actual value is this field multiplied by two.
2090 +#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
2091 +#define BLM_LEGACY_MODE (1 << 16)
2093 + * This is the number of cycles out of the backlight modulation cycle for which
2094 + * the backlight is on.
2096 + * This field must be no greater than the number of cycles in the complete
2097 + * backlight modulation cycle.
2099 +#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
2100 +#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
2102 +/* TV port control */
2103 +#define TV_CTL 0x68000
2104 +/** Enables the TV encoder */
2105 +# define TV_ENC_ENABLE (1 << 31)
2106 +/** Sources the TV encoder input from pipe B instead of A. */
2107 +# define TV_ENC_PIPEB_SELECT (1 << 30)
2108 +/** Outputs composite video (DAC A only) */
2109 +# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
2110 +/** Outputs SVideo video (DAC B/C) */
2111 +# define TV_ENC_OUTPUT_SVIDEO (1 << 28)
2112 +/** Outputs Component video (DAC A/B/C) */
2113 +# define TV_ENC_OUTPUT_COMPONENT (2 << 28)
2114 +/** Outputs Composite and SVideo (DAC A/B/C) */
2115 +# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
2116 +# define TV_TRILEVEL_SYNC (1 << 21)
2117 +/** Enables slow sync generation (945GM only) */
2118 +# define TV_SLOW_SYNC (1 << 20)
2119 +/** Selects 4x oversampling for 480i and 576p */
2120 +# define TV_OVERSAMPLE_4X (0 << 18)
2121 +/** Selects 2x oversampling for 720p and 1080i */
2122 +# define TV_OVERSAMPLE_2X (1 << 18)
2123 +/** Selects no oversampling for 1080p */
2124 +# define TV_OVERSAMPLE_NONE (2 << 18)
2125 +/** Selects 8x oversampling */
2126 +# define TV_OVERSAMPLE_8X (3 << 18)
2127 +/** Selects progressive mode rather than interlaced */
2128 +# define TV_PROGRESSIVE (1 << 17)
2129 +/** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
2130 +# define TV_PAL_BURST (1 << 16)
2131 +/** Field for setting delay of Y compared to C */
2132 +# define TV_YC_SKEW_MASK (7 << 12)
2133 +/** Enables a fix for 480p/576p standard definition modes on the 915GM only */
2134 +# define TV_ENC_SDP_FIX (1 << 11)
2136 + * Enables a fix for the 915GM only.
2138 + * Not sure what it does.
2140 +# define TV_ENC_C0_FIX (1 << 10)
2141 +/** Bits that must be preserved by software */
2142 +# define TV_CTL_SAVE ((3 << 8) | (3 << 6))
2143 +# define TV_FUSE_STATE_MASK (3 << 4)
2144 +/** Read-only state that reports all features enabled */
2145 +# define TV_FUSE_STATE_ENABLED (0 << 4)
2146 +/** Read-only state that reports that Macrovision is disabled in hardware*/
2147 +# define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
2148 +/** Read-only state that reports that TV-out is disabled in hardware. */
2149 +# define TV_FUSE_STATE_DISABLED (2 << 4)
2150 +/** Normal operation */
2151 +# define TV_TEST_MODE_NORMAL (0 << 0)
2152 +/** Encoder test pattern 1 - combo pattern */
2153 +# define TV_TEST_MODE_PATTERN_1 (1 << 0)
2154 +/** Encoder test pattern 2 - full screen vertical 75% color bars */
2155 +# define TV_TEST_MODE_PATTERN_2 (2 << 0)
2156 +/** Encoder test pattern 3 - full screen horizontal 75% color bars */
2157 +# define TV_TEST_MODE_PATTERN_3 (3 << 0)
2158 +/** Encoder test pattern 4 - random noise */
2159 +# define TV_TEST_MODE_PATTERN_4 (4 << 0)
2160 +/** Encoder test pattern 5 - linear color ramps */
2161 +# define TV_TEST_MODE_PATTERN_5 (5 << 0)
2163 + * This test mode forces the DACs to 50% of full output.
2165 + * This is used for load detection in combination with TVDAC_SENSE_MASK
2167 +# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
2168 +# define TV_TEST_MODE_MASK (7 << 0)
2170 +#define TV_DAC 0x68004
2172 + * Reports that DAC state change logic has reported change (RO).
2174 + * This gets cleared when TV_DAC_STATE_EN is cleared
2176 +# define TVDAC_STATE_CHG (1 << 31)
2177 +# define TVDAC_SENSE_MASK (7 << 28)
2178 +/** Reports that DAC A voltage is above the detect threshold */
2179 +# define TVDAC_A_SENSE (1 << 30)
2180 +/** Reports that DAC B voltage is above the detect threshold */
2181 +# define TVDAC_B_SENSE (1 << 29)
2182 +/** Reports that DAC C voltage is above the detect threshold */
2183 +# define TVDAC_C_SENSE (1 << 28)
2185 + * Enables DAC state detection logic, for load-based TV detection.
2187 + * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
2188 + * to off, for load detection to work.
2190 +# define TVDAC_STATE_CHG_EN (1 << 27)
2191 +/** Sets the DAC A sense value to high */
2192 +# define TVDAC_A_SENSE_CTL (1 << 26)
2193 +/** Sets the DAC B sense value to high */
2194 +# define TVDAC_B_SENSE_CTL (1 << 25)
2195 +/** Sets the DAC C sense value to high */
2196 +# define TVDAC_C_SENSE_CTL (1 << 24)
2197 +/** Overrides the ENC_ENABLE and DAC voltage levels */
2198 +# define DAC_CTL_OVERRIDE (1 << 7)
2199 +/** Sets the slew rate. Must be preserved in software */
2200 +# define ENC_TVDAC_SLEW_FAST (1 << 6)
2201 +# define DAC_A_1_3_V (0 << 4)
2202 +# define DAC_A_1_1_V (1 << 4)
2203 +# define DAC_A_0_7_V (2 << 4)
2204 +# define DAC_A_OFF (3 << 4)
2205 +# define DAC_B_1_3_V (0 << 2)
2206 +# define DAC_B_1_1_V (1 << 2)
2207 +# define DAC_B_0_7_V (2 << 2)
2208 +# define DAC_B_OFF (3 << 2)
2209 +# define DAC_C_1_3_V (0 << 0)
2210 +# define DAC_C_1_1_V (1 << 0)
2211 +# define DAC_C_0_7_V (2 << 0)
2212 +# define DAC_C_OFF (3 << 0)
2215 + * CSC coefficients are stored in a floating point format with 9 bits of
2216 + * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
2217 + * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
2218 + * -1 (0x3) being the only legal negative value.
2220 +#define TV_CSC_Y 0x68010
2221 +# define TV_RY_MASK 0x07ff0000
2222 +# define TV_RY_SHIFT 16
2223 +# define TV_GY_MASK 0x00000fff
2224 +# define TV_GY_SHIFT 0
2226 +#define TV_CSC_Y2 0x68014
2227 +# define TV_BY_MASK 0x07ff0000
2228 +# define TV_BY_SHIFT 16
2230 + * Y attenuation for component video.
2232 + * Stored in 1.9 fixed point.
2234 +# define TV_AY_MASK 0x000003ff
2235 +# define TV_AY_SHIFT 0
2237 +#define TV_CSC_U 0x68018
2238 +# define TV_RU_MASK 0x07ff0000
2239 +# define TV_RU_SHIFT 16
2240 +# define TV_GU_MASK 0x000007ff
2241 +# define TV_GU_SHIFT 0
2243 +#define TV_CSC_U2 0x6801c
2244 +# define TV_BU_MASK 0x07ff0000
2245 +# define TV_BU_SHIFT 16
2247 + * U attenuation for component video.
2249 + * Stored in 1.9 fixed point.
2251 +# define TV_AU_MASK 0x000003ff
2252 +# define TV_AU_SHIFT 0
2254 +#define TV_CSC_V 0x68020
2255 +# define TV_RV_MASK 0x0fff0000
2256 +# define TV_RV_SHIFT 16
2257 +# define TV_GV_MASK 0x000007ff
2258 +# define TV_GV_SHIFT 0
2260 +#define TV_CSC_V2 0x68024
2261 +# define TV_BV_MASK 0x07ff0000
2262 +# define TV_BV_SHIFT 16
2264 + * V attenuation for component video.
2266 + * Stored in 1.9 fixed point.
2268 +# define TV_AV_MASK 0x000007ff
2269 +# define TV_AV_SHIFT 0
2271 +#define TV_CLR_KNOBS 0x68028
2272 +/** 2s-complement brightness adjustment */
2273 +# define TV_BRIGHTNESS_MASK 0xff000000
2274 +# define TV_BRIGHTNESS_SHIFT 24
2275 +/** Contrast adjustment, as a 2.6 unsigned floating point number */
2276 +# define TV_CONTRAST_MASK 0x00ff0000
2277 +# define TV_CONTRAST_SHIFT 16
2278 +/** Saturation adjustment, as a 2.6 unsigned floating point number */
2279 +# define TV_SATURATION_MASK 0x0000ff00
2280 +# define TV_SATURATION_SHIFT 8
2281 +/** Hue adjustment, as an integer phase angle in degrees */
2282 +# define TV_HUE_MASK 0x000000ff
2283 +# define TV_HUE_SHIFT 0
2285 +#define TV_CLR_LEVEL 0x6802c
2286 +/** Controls the DAC level for black */
2287 +# define TV_BLACK_LEVEL_MASK 0x01ff0000
2288 +# define TV_BLACK_LEVEL_SHIFT 16
2289 +/** Controls the DAC level for blanking */
2290 +# define TV_BLANK_LEVEL_MASK 0x000001ff
2291 +# define TV_BLANK_LEVEL_SHIFT 0
2293 +#define TV_H_CTL_1 0x68030
2294 +/** Number of pixels in the hsync. */
2295 +# define TV_HSYNC_END_MASK 0x1fff0000
2296 +# define TV_HSYNC_END_SHIFT 16
2297 +/** Total number of pixels minus one in the line (display and blanking). */
2298 +# define TV_HTOTAL_MASK 0x00001fff
2299 +# define TV_HTOTAL_SHIFT 0
2301 +#define TV_H_CTL_2 0x68034
2302 +/** Enables the colorburst (needed for non-component color) */
2303 +# define TV_BURST_ENA (1 << 31)
2304 +/** Offset of the colorburst from the start of hsync, in pixels minus one. */
2305 +# define TV_HBURST_START_SHIFT 16
2306 +# define TV_HBURST_START_MASK 0x1fff0000
2307 +/** Length of the colorburst */
2308 +# define TV_HBURST_LEN_SHIFT 0
2309 +# define TV_HBURST_LEN_MASK 0x0001fff
2311 +#define TV_H_CTL_3 0x68038
2312 +/** End of hblank, measured in pixels minus one from start of hsync */
2313 +# define TV_HBLANK_END_SHIFT 16
2314 +# define TV_HBLANK_END_MASK 0x1fff0000
2315 +/** Start of hblank, measured in pixels minus one from start of hsync */
2316 +# define TV_HBLANK_START_SHIFT 0
2317 +# define TV_HBLANK_START_MASK 0x0001fff
2319 +#define TV_V_CTL_1 0x6803c
2321 +# define TV_NBR_END_SHIFT 16
2322 +# define TV_NBR_END_MASK 0x07ff0000
2324 +# define TV_VI_END_F1_SHIFT 8
2325 +# define TV_VI_END_F1_MASK 0x00003f00
2327 +# define TV_VI_END_F2_SHIFT 0
2328 +# define TV_VI_END_F2_MASK 0x0000003f
2330 +#define TV_V_CTL_2 0x68040
2331 +/** Length of vsync, in half lines */
2332 +# define TV_VSYNC_LEN_MASK 0x07ff0000
2333 +# define TV_VSYNC_LEN_SHIFT 16
2334 +/** Offset of the start of vsync in field 1, measured in one less than the
2335 + * number of half lines.
2337 +# define TV_VSYNC_START_F1_MASK 0x00007f00
2338 +# define TV_VSYNC_START_F1_SHIFT 8
2340 + * Offset of the start of vsync in field 2, measured in one less than the
2341 + * number of half lines.
2343 +# define TV_VSYNC_START_F2_MASK 0x0000007f
2344 +# define TV_VSYNC_START_F2_SHIFT 0
2346 +#define TV_V_CTL_3 0x68044
2347 +/** Enables generation of the equalization signal */
2348 +# define TV_EQUAL_ENA (1 << 31)
2349 +/** Length of vsync, in half lines */
2350 +# define TV_VEQ_LEN_MASK 0x007f0000
2351 +# define TV_VEQ_LEN_SHIFT 16
2352 +/** Offset of the start of equalization in field 1, measured in one less than
2353 + * the number of half lines.
2355 +# define TV_VEQ_START_F1_MASK 0x0007f00
2356 +# define TV_VEQ_START_F1_SHIFT 8
2358 + * Offset of the start of equalization in field 2, measured in one less than
2359 + * the number of half lines.
2361 +# define TV_VEQ_START_F2_MASK 0x000007f
2362 +# define TV_VEQ_START_F2_SHIFT 0
2364 +#define TV_V_CTL_4 0x68048
2366 + * Offset to start of vertical colorburst, measured in one less than the
2367 + * number of lines from vertical start.
2369 +# define TV_VBURST_START_F1_MASK 0x003f0000
2370 +# define TV_VBURST_START_F1_SHIFT 16
2372 + * Offset to the end of vertical colorburst, measured in one less than the
2373 + * number of lines from the start of NBR.
2375 +# define TV_VBURST_END_F1_MASK 0x000000ff
2376 +# define TV_VBURST_END_F1_SHIFT 0
2378 +#define TV_V_CTL_5 0x6804c
2380 + * Offset to start of vertical colorburst, measured in one less than the
2381 + * number of lines from vertical start.
2383 +# define TV_VBURST_START_F2_MASK 0x003f0000
2384 +# define TV_VBURST_START_F2_SHIFT 16
2386 + * Offset to the end of vertical colorburst, measured in one less than the
2387 + * number of lines from the start of NBR.
2389 +# define TV_VBURST_END_F2_MASK 0x000000ff
2390 +# define TV_VBURST_END_F2_SHIFT 0
2392 +#define TV_V_CTL_6 0x68050
2394 + * Offset to start of vertical colorburst, measured in one less than the
2395 + * number of lines from vertical start.
2397 +# define TV_VBURST_START_F3_MASK 0x003f0000
2398 +# define TV_VBURST_START_F3_SHIFT 16
2400 + * Offset to the end of vertical colorburst, measured in one less than the
2401 + * number of lines from the start of NBR.
2403 +# define TV_VBURST_END_F3_MASK 0x000000ff
2404 +# define TV_VBURST_END_F3_SHIFT 0
2406 +#define TV_V_CTL_7 0x68054
2408 + * Offset to start of vertical colorburst, measured in one less than the
2409 + * number of lines from vertical start.
2411 +# define TV_VBURST_START_F4_MASK 0x003f0000
2412 +# define TV_VBURST_START_F4_SHIFT 16
2414 + * Offset to the end of vertical colorburst, measured in one less than the
2415 + * number of lines from the start of NBR.
2417 +# define TV_VBURST_END_F4_MASK 0x000000ff
2418 +# define TV_VBURST_END_F4_SHIFT 0
2420 +#define TV_SC_CTL_1 0x68060
2421 +/** Turns on the first subcarrier phase generation DDA */
2422 +# define TV_SC_DDA1_EN (1 << 31)
2423 +/** Turns on the first subcarrier phase generation DDA */
2424 +# define TV_SC_DDA2_EN (1 << 30)
2425 +/** Turns on the first subcarrier phase generation DDA */
2426 +# define TV_SC_DDA3_EN (1 << 29)
2427 +/** Sets the subcarrier DDA to reset frequency every other field */
2428 +# define TV_SC_RESET_EVERY_2 (0 << 24)
2429 +/** Sets the subcarrier DDA to reset frequency every fourth field */
2430 +# define TV_SC_RESET_EVERY_4 (1 << 24)
2431 +/** Sets the subcarrier DDA to reset frequency every eighth field */
2432 +# define TV_SC_RESET_EVERY_8 (2 << 24)
2433 +/** Sets the subcarrier DDA to never reset the frequency */
2434 +# define TV_SC_RESET_NEVER (3 << 24)
2435 +/** Sets the peak amplitude of the colorburst.*/
2436 +# define TV_BURST_LEVEL_MASK 0x00ff0000
2437 +# define TV_BURST_LEVEL_SHIFT 16
2438 +/** Sets the increment of the first subcarrier phase generation DDA */
2439 +# define TV_SCDDA1_INC_MASK 0x00000fff
2440 +# define TV_SCDDA1_INC_SHIFT 0
2442 +#define TV_SC_CTL_2 0x68064
2443 +/** Sets the rollover for the second subcarrier phase generation DDA */
2444 +# define TV_SCDDA2_SIZE_MASK 0x7fff0000
2445 +# define TV_SCDDA2_SIZE_SHIFT 16
2446 +/** Sets the increent of the second subcarrier phase generation DDA */
2447 +# define TV_SCDDA2_INC_MASK 0x00007fff
2448 +# define TV_SCDDA2_INC_SHIFT 0
2450 +#define TV_SC_CTL_3 0x68068
2451 +/** Sets the rollover for the third subcarrier phase generation DDA */
2452 +# define TV_SCDDA3_SIZE_MASK 0x7fff0000
2453 +# define TV_SCDDA3_SIZE_SHIFT 16
2454 +/** Sets the increent of the third subcarrier phase generation DDA */
2455 +# define TV_SCDDA3_INC_MASK 0x00007fff
2456 +# define TV_SCDDA3_INC_SHIFT 0
2458 +#define TV_WIN_POS 0x68070
2459 +/** X coordinate of the display from the start of horizontal active */
2460 +# define TV_XPOS_MASK 0x1fff0000
2461 +# define TV_XPOS_SHIFT 16
2462 +/** Y coordinate of the display from the start of vertical active (NBR) */
2463 +# define TV_YPOS_MASK 0x00000fff
2464 +# define TV_YPOS_SHIFT 0
2466 +#define TV_WIN_SIZE 0x68074
2467 +/** Horizontal size of the display window, measured in pixels*/
2468 +# define TV_XSIZE_MASK 0x1fff0000
2469 +# define TV_XSIZE_SHIFT 16
2471 + * Vertical size of the display window, measured in pixels.
2473 + * Must be even for interlaced modes.
2475 +# define TV_YSIZE_MASK 0x00000fff
2476 +# define TV_YSIZE_SHIFT 0
2478 +#define TV_FILTER_CTL_1 0x68080
2480 + * Enables automatic scaling calculation.
2482 + * If set, the rest of the registers are ignored, and the calculated values can
2483 + * be read back from the register.
2485 +# define TV_AUTO_SCALE (1 << 31)
2487 + * Disables the vertical filter.
2489 + * This is required on modes more than 1024 pixels wide */
2490 +# define TV_V_FILTER_BYPASS (1 << 29)
2491 +/** Enables adaptive vertical filtering */
2492 +# define TV_VADAPT (1 << 28)
2493 +# define TV_VADAPT_MODE_MASK (3 << 26)
2494 +/** Selects the least adaptive vertical filtering mode */
2495 +# define TV_VADAPT_MODE_LEAST (0 << 26)
2496 +/** Selects the moderately adaptive vertical filtering mode */
2497 +# define TV_VADAPT_MODE_MODERATE (1 << 26)
2498 +/** Selects the most adaptive vertical filtering mode */
2499 +# define TV_VADAPT_MODE_MOST (3 << 26)
2501 + * Sets the horizontal scaling factor.
2503 + * This should be the fractional part of the horizontal scaling factor divided
2504 + * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
2506 + * (src width - 1) / ((oversample * dest width) - 1)
2508 +# define TV_HSCALE_FRAC_MASK 0x00003fff
2509 +# define TV_HSCALE_FRAC_SHIFT 0
2511 +#define TV_FILTER_CTL_2 0x68084
2513 + * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2515 + * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
2517 +# define TV_VSCALE_INT_MASK 0x00038000
2518 +# define TV_VSCALE_INT_SHIFT 15
2520 + * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2522 + * \sa TV_VSCALE_INT_MASK
2524 +# define TV_VSCALE_FRAC_MASK 0x00007fff
2525 +# define TV_VSCALE_FRAC_SHIFT 0
2527 +#define TV_FILTER_CTL_3 0x68088
2529 + * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2531 + * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
2533 + * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2535 +# define TV_VSCALE_IP_INT_MASK 0x00038000
2536 +# define TV_VSCALE_IP_INT_SHIFT 15
2538 + * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2540 + * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2542 + * \sa TV_VSCALE_IP_INT_MASK
2544 +# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
2545 +# define TV_VSCALE_IP_FRAC_SHIFT 0
2547 +#define TV_CC_CONTROL 0x68090
2548 +# define TV_CC_ENABLE (1 << 31)
2550 + * Specifies which field to send the CC data in.
2552 + * CC data is usually sent in field 0.
2554 +# define TV_CC_FID_MASK (1 << 27)
2555 +# define TV_CC_FID_SHIFT 27
2556 +/** Sets the horizontal position of the CC data. Usually 135. */
2557 +# define TV_CC_HOFF_MASK 0x03ff0000
2558 +# define TV_CC_HOFF_SHIFT 16
2559 +/** Sets the vertical position of the CC data. Usually 21 */
2560 +# define TV_CC_LINE_MASK 0x0000003f
2561 +# define TV_CC_LINE_SHIFT 0
2563 +#define TV_CC_DATA 0x68094
2564 +# define TV_CC_RDY (1 << 31)
2565 +/** Second word of CC data to be transmitted. */
2566 +# define TV_CC_DATA_2_MASK 0x007f0000
2567 +# define TV_CC_DATA_2_SHIFT 16
2568 +/** First word of CC data to be transmitted. */
2569 +# define TV_CC_DATA_1_MASK 0x0000007f
2570 +# define TV_CC_DATA_1_SHIFT 0
2572 +#define TV_H_LUMA_0 0x68100
2573 +#define TV_H_LUMA_59 0x681ec
2574 +#define TV_H_CHROMA_0 0x68200
2575 +#define TV_H_CHROMA_59 0x682ec
2576 +#define TV_V_LUMA_0 0x68300
2577 +#define TV_V_LUMA_42 0x683a8
2578 +#define TV_V_CHROMA_0 0x68400
2579 +#define TV_V_CHROMA_42 0x684a8
2581 +/* Display & cursor control */
2584 +#define PIPEADSL 0x70000
2585 +#define PIPEACONF 0x70008
2586 +#define PIPEACONF_ENABLE (1<<31)
2587 +#define PIPEACONF_DISABLE 0
2588 +#define PIPEACONF_DOUBLE_WIDE (1<<30)
2589 +#define I965_PIPECONF_ACTIVE (1<<30)
2590 +#define PIPEACONF_SINGLE_WIDE 0
2591 +#define PIPEACONF_PIPE_UNLOCKED 0
2592 +#define PIPEACONF_PIPE_LOCKED (1<<25)
2593 +#define PIPEACONF_PALETTE 0
2594 +#define PIPEACONF_GAMMA (1<<24)
2595 +#define PIPECONF_FORCE_BORDER (1<<25)
2596 +#define PIPECONF_PROGRESSIVE (0 << 21)
2597 +#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
2598 +#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
2599 +#define PIPEASTAT 0x70024
2600 +#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
2601 +#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
2602 +#define PIPE_CRC_DONE_ENABLE (1UL<<28)
2603 +#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
2604 +#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
2605 +#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
2606 +#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
2607 +#define PIPE_DPST_EVENT_ENABLE (1UL<<23)
2608 +#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
2609 +#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
2610 +#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
2611 +#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
2612 +#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
2613 +#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
2614 +#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
2615 +#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
2616 +#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
2617 +#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
2618 +#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
2619 +#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
2620 +#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
2621 +#define PIPE_DPST_EVENT_STATUS (1UL<<7)
2622 +#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
2623 +#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
2624 +#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
2625 +#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
2626 +#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
2627 +#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
2628 +#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
2630 +#define DSPARB 0x70030
2631 +#define DSPARB_CSTART_MASK (0x7f << 7)
2632 +#define DSPARB_CSTART_SHIFT 7
2633 +#define DSPARB_BSTART_MASK (0x7f)
2634 +#define DSPARB_BSTART_SHIFT 0
2636 + * The two pipe frame counter registers are not synchronized, so
2637 + * reading a stable value is somewhat tricky. The following code
2641 + * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2642 + * PIPE_FRAME_HIGH_SHIFT;
2643 + * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
2644 + * PIPE_FRAME_LOW_SHIFT);
2645 + * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2646 + * PIPE_FRAME_HIGH_SHIFT);
2647 + * } while (high1 != high2);
2648 + * frame = (high1 << 8) | low1;
2650 +#define PIPEAFRAMEHIGH 0x70040
2651 +#define PIPE_FRAME_HIGH_MASK 0x0000ffff
2652 +#define PIPE_FRAME_HIGH_SHIFT 0
2653 +#define PIPEAFRAMEPIXEL 0x70044
2654 +#define PIPE_FRAME_LOW_MASK 0xff000000
2655 +#define PIPE_FRAME_LOW_SHIFT 24
2656 +#define PIPE_PIXEL_MASK 0x00ffffff
2657 +#define PIPE_PIXEL_SHIFT 0
2659 +/* Cursor A & B regs */
2660 +#define CURACNTR 0x70080
2661 +#define CURSOR_MODE_DISABLE 0x00
2662 +#define CURSOR_MODE_64_32B_AX 0x07
2663 +#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
2664 +#define MCURSOR_GAMMA_ENABLE (1 << 26)
2665 +#define CURABASE 0x70084
2666 +#define CURAPOS 0x70088
2667 +#define CURSOR_POS_MASK 0x007FF
2668 +#define CURSOR_POS_SIGN 0x8000
2669 +#define CURSOR_X_SHIFT 0
2670 +#define CURSOR_Y_SHIFT 16
2671 +#define CURBCNTR 0x700c0
2672 +#define CURBBASE 0x700c4
2673 +#define CURBPOS 0x700c8
2675 +/* Display A control */
2676 +#define DSPACNTR 0x70180
2677 +#define DISPLAY_PLANE_ENABLE (1<<31)
2678 +#define DISPLAY_PLANE_DISABLE 0
2679 +#define DISPPLANE_GAMMA_ENABLE (1<<30)
2680 +#define DISPPLANE_GAMMA_DISABLE 0
2681 +#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
2682 +#define DISPPLANE_8BPP (0x2<<26)
2683 +#define DISPPLANE_15_16BPP (0x4<<26)
2684 +#define DISPPLANE_16BPP (0x5<<26)
2685 +#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
2686 +#define DISPPLANE_32BPP (0x7<<26)
2687 +#define DISPPLANE_STEREO_ENABLE (1<<25)
2688 +#define DISPPLANE_STEREO_DISABLE 0
2689 +#define DISPPLANE_SEL_PIPE_MASK (1<<24)
2690 +#define DISPPLANE_SEL_PIPE_A 0
2691 +#define DISPPLANE_SEL_PIPE_B (1<<24)
2692 +#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
2693 +#define DISPPLANE_SRC_KEY_DISABLE 0
2694 +#define DISPPLANE_LINE_DOUBLE (1<<20)
2695 +#define DISPPLANE_NO_LINE_DOUBLE 0
2696 +#define DISPPLANE_STEREO_POLARITY_FIRST 0
2697 +#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
2698 +#define DSPAADDR 0x70184
2699 +#define DSPASTRIDE 0x70188
2700 +#define DSPAPOS 0x7018C /* reserved */
2701 +#define DSPASIZE 0x70190
2702 +#define DSPASURF 0x7019C /* 965+ only */
2703 +#define DSPATILEOFF 0x701A4 /* 965+ only */
2706 +#define SWF00 0x71410
2707 +#define SWF01 0x71414
2708 +#define SWF02 0x71418
2709 +#define SWF03 0x7141c
2710 +#define SWF04 0x71420
2711 +#define SWF05 0x71424
2712 +#define SWF06 0x71428
2713 +#define SWF10 0x70410
2714 +#define SWF11 0x70414
2715 +#define SWF14 0x71420
2716 +#define SWF30 0x72414
2717 +#define SWF31 0x72418
2718 +#define SWF32 0x7241c
2721 +#define PIPEBDSL 0x71000
2722 +#define PIPEBCONF 0x71008
2723 +#define PIPEBSTAT 0x71024
2724 +#define PIPEBFRAMEHIGH 0x71040
2725 +#define PIPEBFRAMEPIXEL 0x71044
2727 +/* Display B control */
2728 +#define DSPBCNTR 0x71180
2729 +#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
2730 +#define DISPPLANE_ALPHA_TRANS_DISABLE 0
2731 +#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
2732 +#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
2733 +#define DSPBADDR 0x71184
2734 +#define DSPBSTRIDE 0x71188
2735 +#define DSPBPOS 0x7118C
2736 +#define DSPBSIZE 0x71190
2737 +#define DSPBSURF 0x7119C
2738 +#define DSPBTILEOFF 0x711A4
2741 +#define VGACNTRL 0x71400
2742 +# define VGA_DISP_DISABLE (1 << 31)
2743 +# define VGA_2X_MODE (1 << 30)
2744 +# define VGA_PIPE_B_SELECT (1 << 29)
2746 +#endif /* _I915_REG_H_ */
