]> code.ossystems Code Review - openembedded-core.git/commit
qemuriscv64: Add the QEMU RISC-V 64-bit machine
authorAlistair Francis <alistair.francis@wdc.com>
Wed, 19 Jun 2019 00:55:41 +0000 (17:55 -0700)
committerRichard Purdie <richard.purdie@linuxfoundation.org>
Wed, 19 Jun 2019 12:10:27 +0000 (13:10 +0100)
commit11b6020dff4550fc3a42e04bc1e86baf37942c62
treef7b24cbd49a6ea5a721e959f8209d2846d146ee8
parent112ca2174dd97f5ca9ea25f83007d44054abc487
qemuriscv64: Add the QEMU RISC-V 64-bit machine

The include is split ready to add the 32-bit RISC-V machine as soon as
glibc supports 32-bit RISC-V.

This is based on the work in the meta-riscv layer, thanks to Khem for
starting this.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
meta/conf/machine/include/riscv/arch-riscv.inc [new file with mode: 0644]
meta/conf/machine/include/riscv/qemuriscv.inc [new file with mode: 0644]
meta/conf/machine/include/riscv/tune-riscv.inc [new file with mode: 0644]
meta/conf/machine/qemuriscv64.conf [new file with mode: 0644]