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(parent: 45108f1) | patch
iMX6: Disable the L2 before chaning the PL310 latency
authorYe.Li <Ye.Li@freescale.com>
Wed, 20 Aug 2014 09:18:24 +0000 (17:18 +0800)
committerOtavio Salvador <otavio@ossystems.com.br>
Tue, 9 Sep 2014 15:30:36 +0000 (12:30 -0300)
commit228135e8e48978045d67fe0dec042ec22d74f6a4
tree3e8da784414b49cf6e1dd0f22abb1beafdf816fctree | snapshot
parent45108f1c02d39da29748bfd84bdcf3459a5cff37commit | diff
iMX6: Disable the L2 before chaning the PL310 latency

The Latency parameters of PL310 Tag RAM latency control register and
Data RAM Latency control register are set in L2 cache enable. And
setting these registers must have PL310 NOT enabled.

But when using Plugin mode boot, the PL310 is enabled by bootrom.
The patch disables the PL310 before applying this setting.

Signed-off-by: Ye.Li <Ye.Li@freescale.com>
arch/arm/cpu/armv7/mx6/soc.c diff | blob | history
U-Boot repository with O.S. Systems patches and backports