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(parent: fe3704b) | patch
imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask
authorYe Li <ye.li@nxp.com>
Wed, 9 Mar 2016 08:13:48 +0000 (16:13 +0800)
committerOtavio Salvador <otavio@ossystems.com.br>
Fri, 1 Apr 2016 20:36:50 +0000 (17:36 -0300)
commit60b774de8ed1c9608cc01ec517078ab9c54516bb
treed31ee5b5da21923f73d20119bc783c86f653f778tree | snapshot
parentfe3704bc66b5f5b86e0ff2a55bfcd121cb98807fcommit | diff
imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask

Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register
the bit[17] for mmdc_ch0 is reserved and its proper state should be 1.
When clear this bit, the periph_clk_sel cannot be set and that
CDHIPR[periph_clk_sel_busy] handshake never clears.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
arch/arm/cpu/armv7/mx6/soc.c diff | blob | history
U-Boot repository with O.S. Systems patches and backports