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(parent: c3bed63) | patch
perf: Disable FPU tune for i.MX5 SoCs to workaround GCC ICE
authorOtavio Salvador <otavio@ossystems.com.br>
Tue, 2 Jul 2013 14:52:51 +0000 (11:52 -0300)
committerOtavio Salvador <otavio@ossystems.com.br>
Tue, 2 Jul 2013 17:49:18 +0000 (14:49 -0300)
commitd6ed1be86352edd4ff72b2ada5f0557e8436c1ae
treea33376d4d19162fc08fca0f1529c838aba25d048tree | snapshot
parentc3bed632d7cf0288c4d7af2b54cd2695623da3b9commit | diff
perf: Disable FPU tune for i.MX5 SoCs to workaround GCC ICE

GCC 4.8 currently ICE when building perf for i.MX5 SoCs and we can
workaround it disabling the FPU tunning for it. This is a temporary
solution until GCC fixes this in an upcoming release.

GCC bugzilla: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57748

Change-Id: I5a23e6b57695a90e9750f0fa28c419b260c83be2
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
meta-fsl-arm/recipes-kernel/perf/perf.bbappend [new file with mode: 0644] blob