iMX6: Disable the L2 before chaning the PL310 latency

The Latency parameters of PL310 Tag RAM latency control register and
Data RAM Latency control register are set in L2 cache enable. And
setting these registers must have PL310 NOT enabled.

But when using Plugin mode boot, the PL310 is enabled by bootrom.
The patch disables the PL310 before applying this setting.

Signed-off-by: Ye.Li <Ye.Li@freescale.com>

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index f2dee76941bc195f1cbb3f4e6a38aaebbb37a606..e9c210970b5afe1711c0939bafeb5665eb2309a2 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -424,6 +424,9 @@ void v7_outer_cache_enable(void)
        }
 #endif
 
+       /* Must disable the L2 before changing the latency parameters */
+       clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
        writel(0x132, &pl310->pl310_tag_latency_ctrl);
        writel(0x132, &pl310->pl310_data_latency_ctrl);