insane.bbclass: Fix typos in 32bit risc-v machine type

Signed-off-by: Khem Raj <raj.khem@gmail.com>
Signed-off-by: Ross Burton <ross.burton@intel.com>

diff --git a/meta/classes/insane.bbclass b/meta/classes/insane.bbclass
index 7791a867f74c5abb210cbd177247888397fd7de2..fa154608420126ec2b5fef4707dc554ad1c99534 100644 (file)
--- a/meta/classes/insane.bbclass
+++ b/meta/classes/insane.bbclass
@@ -71,7 +71,7 @@ def package_qa_get_machine_dict(d):
                         "microblaze":  (189,   0,    0,          False,         32),
                         "microblazeeb":(189,   0,    0,          False,         32),
                         "microblazeel":(189,   0,    0,          True,          32),
-                        "riscv":      (243,    0,    0,          True,          32),
+                        "riscv32":    (243,    0,    0,          True,          32),
                         "riscv64":    (243,    0,    0,          True,          64),
                       },
             "linux" : { 
@@ -99,7 +99,7 @@ def package_qa_get_machine_dict(d):
                         "mipsisa64r6":   ( 8,  0,    0,          False,         64),
                         "mipsisa64r6el": ( 8,  0,    0,          True,          64),
                         "nios2":      (113,    0,    0,          True,          32),
-                        "riscv":      (243,    0,    0,          True,          32),
+                        "riscv32":    (243,    0,    0,          True,          32),
                         "riscv64":    (243,    0,    0,          True,          64),
                         "s390":       (22,     0,    0,          False,         32),
                         "sh4":        (42,     0,    0,          True,          32),
@@ -126,7 +126,7 @@ def package_qa_get_machine_dict(d):
                         "microblaze":  (189,     0,    0,          False,         32),
                         "microblazeeb":(189,     0,    0,          False,         32),
                         "microblazeel":(189,     0,    0,          True,          32),
-                        "riscv":      (243,      0,    0,          True,          32),
+                        "riscv32":    (243,      0,    0,          True,          32),
                         "riscv64":    (243,      0,    0,          True,          64),
                         "sh4":        (  42,     0,    0,          True,          32),
                       },