]> code.ossystems Code Review - openembedded-core.git/commitdiff
insane.bbclass: add support for RISC-V baremetal
authorKhem Raj <raj.khem@gmail.com>
Wed, 14 Mar 2018 06:23:11 +0000 (23:23 -0700)
committerRichard Purdie <richard.purdie@linuxfoundation.org>
Thu, 15 Mar 2018 10:38:48 +0000 (03:38 -0700)
Signed-off-by: Khem Raj <raj.khem@gmail.com>
Signed-off-by: Ross Burton <ross.burton@intel.com>
meta/classes/insane.bbclass

index 7407b29f867a11a289aca3792a110877ccf0186b..7791a867f74c5abb210cbd177247888397fd7de2 100644 (file)
@@ -71,6 +71,8 @@ def package_qa_get_machine_dict(d):
                         "microblaze":  (189,   0,    0,          False,         32),
                         "microblazeeb":(189,   0,    0,          False,         32),
                         "microblazeel":(189,   0,    0,          True,          32),
+                        "riscv":      (243,    0,    0,          True,          32),
+                        "riscv64":    (243,    0,    0,          True,          64),
                       },
             "linux" : { 
                         "aarch64" :   (183,    0,    0,          True,          64),