Index: linux-2.6.28/include/drm/drmP.h
===================================================================
--- linux-2.6.28.orig/include/drm/drmP.h 2009-02-12 09:14:40.000000000 +0000
-+++ linux-2.6.28/include/drm/drmP.h 2009-02-12 09:14:41.000000000 +0000
++++ linux-2.6.28/include/drm/drmP.h 2009-02-12 15:59:51.000000000 +0000
@@ -57,6 +57,7 @@
#include <linux/dma-mapping.h>
#include <linux/mm.h>
/* AGP/GART support (drm_agpsupport.h) */
extern struct drm_agp_head *drm_agp_init(struct drm_device *dev);
-@@ -1303,9 +1340,6 @@
- extern int drm_sysfs_device_add(struct drm_minor *minor);
- extern void drm_sysfs_hotplug_event(struct drm_device *dev);
- extern void drm_sysfs_device_remove(struct drm_minor *minor);
--extern char *drm_get_connector_status_name(enum drm_connector_status status);
--extern int drm_sysfs_connector_add(struct drm_connector *connector);
--extern void drm_sysfs_connector_remove(struct drm_connector *connector);
-
- /*
- * Basic memory manager support (drm_mm.c)
Index: linux-2.6.28/include/drm/drm_pciids.h
===================================================================
--- linux-2.6.28.orig/include/drm/drm_pciids.h 2009-02-12 09:14:31.000000000 +0000
Index: linux-2.6.28/drivers/gpu/drm/Makefile
===================================================================
--- linux-2.6.28.orig/drivers/gpu/drm/Makefile 2009-02-12 09:14:37.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/Makefile 2009-02-12 09:14:41.000000000 +0000
-@@ -10,8 +10,11 @@
++++ linux-2.6.28/drivers/gpu/drm/Makefile 2009-02-12 16:00:51.000000000 +0000
+@@ -10,6 +10,8 @@
drm_lock.o drm_memory.o drm_proc.o drm_stub.o drm_vm.o \
drm_agpsupport.o drm_scatter.o ati_pcigart.o drm_pci.o \
drm_sysfs.o drm_hashtab.o drm_sman.o drm_mm.o \
+ drm_bo_lock.o drm_bo_move.o drm_regman.o \
drm_crtc.o drm_crtc_helper.o drm_modes.o drm_edid.o
-+
drm-$(CONFIG_COMPAT) += drm_ioc32.o
-
- obj-$(CONFIG_DRM) += drm.o
-@@ -22,6 +25,7 @@
+@@ -22,6 +24,7 @@
obj-$(CONFIG_DRM_I810) += i810/
obj-$(CONFIG_DRM_I830) += i830/
obj-$(CONFIG_DRM_I915) += i915/
+ psb_schedule.o psb_xhw.o
+
+obj-$(CONFIG_DRM_PSB) += psb.o
-Index: linux-2.6.28/drivers/gpu/drm/psb/i915_reg.h
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/psb/i915_reg.h 2009-02-12 09:14:41.000000000 +0000
-@@ -0,0 +1,67 @@
-+#include "../i915/i915_reg.h"
-+
-+
-+/*#define IS_I830(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82830_CGC)
-+#define IS_845G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82845G_IG)
-+#define IS_I85X(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82855GM_IG)
-+#define IS_I855(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82855GM_IG)
-+#define IS_I865G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82865_IG)
-+
-+#define IS_I915G(dev) (dev->pci_device == PCI_DEVICE_ID_INTEL_82915G_IG)
-+#define IS_I915GM(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82915GM_IG)
-+#define IS_I945G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82945G_IG)
-+#define IS_I945GM(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82945GM_IG)
-+
-+#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
-+ (dev)->pci_device == 0x2982 || \
-+ (dev)->pci_device == 0x2992 || \
-+ (dev)->pci_device == 0x29A2 || \
-+ (dev)->pci_device == 0x2A02 || \
-+ (dev)->pci_device == 0x2A12)
-+
-+#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
-+
-+#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
-+ (dev)->pci_device == 0x29B2 || \
-+ (dev)->pci_device == 0x29D2)
-+
-+#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
-+ IS_I945GM(dev) || IS_I965G(dev) || IS_POULSBO(dev))
-+
-+#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
-+ IS_I945GM(dev) || IS_I965GM(dev) || IS_POULSBO(dev))
-+
-+#define IS_POULSBO(dev) (((dev)->pci_device == 0x8108) || \
-+ ((dev)->pci_device == 0x8109))*/
-+
-+#define FPA0 0x06040
-+#define FPA1 0x06044
-+#define FPB0 0x06048
-+#define FPB1 0x0604c
-+#define FP_N_DIV_MASK 0x003f0000
-+#define FP_N_DIV_SHIFT 16
-+#define FP_M1_DIV_MASK 0x00003f00
-+#define FP_M1_DIV_SHIFT 8
-+#define FP_M2_DIV_MASK 0x0000003f
-+#define FP_M2_DIV_SHIFT 0
-+
-+#define DPLL_B_MD 0x06020
-+
-+#define ADPA 0x61100
-+#define ADPA_DAC_ENABLE (1<<31)
-+#define ADPA_DAC_DISABLE 0
-+#define ADPA_PIPE_SELECT_MASK (1<<30)
-+#define ADPA_PIPE_A_SELECT 0
-+#define ADPA_PIPE_B_SELECT (1<<30)
-+#define ADPA_USE_VGA_HVPOLARITY (1<<15)
-+#define ADPA_SETS_HVPOLARITY 0
-+#define ADPA_VSYNC_CNTL_DISABLE (1<<11)
-+#define ADPA_VSYNC_CNTL_ENABLE 0
-+#define ADPA_HSYNC_CNTL_DISABLE (1<<10)
-+#define ADPA_HSYNC_CNTL_ENABLE 0
-+#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
-+#define ADPA_VSYNC_ACTIVE_LOW 0
-+#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
-+#define ADPA_HSYNC_ACTIVE_LOW 0
-+
-+
-Index: linux-2.6.28/drivers/gpu/drm/psb/intel_display.c
+Index: linux-2.6.28/drivers/gpu/drm/psb/psb_buffer.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/psb/intel_display.c 2009-02-12 09:14:41.000000000 +0000
-@@ -0,0 +1,1813 @@
-+/*
-+ * Copyright © 2006-2007 Intel Corporation
++++ linux-2.6.28/drivers/gpu/drm/psb/psb_buffer.c 2009-02-12 09:14:41.000000000 +0000
+@@ -0,0 +1,437 @@
++/**************************************************************************
++ * Copyright (c) 2007, Intel Corporation.
++ * All Rights Reserved.
+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
+ *
-+ * The above copyright notice and this permission notice (including the next
-+ * paragraph) shall be included in all copies or substantial portions of the
-+ * Software.
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-+ * DEALINGS IN THE SOFTWARE.
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
-+ * Authors:
-+ * Eric Anholt <eric@anholt.net>
++ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
++ * develop this driver.
++ *
++ **************************************************************************/
++/*
++ * Authors: Thomas Hellstrom <thomas-at-tungstengraphics.com>
+ */
-+
-+#include <linux/i2c.h>
+#include "drmP.h"
-+#include "../i915/intel_drv.h"
-+#include "i915_drm.h"
-+#include "../i915/i915_drv.h"
-+
-+#include "drm_crtc_helper.h"
++#include "psb_drv.h"
++#include "psb_schedule.h"
+
-+bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
-+
-+typedef struct {
-+ /* given values */
-+ int n;
-+ int m1, m2;
-+ int p1, p2;
-+ /* derived values */
-+ int dot;
-+ int vco;
-+ int m;
-+ int p;
-+} intel_clock_t;
-+
-+typedef struct {
-+ int min, max;
-+} intel_range_t;
-+
-+typedef struct {
-+ int dot_limit;
-+ int p2_slow, p2_fast;
-+} intel_p2_t;
-+
-+#define INTEL_P2_NUM 2
-+
-+typedef struct {
-+ intel_range_t dot, vco, n, m, m1, m2, p, p1;
-+ intel_p2_t p2;
-+} intel_limit_t;
-+
-+#define I8XX_DOT_MIN 25000
-+#define I8XX_DOT_MAX 350000
-+#define I8XX_VCO_MIN 930000
-+#define I8XX_VCO_MAX 1400000
-+#define I8XX_N_MIN 3
-+#define I8XX_N_MAX 16
-+#define I8XX_M_MIN 96
-+#define I8XX_M_MAX 140
-+#define I8XX_M1_MIN 18
-+#define I8XX_M1_MAX 26
-+#define I8XX_M2_MIN 6
-+#define I8XX_M2_MAX 16
-+#define I8XX_P_MIN 4
-+#define I8XX_P_MAX 128
-+#define I8XX_P1_MIN 2
-+#define I8XX_P1_MAX 33
-+#define I8XX_P1_LVDS_MIN 1
-+#define I8XX_P1_LVDS_MAX 6
-+#define I8XX_P2_SLOW 4
-+#define I8XX_P2_FAST 2
-+#define I8XX_P2_LVDS_SLOW 14
-+#define I8XX_P2_LVDS_FAST 14 /* No fast option */
-+#define I8XX_P2_SLOW_LIMIT 165000
-+
-+#define I9XX_DOT_MIN 20000
-+#define I9XX_DOT_MAX 400000
-+#define I9XX_VCO_MIN 1400000
-+#define I9XX_VCO_MAX 2800000
-+#define I9XX_N_MIN 3
-+#define I9XX_N_MAX 8
-+#define I9XX_M_MIN 70
-+#define I9XX_M_MAX 120
-+#define I9XX_M1_MIN 10
-+#define I9XX_M1_MAX 20
-+#define I9XX_M2_MIN 5
-+#define I9XX_M2_MAX 9
-+#define I9XX_P_SDVO_DAC_MIN 5
-+#define I9XX_P_SDVO_DAC_MAX 80
-+#define I9XX_P_LVDS_MIN 7
-+#define I9XX_P_LVDS_MAX 98
-+#define I9XX_P1_MIN 1
-+#define I9XX_P1_MAX 8
-+#define I9XX_P2_SDVO_DAC_SLOW 10
-+#define I9XX_P2_SDVO_DAC_FAST 5
-+#define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
-+#define I9XX_P2_LVDS_SLOW 14
-+#define I9XX_P2_LVDS_FAST 7
-+#define I9XX_P2_LVDS_SLOW_LIMIT 112000
-+
-+#define INTEL_LIMIT_I8XX_DVO_DAC 0
-+#define INTEL_LIMIT_I8XX_LVDS 1
-+#define INTEL_LIMIT_I9XX_SDVO_DAC 2
-+#define INTEL_LIMIT_I9XX_LVDS 3
-+
-+static const intel_limit_t intel_limits[] = {
-+ { /* INTEL_LIMIT_I8XX_DVO_DAC */
-+ .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
-+ .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
-+ .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
-+ .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
-+ .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
-+ .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
-+ .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
-+ .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
-+ .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
-+ .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
-+ },
-+ { /* INTEL_LIMIT_I8XX_LVDS */
-+ .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
-+ .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
-+ .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
-+ .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
-+ .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
-+ .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
-+ .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
-+ .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
-+ .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
-+ .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
-+ },
-+ { /* INTEL_LIMIT_I9XX_SDVO_DAC */
-+ .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
-+ .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
-+ .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
-+ .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
-+ .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
-+ .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
-+ .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
-+ .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
-+ .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
-+ .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
-+ },
-+ { /* INTEL_LIMIT_I9XX_LVDS */
-+ .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
-+ .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
-+ .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
-+ .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
-+ .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
-+ .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
-+ .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
-+ .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
-+ /* The single-channel range is 25-112Mhz, and dual-channel
-+ * is 80-224Mhz. Prefer single channel as much as possible.
-+ */
-+ .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
-+ .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
-+ },
++struct drm_psb_ttm_backend {
++ struct drm_ttm_backend base;
++ struct page **pages;
++ unsigned int desired_tile_stride;
++ unsigned int hw_tile_stride;
++ int mem_type;
++ unsigned long offset;
++ unsigned long num_pages;
+};
+
-+static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
++int psb_fence_types(struct drm_buffer_object *bo, uint32_t * class,
++ uint32_t * type)
+{
-+ struct drm_device *dev = crtc->dev;
-+ const intel_limit_t *limit;
-+
-+ if (IS_I9XX(dev)) {
-+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
-+ limit = &intel_limits[INTEL_LIMIT_I9XX_LVDS];
-+ else
-+ limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
-+ } else {
-+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
-+ limit = &intel_limits[INTEL_LIMIT_I8XX_LVDS];
-+ else
-+ limit = &intel_limits[INTEL_LIMIT_I8XX_DVO_DAC];
++ switch (*class) {
++ case PSB_ENGINE_TA:
++ *type = DRM_FENCE_TYPE_EXE |
++ _PSB_FENCE_TYPE_TA_DONE | _PSB_FENCE_TYPE_RASTER_DONE;
++ if (bo->mem.mask & PSB_BO_FLAG_TA)
++ *type &= ~_PSB_FENCE_TYPE_RASTER_DONE;
++ if (bo->mem.mask & PSB_BO_FLAG_SCENE)
++ *type |= _PSB_FENCE_TYPE_SCENE_DONE;
++ if (bo->mem.mask & PSB_BO_FLAG_FEEDBACK)
++ *type |= _PSB_FENCE_TYPE_FEEDBACK;
++ break;
++ default:
++ *type = DRM_FENCE_TYPE_EXE;
+ }
-+ return limit;
++ return 0;
+}
+
-+/** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
-+
-+static void i8xx_clock(int refclk, intel_clock_t *clock)
++static inline size_t drm_size_align(size_t size)
+{
-+ clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
-+ clock->p = clock->p1 * clock->p2;
-+ clock->vco = refclk * clock->m / (clock->n + 2);
-+ clock->dot = clock->vco / clock->p;
++ size_t tmpSize = 4;
++ if (size > PAGE_SIZE)
++ return PAGE_ALIGN(size);
++ while (tmpSize < size)
++ tmpSize <<= 1;
++
++ return (size_t) tmpSize;
+}
+
-+/** Derive the pixel clock for the given refclk and divisors for 9xx chips. */
++/*
++ * Poulsbo GPU virtual space looks like this
++ * (We currently use only one MMU context).
++ *
++ * gatt_start = Start of GATT aperture in bus space.
++ * stolen_end = End of GATT populated by stolen memory in bus space.
++ * gatt_end = End of GATT
++ * twod_end = MIN(gatt_start + 256_MEM, gatt_end)
++ *
++ * 0x00000000 -> 0x10000000 Temporary mapping space for tiling- and copy operations.
++ * This space is not managed and is protected by the
++ * temp_mem mutex.
++ *
++ * 0x10000000 -> 0x20000000 DRM_PSB_MEM_KERNEL For kernel buffers.
++ *
++ * 0x20000000 -> gatt_start DRM_PSB_MEM_MMU For generic MMU-only use.
++ *
++ * gatt_start -> stolen_end DRM_BO_MEM_VRAM Pre-populated GATT pages.
++ *
++ * stolen_end -> twod_end DRM_BO_MEM_TT GATT memory usable by 2D engine.
++ *
++ * twod_end -> gatt_end DRM_BO_MEM_APER GATT memory not usable by 2D engine.
++ *
++ * gatt_end -> 0xffffffff Currently unused.
++ */
+
-+static void i9xx_clock(int refclk, intel_clock_t *clock)
++int psb_init_mem_type(struct drm_device *dev, uint32_t type,
++ struct drm_mem_type_manager *man)
+{
-+ clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
-+ clock->p = clock->p1 * clock->p2;
-+ clock->vco = refclk * clock->m / (clock->n + 2);
-+ clock->dot = clock->vco / clock->p;
-+}
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
++ struct psb_gtt *pg = dev_priv->pg;
+
-+static void intel_clock(struct drm_device *dev, int refclk,
-+ intel_clock_t *clock)
-+{
-+ if (IS_I9XX(dev))
-+ i9xx_clock (refclk, clock);
-+ else
-+ i8xx_clock (refclk, clock);
++ switch (type) {
++ case DRM_BO_MEM_LOCAL:
++ man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
++ _DRM_FLAG_MEMTYPE_CACHED;
++ man->drm_bus_maptype = 0;
++ break;
++ case DRM_PSB_MEM_KERNEL:
++ man->io_offset = 0x00000000;
++ man->io_size = 0x00000000;
++ man->io_addr = NULL;
++ man->drm_bus_maptype = _DRM_TTM;
++ man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
++ _DRM_FLAG_MEMTYPE_CSELECT | _DRM_FLAG_MEMTYPE_CMA;
++ man->gpu_offset = PSB_MEM_KERNEL_START;
++ break;
++ case DRM_PSB_MEM_MMU:
++ man->io_offset = 0x00000000;
++ man->io_size = 0x00000000;
++ man->io_addr = NULL;
++ man->drm_bus_maptype = _DRM_TTM;
++ man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
++ _DRM_FLAG_MEMTYPE_CSELECT | _DRM_FLAG_MEMTYPE_CMA;
++ man->gpu_offset = PSB_MEM_MMU_START;
++ break;
++ case DRM_PSB_MEM_PDS:
++ man->io_offset = 0x00000000;
++ man->io_size = 0x00000000;
++ man->io_addr = NULL;
++ man->drm_bus_maptype = _DRM_TTM;
++ man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
++ _DRM_FLAG_MEMTYPE_CSELECT | _DRM_FLAG_MEMTYPE_CMA;
++ man->gpu_offset = PSB_MEM_PDS_START;
++ break;
++ case DRM_PSB_MEM_RASTGEOM:
++ man->io_offset = 0x00000000;
++ man->io_size = 0x00000000;
++ man->io_addr = NULL;
++ man->drm_bus_maptype = _DRM_TTM;
++ man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
++ _DRM_FLAG_MEMTYPE_CSELECT | _DRM_FLAG_MEMTYPE_CMA;
++ man->gpu_offset = PSB_MEM_RASTGEOM_START;
++ break;
++ case DRM_BO_MEM_VRAM:
++ man->io_addr = NULL;
++ man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
++ _DRM_FLAG_MEMTYPE_FIXED | _DRM_FLAG_NEEDS_IOREMAP;
++#ifdef PSB_WORKING_HOST_MMU_ACCESS
++ man->drm_bus_maptype = _DRM_AGP;
++ man->io_offset = pg->gatt_start;
++ man->io_size = pg->gatt_pages << PAGE_SHIFT;
++#else
++ man->drm_bus_maptype = _DRM_TTM; /* Forces uncached */
++ man->io_offset = pg->stolen_base;
++ man->io_size = pg->stolen_size;
++#endif
++ man->gpu_offset = pg->gatt_start;
++ break;
++ case DRM_BO_MEM_TT: /* Mappable GATT memory */
++ man->io_offset = pg->gatt_start;
++ man->io_size = pg->gatt_pages << PAGE_SHIFT;
++ man->io_addr = NULL;
++#ifdef PSB_WORKING_HOST_MMU_ACCESS
++ man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
++ _DRM_FLAG_MEMTYPE_CSELECT | _DRM_FLAG_NEEDS_IOREMAP;
++ man->drm_bus_maptype = _DRM_AGP;
++#else
++ man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
++ _DRM_FLAG_MEMTYPE_CSELECT | _DRM_FLAG_MEMTYPE_CMA;
++ man->drm_bus_maptype = _DRM_TTM;
++#endif
++ man->gpu_offset = pg->gatt_start;
++ break;
++ case DRM_PSB_MEM_APER: /*MMU memory. Mappable. Not usable for 2D. */
++ man->io_offset = pg->gatt_start;
++ man->io_size = pg->gatt_pages << PAGE_SHIFT;
++ man->io_addr = NULL;
++#ifdef PSB_WORKING_HOST_MMU_ACCESS
++ man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
++ _DRM_FLAG_MEMTYPE_CSELECT | _DRM_FLAG_NEEDS_IOREMAP;
++ man->drm_bus_maptype = _DRM_AGP;
++#else
++ man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
++ _DRM_FLAG_MEMTYPE_CSELECT | _DRM_FLAG_MEMTYPE_CMA;
++ man->drm_bus_maptype = _DRM_TTM;
++#endif
++ man->gpu_offset = pg->gatt_start;
++ break;
++ default:
++ DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
++ return -EINVAL;
++ }
++ return 0;
+}
+
-+/**
-+ * Returns whether any output on the specified pipe is of the specified type
-+ */
-+bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
-+{
-+ struct drm_device *dev = crtc->dev;
-+ struct drm_mode_config *mode_config = &dev->mode_config;
-+ struct drm_connector *l_entry;
-+
-+ list_for_each_entry(l_entry, &mode_config->connector_list, head) {
-+ if (l_entry->encoder &&
-+ l_entry->encoder->crtc == crtc) {
-+ struct intel_output *intel_output = to_intel_output(l_entry);
-+ if (intel_output->type == type)
-+ return true;
-+ }
-+ }
-+ return false;
++uint32_t psb_evict_mask(struct drm_buffer_object * bo)
++{
++ switch (bo->mem.mem_type) {
++ case DRM_BO_MEM_VRAM:
++ return DRM_BO_FLAG_MEM_TT;
++ default:
++ return DRM_BO_FLAG_MEM_LOCAL;
++ }
+}
+
-+#define INTELPllInvalid(s) { /* ErrorF (s) */; return false; }
-+/**
-+ * Returns whether the given set of divisors are valid for a given refclk with
-+ * the given connectors.
-+ */
-+
-+static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
-+{
-+ const intel_limit_t *limit = intel_limit (crtc);
-+
-+ if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
-+ INTELPllInvalid ("p1 out of range\n");
-+ if (clock->p < limit->p.min || limit->p.max < clock->p)
-+ INTELPllInvalid ("p out of range\n");
-+ if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
-+ INTELPllInvalid ("m2 out of range\n");
-+ if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
-+ INTELPllInvalid ("m1 out of range\n");
-+ if (clock->m1 <= clock->m2)
-+ INTELPllInvalid ("m1 <= m2\n");
-+ if (clock->m < limit->m.min || limit->m.max < clock->m)
-+ INTELPllInvalid ("m out of range\n");
-+ if (clock->n < limit->n.min || limit->n.max < clock->n)
-+ INTELPllInvalid ("n out of range\n");
-+ if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
-+ INTELPllInvalid ("vco out of range\n");
-+ /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
-+ * connector, etc., rather than just a single range.
-+ */
-+ if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
-+ INTELPllInvalid ("dot out of range\n");
-+
-+ return true;
++int psb_invalidate_caches(struct drm_device *dev, uint64_t flags)
++{
++ return 0;
+}
+
-+/**
-+ * Returns a set of divisors for the desired target clock with the given
-+ * refclk, or FALSE. The returned values represent the clock equation:
-+ * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
-+ */
-+static bool intel_find_best_PLL(struct drm_crtc *crtc, int target,
-+ int refclk, intel_clock_t *best_clock)
++static int psb_move_blit(struct drm_buffer_object *bo,
++ int evict, int no_wait, struct drm_bo_mem_reg *new_mem)
+{
-+ struct drm_device *dev = crtc->dev;
-+ DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
-+ intel_clock_t clock;
-+ const intel_limit_t *limit = intel_limit(crtc);
-+ int err = target;
++ struct drm_bo_mem_reg *old_mem = &bo->mem;
++ int dir = 0;
+
-+ if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
-+ (I915_READ(LVDS) & LVDS_PORT_EN) != 0) {
-+ /*
-+ * For LVDS, if the panel is on, just rely on its current
-+ * settings for dual-channel. We haven't figured out how to
-+ * reliably set up different single/dual channel state, if we
-+ * even can.
-+ */
-+ if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
-+ LVDS_CLKB_POWER_UP)
-+ clock.p2 = limit->p2.p2_fast;
-+ else
-+ clock.p2 = limit->p2.p2_slow;
-+ } else {
-+ if (target < limit->p2.dot_limit)
-+ clock.p2 = limit->p2.p2_slow;
-+ else
-+ clock.p2 = limit->p2.p2_fast;
++ if ((old_mem->mem_type == new_mem->mem_type) &&
++ (new_mem->mm_node->start <
++ old_mem->mm_node->start + old_mem->mm_node->size)) {
++ dir = 1;
+ }
+
-+ memset (best_clock, 0, sizeof (*best_clock));
++ psb_emit_2d_copy_blit(bo->dev,
++ old_mem->mm_node->start << PAGE_SHIFT,
++ new_mem->mm_node->start << PAGE_SHIFT,
++ new_mem->num_pages, dir);
+
-+ for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
-+ for (clock.m2 = limit->m2.min; clock.m2 < clock.m1 &&
-+ clock.m2 <= limit->m2.max; clock.m2++) {
-+ for (clock.n = limit->n.min; clock.n <= limit->n.max;
-+ clock.n++) {
-+ for (clock.p1 = limit->p1.min;
-+ clock.p1 <= limit->p1.max; clock.p1++) {
-+ int this_err;
++ return drm_bo_move_accel_cleanup(bo, evict, no_wait, 0,
++ DRM_FENCE_TYPE_EXE, 0, new_mem);
++}
+
-+ intel_clock(dev, refclk, &clock);
++/*
++ * Flip destination ttm into cached-coherent GATT,
++ * then blit and subsequently move out again.
++ */
+
-+ if (!intel_PLL_is_valid(crtc, &clock))
-+ continue;
++static int psb_move_flip(struct drm_buffer_object *bo,
++ int evict, int no_wait, struct drm_bo_mem_reg *new_mem)
++{
++ struct drm_device *dev = bo->dev;
++ struct drm_bo_mem_reg tmp_mem;
++ int ret;
+
-+ this_err = abs(clock.dot - target);
-+ if (this_err < err) {
-+ *best_clock = clock;
-+ err = this_err;
-+ }
-+ }
-+ }
-+ }
-+ }
++ tmp_mem = *new_mem;
++ tmp_mem.mm_node = NULL;
++ tmp_mem.mask = DRM_BO_FLAG_MEM_TT |
++ DRM_BO_FLAG_CACHED | DRM_BO_FLAG_FORCE_CACHING;
+
-+ return (err != target);
-+}
++ ret = drm_bo_mem_space(bo, &tmp_mem, no_wait);
++ if (ret)
++ return ret;
++ ret = drm_bind_ttm(bo->ttm, &tmp_mem);
++ if (ret)
++ goto out_cleanup;
++ ret = psb_move_blit(bo, 1, no_wait, &tmp_mem);
++ if (ret)
++ goto out_cleanup;
+
-+void
-+intel_wait_for_vblank(struct drm_device *dev)
-+{
-+ /* Wait for 20ms, i.e. one cycle at 50hz. */
-+ udelay(20000);
++ ret = drm_bo_move_ttm(bo, evict, no_wait, new_mem);
++ out_cleanup:
++ if (tmp_mem.mm_node) {
++ mutex_lock(&dev->struct_mutex);
++ if (tmp_mem.mm_node != bo->pinned_node)
++ drm_mm_put_block(tmp_mem.mm_node);
++ tmp_mem.mm_node = NULL;
++ mutex_unlock(&dev->struct_mutex);
++ }
++ return ret;
+}
+
-+static void
-+intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
-+ struct drm_framebuffer *old_fb)
++int psb_move(struct drm_buffer_object *bo,
++ int evict, int no_wait, struct drm_bo_mem_reg *new_mem)
+{
-+ struct drm_device *dev = crtc->dev;
-+ DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
-+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-+ int pipe = intel_crtc->pipe;
-+ unsigned long Start, Offset;
-+ int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
-+ int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
-+ int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
-+ int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
-+ u32 dspcntr, alignment;
-+
-+ Start = crtc->fb->offset;
-+ Offset = y * crtc->fb->pitch + x;
++ struct drm_bo_mem_reg *old_mem = &bo->mem;
+
-+ DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
-+ if (IS_I965G(dev)) {
-+ I915_WRITE(dspbase, Offset);
-+ I915_READ(dspbase);
-+ I915_WRITE(dspsurf, Start);
-+ I915_READ(dspsurf);
++ if (old_mem->mem_type == DRM_BO_MEM_LOCAL) {
++ return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
++ } else if (new_mem->mem_type == DRM_BO_MEM_LOCAL) {
++ if (psb_move_flip(bo, evict, no_wait, new_mem))
++ return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
+ } else {
-+ I915_WRITE(dspbase, Start + Offset);
-+ I915_READ(dspbase);
++ if (psb_move_blit(bo, evict, no_wait, new_mem))
++ return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
+ }
++ return 0;
++}
+
-+
-+ if (!dev_priv->sarea_priv)
-+ return;
-+
-+ switch (pipe) {
-+ case 0:
-+ dev_priv->sarea_priv->pipeA_x = x;
-+ dev_priv->sarea_priv->pipeA_y = y;
-+ break;
-+ case 1:
-+ dev_priv->sarea_priv->pipeB_x = x;
-+ dev_priv->sarea_priv->pipeB_y = y;
-+ break;
-+ default:
-+ DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
-+ break;
-+ }
++static int drm_psb_tbe_nca(struct drm_ttm_backend *backend)
++{
++ return ((backend->flags & DRM_BE_FLAG_BOUND_CACHED) ? 0 : 1);
+}
+
++static int drm_psb_tbe_populate(struct drm_ttm_backend *backend,
++ unsigned long num_pages, struct page **pages)
++{
++ struct drm_psb_ttm_backend *psb_be =
++ container_of(backend, struct drm_psb_ttm_backend, base);
+
++ psb_be->pages = pages;
++ return 0;
++}
+
-+/**
-+ * Sets the power management mode of the pipe and plane.
-+ *
-+ * This code should probably grow support for turning the cursor off and back
-+ * on appropriately at the same time as we're turning the pipe off/on.
-+ */
-+static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
++static int drm_psb_tbe_unbind(struct drm_ttm_backend *backend)
+{
-+ struct drm_device *dev = crtc->dev;
-+ DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
-+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-+ int pipe = intel_crtc->pipe;
-+ int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
-+ int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
-+ int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR;
-+ int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
-+ u32 temp;
-+ bool enabled;
++ struct drm_device *dev = backend->dev;
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
++ struct drm_psb_ttm_backend *psb_be =
++ container_of(backend, struct drm_psb_ttm_backend, base);
++ struct psb_mmu_pd *pd = psb_mmu_get_default_pd(dev_priv->mmu);
++ struct drm_mem_type_manager *man = &dev->bm.man[psb_be->mem_type];
+
-+ /* XXX: When our outputs are all unaware of DPMS modes other than off
-+ * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
-+ */
-+ switch (mode) {
-+ case DRM_MODE_DPMS_ON:
-+ case DRM_MODE_DPMS_STANDBY:
-+ case DRM_MODE_DPMS_SUSPEND:
-+ /* Enable the DPLL */
-+ temp = I915_READ(dpll_reg);
-+ if ((temp & DPLL_VCO_ENABLE) == 0) {
-+ I915_WRITE(dpll_reg, temp);
-+ I915_READ(dpll_reg);
-+ /* Wait for the clocks to stabilize. */
-+ udelay(150);
-+ I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
-+ I915_READ(dpll_reg);
-+ /* Wait for the clocks to stabilize. */
-+ udelay(150);
-+ I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
-+ I915_READ(dpll_reg);
-+ /* Wait for the clocks to stabilize. */
-+ udelay(150);
-+ }
++ PSB_DEBUG_RENDER("MMU unbind.\n");
+
-+ /* Enable the pipe */
-+ temp = I915_READ(pipeconf_reg);
-+ if ((temp & PIPEACONF_ENABLE) == 0)
-+ I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
-+
-+ /* Enable the plane */
-+ temp = I915_READ(dspcntr_reg);
-+ if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
-+ I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
-+ /* Flush the plane changes */
-+ I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
-+ }
++ if (psb_be->mem_type == DRM_BO_MEM_TT) {
++ uint32_t gatt_p_offset = (psb_be->offset - man->gpu_offset) >>
++ PAGE_SHIFT;
+
-+ intel_crtc_load_lut(crtc);
-+
-+ /* Give the overlay scaler a chance to enable if it's on this pipe */
-+ //intel_crtc_dpms_video(crtc, true); TODO
-+ break;
-+ case DRM_MODE_DPMS_OFF:
-+ /* Give the overlay scaler a chance to disable if it's on this pipe */
-+ //intel_crtc_dpms_video(crtc, FALSE); TODO
-+
-+ /* Disable the VGA plane that we never use */
-+ I915_WRITE(VGACNTRL, VGA_DISP_DISABLE);
-+
-+ /* Disable display plane */
-+ temp = I915_READ(dspcntr_reg);
-+ if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
-+ I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
-+ /* Flush the plane changes */
-+ I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
-+ I915_READ(dspbase_reg);
-+ }
++ (void)psb_gtt_remove_pages(dev_priv->pg, gatt_p_offset,
++ psb_be->num_pages,
++ psb_be->desired_tile_stride,
++ psb_be->hw_tile_stride);
++ }
+
-+ if (!IS_I9XX(dev)) {
-+ /* Wait for vblank for the disable to take effect */
-+ intel_wait_for_vblank(dev);
-+ }
++ psb_mmu_remove_pages(pd, psb_be->offset,
++ psb_be->num_pages,
++ psb_be->desired_tile_stride,
++ psb_be->hw_tile_stride);
+
-+ /* Next, disable display pipes */
-+ temp = I915_READ(pipeconf_reg);
-+ if ((temp & PIPEACONF_ENABLE) != 0) {
-+ I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
-+ I915_READ(pipeconf_reg);
-+ }
++ return 0;
++}
+
-+ /* Wait for vblank for the disable to take effect. */
-+ intel_wait_for_vblank(dev);
++static int drm_psb_tbe_bind(struct drm_ttm_backend *backend,
++ struct drm_bo_mem_reg *bo_mem)
++{
++ struct drm_device *dev = backend->dev;
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
++ struct drm_psb_ttm_backend *psb_be =
++ container_of(backend, struct drm_psb_ttm_backend, base);
++ struct psb_mmu_pd *pd = psb_mmu_get_default_pd(dev_priv->mmu);
++ struct drm_mem_type_manager *man = &dev->bm.man[bo_mem->mem_type];
++ int type;
++ int ret = 0;
+
-+ temp = I915_READ(dpll_reg);
-+ if ((temp & DPLL_VCO_ENABLE) != 0) {
-+ I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
-+ I915_READ(dpll_reg);
-+ }
++ psb_be->mem_type = bo_mem->mem_type;
++ psb_be->num_pages = bo_mem->num_pages;
++ psb_be->desired_tile_stride = bo_mem->desired_tile_stride;
++ psb_be->hw_tile_stride = bo_mem->hw_tile_stride;
++ psb_be->desired_tile_stride = 0;
++ psb_be->hw_tile_stride = 0;
++ psb_be->offset = (bo_mem->mm_node->start << PAGE_SHIFT) +
++ man->gpu_offset;
+
-+ /* Wait for the clocks to turn off. */
-+ udelay(150);
-+ break;
-+ }
++ type = (bo_mem->flags & DRM_BO_FLAG_CACHED) ? PSB_MMU_CACHED_MEMORY : 0;
+
++ PSB_DEBUG_RENDER("MMU bind.\n");
++ if (psb_be->mem_type == DRM_BO_MEM_TT) {
++ uint32_t gatt_p_offset = (psb_be->offset - man->gpu_offset) >>
++ PAGE_SHIFT;
+
-+ if (!dev_priv->sarea_priv)
-+ return;
++ ret = psb_gtt_insert_pages(dev_priv->pg, psb_be->pages,
++ gatt_p_offset,
++ psb_be->num_pages,
++ psb_be->desired_tile_stride,
++ psb_be->hw_tile_stride, type);
++ }
+
-+ enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
++ ret = psb_mmu_insert_pages(pd, psb_be->pages,
++ psb_be->offset, psb_be->num_pages,
++ psb_be->desired_tile_stride,
++ psb_be->hw_tile_stride, type);
++ if (ret)
++ goto out_err;
+
-+ switch (pipe) {
-+ case 0:
-+ dev_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
-+ dev_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
-+ break;
-+ case 1:
-+ dev_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
-+ dev_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
-+ break;
-+ default:
-+ DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
-+ break;
-+ }
++ DRM_FLAG_MASKED(backend->flags, (bo_mem->flags & DRM_BO_FLAG_CACHED) ?
++ DRM_BE_FLAG_BOUND_CACHED : 0, DRM_BE_FLAG_BOUND_CACHED);
+
-+ intel_crtc->dpms_mode = mode;
-+}
++ return 0;
++ out_err:
++ drm_psb_tbe_unbind(backend);
++ return ret;
+
-+static void intel_crtc_prepare (struct drm_crtc *crtc)
-+{
-+ struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
-+ crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
+}
+
-+static void intel_crtc_commit (struct drm_crtc *crtc)
++static void drm_psb_tbe_clear(struct drm_ttm_backend *backend)
+{
-+ struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
-+ crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
-+}
++ struct drm_psb_ttm_backend *psb_be =
++ container_of(backend, struct drm_psb_ttm_backend, base);
+
-+void intel_encoder_prepare (struct drm_encoder *encoder)
-+{
-+ struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
-+ /* lvds has its own version of prepare see intel_lvds_prepare */
-+ encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
++ psb_be->pages = NULL;
++ return;
+}
+
-+void intel_encoder_commit (struct drm_encoder *encoder)
++static void drm_psb_tbe_destroy(struct drm_ttm_backend *backend)
+{
-+ struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
-+ /* lvds has its own version of commit see intel_lvds_commit */
-+ encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
-+}
++ struct drm_psb_ttm_backend *psb_be =
++ container_of(backend, struct drm_psb_ttm_backend, base);
+
-+static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
-+ struct drm_display_mode *mode,
-+ struct drm_display_mode *adjusted_mode)
-+{
-+ return true;
++ if (backend)
++ drm_free(psb_be, sizeof(*psb_be), DRM_MEM_TTM);
+}
+
++static struct drm_ttm_backend_func psb_ttm_backend = {
++ .needs_ub_cache_adjust = drm_psb_tbe_nca,
++ .populate = drm_psb_tbe_populate,
++ .clear = drm_psb_tbe_clear,
++ .bind = drm_psb_tbe_bind,
++ .unbind = drm_psb_tbe_unbind,
++ .destroy = drm_psb_tbe_destroy,
++};
+
-+/** Returns the core display clock speed for i830 - i945 */
-+static int intel_get_core_clock_speed(struct drm_device *dev)
++struct drm_ttm_backend *drm_psb_tbe_init(struct drm_device *dev)
+{
++ struct drm_psb_ttm_backend *psb_be;
+
-+ /* Core clock values taken from the published datasheets.
-+ * The 830 may go up to 166 Mhz, which we should check.
-+ */
-+ if (IS_I945G(dev))
-+ return 400000;
-+ else if (IS_I915G(dev))
-+ return 333000;
-+ else if (IS_I945GM(dev) || IS_POULSBO(dev) || IS_845G(dev))
-+ return 200000;
-+ else if (IS_I915GM(dev)) {
-+ u16 gcfgc = 0;
-+
-+ pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
-+
-+ if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
-+ return 133000;
-+ else {
-+ switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
-+ case GC_DISPLAY_CLOCK_333_MHZ:
-+ return 333000;
-+ default:
-+ case GC_DISPLAY_CLOCK_190_200_MHZ:
-+ return 190000;
-+ }
-+ }
-+ } else if (IS_I865G(dev))
-+ return 266000;
-+ else if (IS_I855(dev)) {
-+ u16 hpllcc = 0;
-+ /* Assume that the hardware is in the high speed state. This
-+ * should be the default.
-+ */
-+ switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
-+ case GC_CLOCK_133_200:
-+ case GC_CLOCK_100_200:
-+ return 200000;
-+ case GC_CLOCK_166_250:
-+ return 250000;
-+ case GC_CLOCK_100_133:
-+ return 133000;
-+ }
-+ } else /* 852, 830 */
-+ return 133000;
++ psb_be = drm_calloc(1, sizeof(*psb_be), DRM_MEM_TTM);
++ if (!psb_be)
++ return NULL;
++ psb_be->pages = NULL;
++ psb_be->base.func = &psb_ttm_backend;
++ psb_be->base.dev = dev;
+
-+ return 0; /* Silence gcc warning */
++ return &psb_be->base;
+}
+
-+
-+/**
-+ * Return the pipe currently connected to the panel fitter,
-+ * or -1 if the panel fitter is not present or not in use
-+ */
-+static int intel_panel_fitter_pipe (struct drm_device *dev)
++int psb_tbe_size(struct drm_device *dev, unsigned long num_pages)
+{
-+ DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
-+ u32 pfit_control;
-+
-+ /* i830 doesn't have a panel fitter */
-+ if (IS_I830(dev))
-+ return -1;
-+
-+ pfit_control = I915_READ(PFIT_CONTROL);
++ /*
++ * Return the size of the structures themselves and the
++ * estimated size of the pagedir and pagetable entries.
++ */
+
-+ /* See if the panel fitter is in use */
-+ if ((pfit_control & PFIT_ENABLE) == 0)
-+ return -1;
-+
-+ /* 965 can place panel fitter on either pipe */
-+ if (IS_I965G(dev))
-+ return (pfit_control >> 29) & 0x3;
-+
-+ /* older chips can only use pipe 1 */
-+ return 1;
++ return drm_size_align(sizeof(struct drm_psb_ttm_backend)) +
++ 8*num_pages;
+}
+Index: linux-2.6.28/drivers/gpu/drm/psb/psb_drm.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.28/drivers/gpu/drm/psb/psb_drm.h 2009-02-12 09:14:41.000000000 +0000
+@@ -0,0 +1,370 @@
++/**************************************************************************
++ * Copyright (c) 2007, Intel Corporation.
++ * All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
++ *
++ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
++ * develop this driver.
++ *
++ **************************************************************************/
++/*
++ */
+
-+#define WA_NO_FB_GARBAGE_DISPLAY
-+#ifdef WA_NO_FB_GARBAGE_DISPLAY
-+static u32 fp_reg_value[2];
-+static u32 dpll_reg_value[2];
-+static u32 dpll_md_reg_value[2];
-+static u32 dspcntr_reg_value[2];
-+static u32 pipeconf_reg_value[2];
-+static u32 htot_reg_value[2];
-+static u32 hblank_reg_value[2];
-+static u32 hsync_reg_value[2];
-+static u32 vtot_reg_value[2];
-+static u32 vblank_reg_value[2];
-+static u32 vsync_reg_value[2];
-+static u32 dspsize_reg_value[2];
-+static u32 dspstride_reg_value[2];
-+static u32 dsppos_reg_value[2];
-+static u32 pipesrc_reg_value[2];
++#ifndef _PSB_DRM_H_
++#define _PSB_DRM_H_
+
-+static u32 dspbase_value[2];
++#if defined(__linux__) && !defined(__KERNEL__)
++#include<stdint.h>
++#endif
+
-+static u32 lvds_reg_value[2];
-+static u32 vgacntrl_reg_value[2];
-+static u32 pfit_control_reg_value[2];
++/*
++ * Intel Poulsbo driver package version.
++ *
++ */
++/* #define PSB_PACKAGE_VERSION "ED"__DATE__*/
++#define PSB_PACKAGE_VERSION "2.1.0.32L.0019"
+
-+#if 0
-+void intel_crtc_mode_restore(struct drm_crtc *crtc)
-+{
-+ struct drm_device *dev = crtc->dev;
-+ DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
-+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-+ int pipe = intel_crtc->pipe;
-+ int fp_reg = (pipe == 0) ? FPA0 : FPB0;
-+ int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
-+ int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
-+ int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
-+ int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
-+ int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
-+ int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
-+ int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
-+ int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
-+ int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
-+ int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
-+ int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
-+ int dspstride_reg = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
-+ int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
-+ int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
-+ int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
++#define DRM_PSB_SAREA_MAJOR 0
++#define DRM_PSB_SAREA_MINOR 1
++#define PSB_FIXED_SHIFT 16
+
-+ bool ok, is_sdvo = false, is_dvo = false;
-+ bool is_crt = false, is_lvds = false, is_tv = false;
-+ struct drm_mode_config *mode_config = &dev->mode_config;
-+ struct drm_connector *output;
++/*
++ * Public memory types.
++ */
+
-+ list_for_each_entry(output, &mode_config->connector_list, head) {
-+ struct intel_output *intel_output = to_intel_output(crtc);
++#define DRM_PSB_MEM_MMU DRM_BO_MEM_PRIV1
++#define DRM_PSB_FLAG_MEM_MMU DRM_BO_FLAG_MEM_PRIV1
++#define DRM_PSB_MEM_PDS DRM_BO_MEM_PRIV2
++#define DRM_PSB_FLAG_MEM_PDS DRM_BO_FLAG_MEM_PRIV2
++#define DRM_PSB_MEM_APER DRM_BO_MEM_PRIV3
++#define DRM_PSB_FLAG_MEM_APER DRM_BO_FLAG_MEM_PRIV3
++#define DRM_PSB_MEM_RASTGEOM DRM_BO_MEM_PRIV4
++#define DRM_PSB_FLAG_MEM_RASTGEOM DRM_BO_FLAG_MEM_PRIV4
++#define PSB_MEM_RASTGEOM_START 0x30000000
+
-+ if (output->crtc != crtc)
-+ continue;
++typedef int32_t psb_fixed;
++typedef uint32_t psb_ufixed;
+
-+ switch (intel_output->type) {
-+ case INTEL_OUTPUT_LVDS:
-+ is_lvds = TRUE;
-+ break;
-+ case INTEL_OUTPUT_SDVO:
-+ is_sdvo = TRUE;
-+ break;
-+ case INTEL_OUTPUT_DVO:
-+ is_dvo = TRUE;
-+ break;
-+ case INTEL_OUTPUT_TVOUT:
-+ is_tv = TRUE;
-+ break;
-+ case INTEL_OUTPUT_ANALOG:
-+ is_crt = TRUE;
-+ break;
-+ }
-+ if(is_lvds && ((lvds_reg_value[pipe] & LVDS_PORT_EN) == 0))
-+ {
-+ printk("%s: is_lvds but not the boot display, so return\n",
-+ __FUNCTION__);
-+ return;
-+ }
-+ output->funcs->prepare(output);
-+ }
++static inline psb_fixed psb_int_to_fixed(int a)
++{
++ return a * (1 << PSB_FIXED_SHIFT);
++}
+
-+ intel_crtc_prepare(crtc);
-+ /* Disable the panel fitter if it was on our pipe */
-+ if (intel_panel_fitter_pipe(dev) == pipe)
-+ I915_WRITE(PFIT_CONTROL, 0);
++static inline psb_ufixed psb_unsigned_to_ufixed(unsigned int a)
++{
++ return a << PSB_FIXED_SHIFT;
++}
+
-+ if (dpll_reg_value[pipe] & DPLL_VCO_ENABLE) {
-+ I915_WRITE(fp_reg, fp_reg_value[pipe]);
-+ I915_WRITE(dpll_reg, dpll_reg_value[pipe]& ~DPLL_VCO_ENABLE);
-+ I915_READ(dpll_reg);
-+ udelay(150);
-+ }
++/*Status of the command sent to the gfx device.*/
++typedef enum {
++ DRM_CMD_SUCCESS,
++ DRM_CMD_FAILED,
++ DRM_CMD_HANG
++} drm_cmd_status_t;
+
-+ /*
-+ if(is_lvds)
-+ I915_WRITE(LVDS, lvds_reg_value[pipe]);
-+ */
-+ if (is_lvds) {
-+ I915_WRITE(LVDS, lvds_reg_value[pipe]);
-+ I915_READ(LVDS);
-+ }
++struct drm_psb_scanout {
++ uint32_t buffer_id; /* DRM buffer object ID */
++ uint32_t rotation; /* Rotation as in RR_rotation definitions */
++ uint32_t stride; /* Buffer stride in bytes */
++ uint32_t depth; /* Buffer depth in bits (NOT) bpp */
++ uint32_t width; /* Buffer width in pixels */
++ uint32_t height; /* Buffer height in lines */
++ psb_fixed transform[3][3]; /* Buffer composite transform */
++ /* (scaling, rot, reflect) */
++};
+
-+ I915_WRITE(fp_reg, fp_reg_value[pipe]);
-+ I915_WRITE(dpll_reg, dpll_reg_value[pipe]);
-+ I915_READ(dpll_reg);
-+ udelay(150);
-+ //I915_WRITE(dpll_md_reg, dpll_md_reg_value[pipe]);
-+ I915_WRITE(dpll_reg, dpll_reg_value[pipe]);
-+ I915_READ(dpll_reg);
-+ udelay(150);
-+ I915_WRITE(htot_reg, htot_reg_value[pipe]);
-+ I915_WRITE(hblank_reg, hblank_reg_value[pipe]);
-+ I915_WRITE(hsync_reg, hsync_reg_value[pipe]);
-+ I915_WRITE(vtot_reg, vtot_reg_value[pipe]);
-+ I915_WRITE(vblank_reg, vblank_reg_value[pipe]);
-+ I915_WRITE(vsync_reg, vsync_reg_value[pipe]);
-+ I915_WRITE(dspstride_reg, dspstride_reg_value[pipe]);
-+ I915_WRITE(dspsize_reg, dspsize_reg_value[pipe]);
-+ I915_WRITE(dsppos_reg, dsppos_reg_value[pipe]);
-+ I915_WRITE(pipesrc_reg, pipesrc_reg_value[pipe]);
-+ I915_WRITE(pipeconf_reg, pipeconf_reg_value[pipe]);
-+ I915_READ(pipeconf_reg);
-+ intel_wait_for_vblank(dev);
-+ I915_WRITE(dspcntr_reg, dspcntr_reg_value[pipe]);
-+ I915_WRITE(dspbase, dspbase_value[pipe]);
-+ I915_READ(dspbase);
-+ I915_WRITE(VGACNTRL, vgacntrl_reg_value[pipe]);
-+ intel_wait_for_vblank(dev);
-+ I915_WRITE(PFIT_CONTROL, pfit_control_reg_value[pipe]);
++#define DRM_PSB_SAREA_OWNERS 16
++#define DRM_PSB_SAREA_OWNER_2D 0
++#define DRM_PSB_SAREA_OWNER_3D 1
+
-+ intel_crtc_commit(crtc);
-+ list_for_each_entry(output, &mode_config->connector_list, head) {
-+ if (output->crtc != crtc)
-+ continue;
++#define DRM_PSB_SAREA_SCANOUTS 3
+
-+ output->funcs->commit(output);
-+ //output->funcs->dpms(output, DRM_MODE_DPMS_OFF);
-+ //printk("turn off the display first\n");
-+ }
-+ return;
-+}
++struct drm_psb_sarea {
++ /* Track changes of this data structure */
+
-+void intel_crtc_mode_save(struct drm_crtc *crtc)
-+{
-+ struct drm_device *dev = crtc->dev;
-+ DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
-+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-+ int pipe = intel_crtc->pipe;
-+ int fp_reg = (pipe == 0) ? FPA0 : FPB0;
-+ int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
-+ int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
-+ int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
-+ int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
-+ int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
-+ int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
-+ int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
-+ int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
-+ int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
-+ int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
-+ int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
-+ int dspstride_reg = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
-+ int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
-+ int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
-+ int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
-+ bool ok, is_sdvo = false, is_dvo = false;
-+ bool is_crt = false, is_lvds = false, is_tv = false;
-+ struct drm_mode_config *mode_config = &dev->mode_config;
-+ struct drm_connector *output;
++ uint32_t major;
++ uint32_t minor;
+
-+ list_for_each_entry(output, &mode_config->connector_list, head) {
-+ struct intel_output *intel_output = to_intel_output(crtc);
++ /* Last context to touch part of hw */
++ uint32_t ctx_owners[DRM_PSB_SAREA_OWNERS];
+
-+ if (output->crtc != crtc)
-+ continue;
-+
-+ switch (intel_output->type) {
-+ case INTEL_OUTPUT_LVDS:
-+ is_lvds = TRUE;
-+ break;
-+ case INTEL_OUTPUT_SDVO:
-+ is_sdvo = TRUE;
-+ break;
-+ case INTEL_OUTPUT_DVO:
-+ is_dvo = TRUE;
-+ break;
-+ case INTEL_OUTPUT_TVOUT:
-+ is_tv = TRUE;
-+ break;
-+ case INTEL_OUTPUT_ANALOG:
-+ is_crt = TRUE;
-+ break;
-+ }
-+ }
-+
-+ fp_reg_value[pipe] = I915_READ(fp_reg);
-+ dpll_reg_value[pipe] = I915_READ(dpll_reg);
-+ dpll_md_reg_value[pipe] = I915_READ(dpll_md_reg);
-+ dspcntr_reg_value[pipe] = I915_READ(dspcntr_reg);
-+ pipeconf_reg_value[pipe] = I915_READ(pipeconf_reg);
-+ htot_reg_value[pipe] = I915_READ(htot_reg);
-+ hblank_reg_value[pipe] = I915_READ(hblank_reg);
-+ hsync_reg_value[pipe] = I915_READ(hsync_reg);
-+ vtot_reg_value[pipe] = I915_READ(vtot_reg);
-+ vblank_reg_value[pipe] = I915_READ(vblank_reg);
-+ vsync_reg_value[pipe] = I915_READ(vsync_reg);
-+ dspsize_reg_value[pipe] = I915_READ(dspsize_reg);
-+ dspstride_reg_value[pipe] = I915_READ(dspstride_reg);
-+ dsppos_reg_value[pipe] = I915_READ(dsppos_reg);
-+ pipesrc_reg_value[pipe] = I915_READ(pipesrc_reg);
-+ dspbase_value[pipe] = I915_READ(dspbase);
-+ if(is_lvds)
-+ lvds_reg_value[pipe] = I915_READ(LVDS);
-+ vgacntrl_reg_value[pipe] = I915_READ(VGACNTRL);
-+ pfit_control_reg_value[pipe] = I915_READ(PFIT_CONTROL);
-+}
-+#endif
-+#endif
-+static void intel_crtc_mode_set(struct drm_crtc *crtc,
-+ struct drm_display_mode *mode,
-+ struct drm_display_mode *adjusted_mode,
-+ int x, int y,
-+ struct drm_framebuffer *old_fb)
-+{
-+ struct drm_device *dev = crtc->dev;
-+ DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
-+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-+ int pipe = intel_crtc->pipe;
-+ int fp_reg = (pipe == 0) ? FPA0 : FPB0;
-+ int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
-+ int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
-+ int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
-+ int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
-+ int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
-+ int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
-+ int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
-+ int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
-+ int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
-+ int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
-+ int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
-+ int dspstride_reg = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
-+ int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
-+ int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
-+ int refclk;
-+ intel_clock_t clock;
-+ u32 dpll = 0, fp = 0, dspcntr, pipeconf;
-+ bool ok, is_sdvo = false, is_dvo = false;
-+ bool is_crt = false, is_lvds = false, is_tv = false;
-+ struct drm_mode_config *mode_config = &dev->mode_config;
-+ struct drm_connector *connector;
-+
-+ if (!crtc->fb) {
-+ DRM_ERROR("Can't set mode without attached fb\n");
-+ return;
-+ }
++ /* Definition of front- and rotated buffers */
++ uint32_t num_scanouts;
++ struct drm_psb_scanout scanouts[DRM_PSB_SAREA_SCANOUTS];
+
-+ list_for_each_entry(connector, &mode_config->connector_list, head) {
-+ struct intel_output *intel_output = to_intel_output(connector);
++ int pipeA_x;
++ int pipeA_y;
++ int pipeA_w;
++ int pipeA_h;
++ int pipeB_x;
++ int pipeB_y;
++ int pipeB_w;
++ int pipeB_h;
++ uint32_t msvdx_state;
++ uint32_t msvdx_context;
++};
+
-+ if (!connector->encoder || connector->encoder->crtc != crtc)
-+ continue;
++#define PSB_RELOC_MAGIC 0x67676767
++#define PSB_RELOC_SHIFT_MASK 0x0000FFFF
++#define PSB_RELOC_SHIFT_SHIFT 0
++#define PSB_RELOC_ALSHIFT_MASK 0xFFFF0000
++#define PSB_RELOC_ALSHIFT_SHIFT 16
+
-+ switch (intel_output->type) {
-+ case INTEL_OUTPUT_LVDS:
-+ is_lvds = true;
-+ break;
-+ case INTEL_OUTPUT_SDVO:
-+ case INTEL_OUTPUT_HDMI:
-+ is_sdvo = true;
-+ break;
-+ case INTEL_OUTPUT_DVO:
-+ is_dvo = true;
-+ break;
-+ case INTEL_OUTPUT_TVOUT:
-+ is_tv = true;
-+ break;
-+ case INTEL_OUTPUT_ANALOG:
-+ is_crt = true;
-+ break;
-+ }
-+ }
++#define PSB_RELOC_OP_OFFSET 0 /* Offset of the indicated
++ * buffer
++ */
++#define PSB_RELOC_OP_2D_OFFSET 1 /* Offset of the indicated
++ * buffer, relative to 2D
++ * base address
++ */
++#define PSB_RELOC_OP_PDS_OFFSET 2 /* Offset of the indicated buffer,
++ * relative to PDS base address
++ */
++#define PSB_RELOC_OP_STRIDE 3 /* Stride of the indicated
++ * buffer (for tiling)
++ */
++#define PSB_RELOC_OP_USE_OFFSET 4 /* Offset of USE buffer
++ * relative to base reg
++ */
++#define PSB_RELOC_OP_USE_REG 5 /* Base reg of USE buffer */
+
-+ if (IS_I9XX(dev)) {
-+ refclk = 96000;
-+ } else {
-+ refclk = 48000;
-+ }
++struct drm_psb_reloc {
++ uint32_t reloc_op;
++ uint32_t where; /* offset in destination buffer */
++ uint32_t buffer; /* Buffer reloc applies to */
++ uint32_t mask; /* Destination format: */
++ uint32_t shift; /* Destination format: */
++ uint32_t pre_add; /* Destination format: */
++ uint32_t background; /* Destination add */
++ uint32_t dst_buffer; /* Destination buffer. Index into buffer_list */
++ uint32_t arg0; /* Reloc-op dependant */
++ uint32_t arg1;
++};
+
-+ ok = intel_find_best_PLL(crtc, adjusted_mode->clock, refclk, &clock);
-+ if (!ok) {
-+ DRM_ERROR("Couldn't find PLL settings for mode!\n");
-+ return;
-+ }
++#define PSB_BO_FLAG_TA (1ULL << 48)
++#define PSB_BO_FLAG_SCENE (1ULL << 49)
++#define PSB_BO_FLAG_FEEDBACK (1ULL << 50)
++#define PSB_BO_FLAG_USSE (1ULL << 51)
+
-+ fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
++#define PSB_ENGINE_2D 0
++#define PSB_ENGINE_VIDEO 1
++#define PSB_ENGINE_RASTERIZER 2
++#define PSB_ENGINE_TA 3
++#define PSB_ENGINE_HPRAST 4
+
-+ dpll = DPLL_VGA_MODE_DIS;
-+ if (IS_I9XX(dev)) {
-+ if (is_lvds) {
-+ dpll |= DPLLB_MODE_LVDS;
-+ if (IS_POULSBO(dev))
-+ dpll |= DPLL_DVO_HIGH_SPEED;
-+ } else
-+ dpll |= DPLLB_MODE_DAC_SERIAL;
-+ if (is_sdvo) {
-+ dpll |= DPLL_DVO_HIGH_SPEED;
-+ if (IS_I945G(dev) || IS_I945GM(dev) || IS_POULSBO(dev)) {
-+ int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
-+ dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
-+ }
-+ }
++/*
++ * For this fence class we have a couple of
++ * fence types.
++ */
+
-+ /* compute bitmask from p1 value */
-+ dpll |= (1 << (clock.p1 - 1)) << 16;
-+ switch (clock.p2) {
-+ case 5:
-+ dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
-+ break;
-+ case 7:
-+ dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
-+ break;
-+ case 10:
-+ dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
-+ break;
-+ case 14:
-+ dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
-+ break;
-+ }
-+ if (IS_I965G(dev))
-+ dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
-+ } else {
-+ if (is_lvds) {
-+ dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
-+ } else {
-+ if (clock.p1 == 2)
-+ dpll |= PLL_P1_DIVIDE_BY_TWO;
-+ else
-+ dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
-+ if (clock.p2 == 4)
-+ dpll |= PLL_P2_DIVIDE_BY_4;
-+ }
-+ }
++#define _PSB_FENCE_EXE_SHIFT 0
++#define _PSB_FENCE_TA_DONE_SHIFT 1
++#define _PSB_FENCE_RASTER_DONE_SHIFT 2
++#define _PSB_FENCE_SCENE_DONE_SHIFT 3
++#define _PSB_FENCE_FEEDBACK_SHIFT 4
+
-+ if (is_tv) {
-+ /* XXX: just matching BIOS for now */
-+/* dpll |= PLL_REF_INPUT_TVCLKINBC; */
-+ dpll |= 3;
-+ }
-+ else
-+ dpll |= PLL_REF_INPUT_DREFCLK;
++#define _PSB_ENGINE_TA_FENCE_TYPES 5
++#define _PSB_FENCE_TYPE_TA_DONE (1 << _PSB_FENCE_TA_DONE_SHIFT)
++#define _PSB_FENCE_TYPE_RASTER_DONE (1 << _PSB_FENCE_RASTER_DONE_SHIFT)
++#define _PSB_FENCE_TYPE_SCENE_DONE (1 << _PSB_FENCE_SCENE_DONE_SHIFT)
++#define _PSB_FENCE_TYPE_FEEDBACK (1 << _PSB_FENCE_FEEDBACK_SHIFT)
+
-+ /* setup pipeconf */
-+ pipeconf = I915_READ(pipeconf_reg);
++#define PSB_ENGINE_HPRAST 4
++#define PSB_NUM_ENGINES 5
+
-+ /* Set up the display plane register */
-+ dspcntr = DISPPLANE_GAMMA_ENABLE;
++#define PSB_TA_FLAG_FIRSTPASS (1 << 0)
++#define PSB_TA_FLAG_LASTPASS (1 << 1)
+
-+ switch (crtc->fb->bits_per_pixel) {
-+ case 8:
-+ dspcntr |= DISPPLANE_8BPP;
-+ break;
-+ case 16:
-+ if (crtc->fb->depth == 15)
-+ dspcntr |= DISPPLANE_15_16BPP;
-+ else
-+ dspcntr |= DISPPLANE_16BPP;
-+ break;
-+ case 32:
-+ dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
-+ break;
-+ default:
-+ DRM_ERROR("Unknown color depth\n");
-+ return;
-+ }
++#define PSB_FEEDBACK_OP_VISTEST (1 << 0)
+
++struct drm_psb_scene {
++ int handle_valid;
++ uint32_t handle;
++ uint32_t w;
++ uint32_t h;
++ uint32_t num_buffers;
++};
+
-+ if (pipe == 0)
-+ dspcntr |= DISPPLANE_SEL_PIPE_A;
-+ else
-+ dspcntr |= DISPPLANE_SEL_PIPE_B;
++struct drm_psb_hw_info
++{
++ uint32_t rev_id;
++ uint32_t caps;
++};
+
-+ if (pipe == 0 && !IS_I965G(dev)) {
-+ /* Enable pixel doubling when the dot clock is > 90% of the (display)
-+ * core speed.
-+ *
-+ * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
-+ * pipe == 0 check?
-+ */
-+ if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10)
-+ pipeconf |= PIPEACONF_DOUBLE_WIDE;
-+ else
-+ pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
-+ }
++typedef struct drm_psb_cmdbuf_arg {
++ uint64_t buffer_list; /* List of buffers to validate */
++ uint64_t clip_rects; /* See i915 counterpart */
++ uint64_t scene_arg;
++ uint64_t fence_arg;
+
-+ dspcntr |= DISPLAY_PLANE_ENABLE;
-+ pipeconf |= PIPEACONF_ENABLE;
-+ dpll |= DPLL_VCO_ENABLE;
++ uint32_t ta_flags;
+
++ uint32_t ta_handle; /* TA reg-value pairs */
++ uint32_t ta_offset;
++ uint32_t ta_size;
+
-+ /* Disable the panel fitter if it was on our pipe */
-+ if (intel_panel_fitter_pipe(dev) == pipe)
-+ I915_WRITE(PFIT_CONTROL, 0);
++ uint32_t oom_handle;
++ uint32_t oom_offset;
++ uint32_t oom_size;
+
-+ DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
-+ drm_mode_debug_printmodeline(mode);
++ uint32_t cmdbuf_handle; /* 2D Command buffer object or, */
++ uint32_t cmdbuf_offset; /* rasterizer reg-value pairs */
++ uint32_t cmdbuf_size;
+
++ uint32_t reloc_handle; /* Reloc buffer object */
++ uint32_t reloc_offset;
++ uint32_t num_relocs;
+
-+ if (dpll & DPLL_VCO_ENABLE) {
-+ I915_WRITE(fp_reg, fp);
-+ I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
-+ I915_READ(dpll_reg);
-+ udelay(150);
-+ }
++ int32_t damage; /* Damage front buffer with cliprects */
++ /* Not implemented yet */
++ uint32_t fence_flags;
++ uint32_t engine;
+
-+ /* The LVDS pin pair needs to be on before the DPLLs are enabled.
-+ * This is an exception to the general rule that mode_set doesn't turn
-+ * things on.
++ /*
++ * Feedback;
+ */
-+ if (is_lvds) {
-+ u32 lvds = I915_READ(LVDS);
-+
-+ lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
-+ /* Set the B0-B3 data pairs corresponding to whether we're going to
-+ * set the DPLLs for dual-channel mode or not.
-+ */
-+ if (clock.p2 == 7)
-+ lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
-+ else
-+ lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
-+
-+ /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
-+ * appropriately here, but we need to look more thoroughly into how
-+ * panels behave in the two modes.
-+ */
+
-+ I915_WRITE(LVDS, lvds);
-+ I915_READ(LVDS);
-+ }
-+
-+ I915_WRITE(fp_reg, fp);
-+ I915_WRITE(dpll_reg, dpll);
-+ I915_READ(dpll_reg);
-+ /* Wait for the clocks to stabilize. */
-+ udelay(150);
-+
-+ if (IS_I965G(dev)) {
-+ int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
-+ I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
-+ ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
-+ } else {
-+ /* write it again -- the BIOS does, after all */
-+ I915_WRITE(dpll_reg, dpll);
-+ }
-+ I915_READ(dpll_reg);
-+ /* Wait for the clocks to stabilize. */
-+ udelay(150);
-+
-+ I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
-+ ((adjusted_mode->crtc_htotal - 1) << 16));
-+ I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
-+ ((adjusted_mode->crtc_hblank_end - 1) << 16));
-+ I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
-+ ((adjusted_mode->crtc_hsync_end - 1) << 16));
-+ I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
-+ ((adjusted_mode->crtc_vtotal - 1) << 16));
-+ I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
-+ ((adjusted_mode->crtc_vblank_end - 1) << 16));
-+ I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
-+ ((adjusted_mode->crtc_vsync_end - 1) << 16));
-+ I915_WRITE(dspstride_reg, crtc->fb->pitch);
-+ /* pipesrc and dspsize control the size that is scaled from, which should
-+ * always be the user's requested size.
-+ */
-+ I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
-+ I915_WRITE(dsppos_reg, 0);
-+ I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
-+ I915_WRITE(pipeconf_reg, pipeconf);
-+ I915_READ(pipeconf_reg);
-+
-+ intel_wait_for_vblank(dev);
-+
-+ I915_WRITE(dspcntr_reg, dspcntr);
++ uint32_t feedback_ops;
++ uint32_t feedback_handle;
++ uint32_t feedback_offset;
++ uint32_t feedback_breakpoints;
++ uint32_t feedback_size;
++} drm_psb_cmdbuf_arg_t;
+
-+ /* Flush the plane changes */
-+ intel_pipe_set_base(crtc, x, y, old_fb);
++struct drm_psb_xhw_init_arg {
++ uint32_t operation;
++ uint32_t buffer_handle;
++};
+
-+ intel_wait_for_vblank(dev);
-+}
++/*
++ * Feedback components:
++ */
+
-+/** Loads the palette/gamma unit for the CRTC with the prepared values */
-+void intel_crtc_load_lut(struct drm_crtc *crtc)
-+{
-+ struct drm_device *dev = crtc->dev;
-+ DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
-+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-+ int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
-+ int i;
++/*
++ * Vistest component. The number of these in the feedback buffer
++ * equals the number of vistest breakpoints + 1.
++ * This is currently the only feedback component.
++ */
+
-+ /* The clocks have to be on to load the palette. */
-+ if (!crtc->enabled)
-+ return;
++struct drm_psb_vistest {
++ uint32_t vt[8];
++};
+
-+ for (i = 0; i < 256; i++) {
-+ I915_WRITE(palreg + 4 * i,
-+ (intel_crtc->lut_r[i] << 16) |
-+ (intel_crtc->lut_g[i] << 8) |
-+ intel_crtc->lut_b[i]);
-+ }
-+}
++#define PSB_HW_COOKIE_SIZE 16
++#define PSB_HW_FEEDBACK_SIZE 8
++#define PSB_HW_OOM_CMD_SIZE 6
+
-+static int intel_crtc_cursor_set(struct drm_crtc *crtc,
-+ struct drm_file *file_priv,
-+ uint32_t handle,
-+ uint32_t width, uint32_t height)
-+{
-+ struct drm_device *dev = crtc->dev;
-+ DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
-+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-+ struct drm_gem_object *bo;
-+ struct drm_i915_gem_object *obj_priv;
-+ int pipe = intel_crtc->pipe;
-+ uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
-+ uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
-+ uint32_t temp;
-+ size_t addr;
++struct drm_psb_xhw_arg {
++ uint32_t op;
+ int ret;
++ uint32_t irq_op;
++ uint32_t issue_irq;
++ uint32_t cookie[PSB_HW_COOKIE_SIZE];
++ union {
++ struct {
++ uint32_t w;
++ uint32_t h;
++ uint32_t size;
++ uint32_t clear_p_start;
++ uint32_t clear_num_pages;
++ } si;
++ struct {
++ uint32_t fire_flags;
++ uint32_t hw_context;
++ uint32_t offset;
++ uint32_t engine;
++ uint32_t flags;
++ uint32_t rca;
++ uint32_t num_oom_cmds;
++ uint32_t oom_cmds[PSB_HW_OOM_CMD_SIZE];
++ } sb;
++ struct {
++ uint32_t pages;
++ uint32_t size;
++ } bi;
++ struct {
++ uint32_t bca;
++ uint32_t rca;
++ uint32_t flags;
++ } oom;
++ struct {
++ uint32_t pt_offset;
++ uint32_t param_offset;
++ uint32_t flags;
++ } bl;
++ struct {
++ uint32_t value;
++ } cl;
++ uint32_t feedback[PSB_HW_FEEDBACK_SIZE];
++ } arg;
++};
+
-+ DRM_DEBUG("\n");
-+
-+ /* if we want to turn off the cursor ignore width and height */
-+ if (!handle) {
-+ DRM_DEBUG("cursor off\n");
-+ temp = CURSOR_MODE_DISABLE;
-+ addr = 0;
-+ bo = NULL;
-+ goto finish;
-+ }
-+
-+ /* Currently we only support 64x64 cursors */
-+ if (width != 64 || height != 64) {
-+ DRM_ERROR("we currently only support 64x64 cursors\n");
-+ return -EINVAL;
-+ }
-+
-+ bo = drm_gem_object_lookup(dev, file_priv, handle);
-+ if (!bo)
-+ return -ENOENT;
-+
-+ obj_priv = bo->driver_private;
-+
-+ if (bo->size < width * height * 4) {
-+ DRM_ERROR("buffer is to small\n");
-+ ret = -ENOMEM;
-+ goto fail;
-+ }
-+#if 0
-+ /* we only need to pin inside GTT if cursor is non-phy */
-+ if (!dev_priv->cursor_needs_physical) {
-+ ret = i915_gem_object_pin(bo, PAGE_SIZE);
-+ if (ret) {
-+ DRM_ERROR("failed to pin cursor bo\n");
-+ goto fail;
-+ }
-+ addr = obj_priv->gtt_offset;
-+ } else {
-+ ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
-+ if (ret) {
-+ DRM_ERROR("failed to attach phys object\n");
-+ goto fail;
-+ }
-+ addr = obj_priv->phys_obj->handle->busaddr;
-+ }
-+#endif
-+ temp = 0;
-+ /* set the pipe for the cursor */
-+ temp |= (pipe << 28);
-+ temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
-+
-+ finish:
-+ I915_WRITE(control, temp);
-+ I915_WRITE(base, addr);
-+
-+ if (intel_crtc->cursor_bo) {
-+#if 0
-+ if (dev_priv->cursor_needs_physical) {
-+ if (intel_crtc->cursor_bo != bo)
-+ i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
-+ } else
-+ i915_gem_object_unpin(intel_crtc->cursor_bo);
-+ mutex_lock(&dev->struct_mutex);
-+ drm_gem_object_unreference(intel_crtc->cursor_bo);
-+ mutex_unlock(&dev->struct_mutex);
-+#endif
-+ }
-+
-+ intel_crtc->cursor_addr = addr;
-+ intel_crtc->cursor_bo = bo;
-+
-+ return 0;
-+fail:
-+ mutex_lock(&dev->struct_mutex);
-+ drm_gem_object_unreference(bo);
-+ mutex_unlock(&dev->struct_mutex);
-+ return ret;
-+}
-+
-+static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
-+{
-+ struct drm_device *dev = crtc->dev;
-+ DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
-+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-+ int pipe = intel_crtc->pipe;
-+ uint32_t temp = 0;
-+ uint32_t adder;
-+
-+ if (x < 0) {
-+ temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT);
-+ x = -x;
-+ }
-+ if (y < 0) {
-+ temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT);
-+ y = -y;
-+ }
-+
-+ temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
-+ temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
-+
-+ adder = intel_crtc->cursor_addr;
-+ I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
-+ I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
++#define DRM_PSB_CMDBUF 0x00
++#define DRM_PSB_XHW_INIT 0x01
++#define DRM_PSB_XHW 0x02
++#define DRM_PSB_SCENE_UNREF 0x03
++/* Controlling the kernel modesetting buffers */
++#define DRM_PSB_KMS_OFF 0x04
++#define DRM_PSB_KMS_ON 0x05
++#define DRM_PSB_HW_INFO 0x06
+
-+ return 0;
-+}
++#define PSB_XHW_INIT 0x00
++#define PSB_XHW_TAKEDOWN 0x01
+
-+/** Sets the color ramps on behalf of RandR */
-+void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
-+ u16 blue, int regno)
-+{
-+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
++#define PSB_XHW_FIRE_RASTER 0x00
++#define PSB_XHW_SCENE_INFO 0x01
++#define PSB_XHW_SCENE_BIND_FIRE 0x02
++#define PSB_XHW_TA_MEM_INFO 0x03
++#define PSB_XHW_RESET_DPM 0x04
++#define PSB_XHW_OOM 0x05
++#define PSB_XHW_TERMINATE 0x06
++#define PSB_XHW_VISTEST 0x07
++#define PSB_XHW_RESUME 0x08
++#define PSB_XHW_TA_MEM_LOAD 0x09
++#define PSB_XHW_CHECK_LOCKUP 0x0a
+
-+ intel_crtc->lut_r[regno] = red >> 8;
-+ intel_crtc->lut_g[regno] = green >> 8;
-+ intel_crtc->lut_b[regno] = blue >> 8;
-+}
++#define PSB_SCENE_FLAG_DIRTY (1 << 0)
++#define PSB_SCENE_FLAG_COMPLETE (1 << 1)
++#define PSB_SCENE_FLAG_SETUP (1 << 2)
++#define PSB_SCENE_FLAG_SETUP_ONLY (1 << 3)
++#define PSB_SCENE_FLAG_CLEARED (1 << 4)
+
-+static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
-+ u16 *blue, uint32_t size)
-+{
-+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-+ int i;
++#define PSB_TA_MEM_FLAG_TA (1 << 0)
++#define PSB_TA_MEM_FLAG_RASTER (1 << 1)
++#define PSB_TA_MEM_FLAG_HOSTA (1 << 2)
++#define PSB_TA_MEM_FLAG_HOSTD (1 << 3)
++#define PSB_TA_MEM_FLAG_INIT (1 << 4)
++#define PSB_TA_MEM_FLAG_NEW_PT_OFFSET (1 << 5)
+
-+ if (size != 256)
-+ return;
++/*Raster fire will deallocate memory */
++#define PSB_FIRE_FLAG_RASTER_DEALLOC (1 << 0)
++/*Isp reset needed due to change in ZLS format */
++#define PSB_FIRE_FLAG_NEEDS_ISP_RESET (1 << 1)
++/*These are set by Xpsb. */
++#define PSB_FIRE_FLAG_XHW_MASK 0xff000000
++/*The task has had at least one OOM and Xpsb will
++ send back messages on each fire. */
++#define PSB_FIRE_FLAG_XHW_OOM (1 << 24)
+
-+ for (i = 0; i < 256; i++) {
-+ intel_crtc->lut_r[i] = red[i] >> 8;
-+ intel_crtc->lut_g[i] = green[i] >> 8;
-+ intel_crtc->lut_b[i] = blue[i] >> 8;
-+ }
++#define PSB_SCENE_ENGINE_TA 0
++#define PSB_SCENE_ENGINE_RASTER 1
++#define PSB_SCENE_NUM_ENGINES 2
+
-+ intel_crtc_load_lut(crtc);
-+}
++struct drm_psb_dev_info_arg {
++ uint32_t num_use_attribute_registers;
++};
++#define DRM_PSB_DEVINFO 0x01
+
-+/**
-+ * Get a pipe with a simple mode set on it for doing load-based monitor
-+ * detection.
++#endif
+Index: linux-2.6.28/drivers/gpu/drm/psb/psb_drv.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.28/drivers/gpu/drm/psb/psb_drv.c 2009-02-12 10:11:59.000000000 +0000
+@@ -0,0 +1,1096 @@
++/**************************************************************************
++ * Copyright (c) 2007, Intel Corporation.
++ * All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
+ *
-+ * It will be up to the load-detect code to adjust the pipe as appropriate for
-+ * its requirements. The pipe will be connected to no other outputs.
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
-+ * Currently this code will only succeed if there is a pipe with no outputs
-+ * configured for it. In the future, it could choose to temporarily disable
-+ * some outputs to free up a pipe for its use.
++ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
++ * develop this driver.
+ *
-+ * \return crtc, or NULL if no pipes are available.
++ **************************************************************************/
++/*
+ */
+
-+/* VESA 640x480x72Hz mode to set on the pipe */
-+static struct drm_display_mode load_detect_mode = {
-+ DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
-+ 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
-+};
-+
-+struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
-+ struct drm_display_mode *mode,
-+ int *dpms_mode)
-+{
-+ struct intel_crtc *intel_crtc;
-+ struct drm_crtc *possible_crtc;
-+ struct drm_crtc *supported_crtc =NULL;
-+ struct drm_encoder *encoder = &intel_output->enc;
-+ struct drm_crtc *crtc = NULL;
-+ struct drm_device *dev = encoder->dev;
-+ struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
-+ struct drm_crtc_helper_funcs *crtc_funcs;
-+ int i = -1;
-+
-+ /*
-+ * Algorithm gets a little messy:
-+ * - if the connector already has an assigned crtc, use it (but make
-+ * sure it's on first)
-+ * - try to find the first unused crtc that can drive this connector,
-+ * and use that if we find one
-+ * - if there are no unused crtcs available, try to use the first
-+ * one we found that supports the connector
-+ */
-+
-+ /* See if we already have a CRTC for this connector */
-+ if (encoder->crtc) {
-+ crtc = encoder->crtc;
-+ /* Make sure the crtc and connector are running */
-+ intel_crtc = to_intel_crtc(crtc);
-+ *dpms_mode = intel_crtc->dpms_mode;
-+ if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
-+ crtc_funcs = crtc->helper_private;
-+ crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
-+ encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
-+ }
-+ return crtc;
-+ }
++#include "drmP.h"
++#include "drm.h"
++#include "psb_drm.h"
++#include "psb_drv.h"
++#include "psb_reg.h"
++#include "../i915/i915_reg.h"
++#include "psb_msvdx.h"
++#include "drm_pciids.h"
++#include "psb_scene.h"
++#include "drm_crtc.h"
++#include "drm_crtc_helper.h"
++#include <linux/cpu.h>
++#include <linux/notifier.h>
++#include <linux/fb.h>
+
-+ /* Find an unused one (if possible) */
-+ list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
-+ i++;
-+ if (!(encoder->possible_crtcs & (1 << i)))
-+ continue;
-+ if (!possible_crtc->enabled) {
-+ crtc = possible_crtc;
-+ break;
-+ }
-+ if (!supported_crtc)
-+ supported_crtc = possible_crtc;
-+ }
++extern int drm_helper_probe_connector_modes(struct drm_device *dev, uint32_t maxX, uint32_t maxY);
+
-+ /*
-+ * If we didn't find an unused CRTC, don't use any.
-+ */
-+ if (!crtc) {
-+ return NULL;
-+ }
++int drm_psb_debug = 0;
++EXPORT_SYMBOL(drm_psb_debug);
++static int drm_psb_trap_pagefaults = 0;
++static int drm_psb_clock_gating = 0;
++static int drm_psb_ta_mem_size = 32 * 1024;
++int drm_psb_disable_vsync = 1;
++int drm_psb_no_fb = 0;
++int drm_psb_force_pipeb = 0;
++char* psb_init_mode;
++/*
++ *
++ */
++#define SII_1392_WA
++#ifdef SII_1392_WA
++extern int SII_1392;
++#endif
+
-+ encoder->crtc = crtc;
-+ intel_output->load_detect_temp = true;
++MODULE_PARM_DESC(debug, "Enable debug output");
++MODULE_PARM_DESC(clock_gating, "clock gating");
++MODULE_PARM_DESC(no_fb, "Disable FBdev");
++MODULE_PARM_DESC(trap_pagefaults, "Error and reset on MMU pagefaults");
++MODULE_PARM_DESC(disable_vsync, "Disable vsync interrupts");
++MODULE_PARM_DESC(force_pipeb, "Forces PIPEB to become primary fb");
++MODULE_PARM_DESC(ta_mem_size, "TA memory size in kiB");
++MODULE_PARM_DESC(mode, "initial mode name");
++MODULE_PARM_DESC(xres, "initial mode width");
++MODULE_PARM_DESC(yres, "initial mode height");
+
-+ intel_crtc = to_intel_crtc(crtc);
-+ *dpms_mode = intel_crtc->dpms_mode;
++module_param_named(debug, drm_psb_debug, int, 0600);
++module_param_named(clock_gating, drm_psb_clock_gating, int, 0600);
++module_param_named(no_fb, drm_psb_no_fb, int, 0600);
++module_param_named(trap_pagefaults, drm_psb_trap_pagefaults, int, 0600);
++module_param_named(disable_vsync, drm_psb_disable_vsync, int, 0600);
++module_param_named(force_pipeb, drm_psb_force_pipeb, int, 0600);
++module_param_named(ta_mem_size, drm_psb_ta_mem_size, int, 0600);
++module_param_named(mode, psb_init_mode, charp, 0600);
+
-+ if (!crtc->enabled) {
-+ if (!mode)
-+ mode = &load_detect_mode;
-+ drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
-+ } else {
-+ if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
-+ crtc_funcs = crtc->helper_private;
-+ crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
-+ }
++static struct pci_device_id pciidlist[] = {
++ psb_PCI_IDS
++};
+
-+ /* Add this connector to the crtc */
-+ encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
-+ encoder_funcs->commit(encoder);
-+ }
-+ /* let the connector get through one full cycle before testing */
-+ intel_wait_for_vblank(dev);
++#define DRM_PSB_CMDBUF_IOCTL DRM_IOW(DRM_PSB_CMDBUF, \
++ struct drm_psb_cmdbuf_arg)
++#define DRM_PSB_XHW_INIT_IOCTL DRM_IOR(DRM_PSB_XHW_INIT, \
++ struct drm_psb_xhw_init_arg)
++#define DRM_PSB_XHW_IOCTL DRM_IO(DRM_PSB_XHW)
+
-+ return crtc;
-+}
++#define DRM_PSB_SCENE_UNREF_IOCTL DRM_IOWR(DRM_PSB_SCENE_UNREF, \
++ struct drm_psb_scene)
++#define DRM_PSB_HW_INFO_IOCTL DRM_IOR(DRM_PSB_HW_INFO, \
++ struct drm_psb_hw_info)
+
-+void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
-+{
-+ struct drm_encoder *encoder = &intel_output->enc;
-+ struct drm_device *dev = encoder->dev;
-+ struct drm_crtc *crtc = encoder->crtc;
-+ struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
-+ struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
++#define DRM_PSB_KMS_OFF_IOCTL DRM_IO(DRM_PSB_KMS_OFF)
++#define DRM_PSB_KMS_ON_IOCTL DRM_IO(DRM_PSB_KMS_ON)
+
-+ if (intel_output->load_detect_temp) {
-+ encoder->crtc = NULL;
-+ intel_output->load_detect_temp = false;
-+ crtc->enabled = drm_helper_crtc_in_use(crtc);
-+ drm_helper_disable_unused_functions(dev);
-+ }
++static struct drm_ioctl_desc psb_ioctls[] = {
++ DRM_IOCTL_DEF(DRM_PSB_CMDBUF_IOCTL, psb_cmdbuf_ioctl, DRM_AUTH),
++ DRM_IOCTL_DEF(DRM_PSB_XHW_INIT_IOCTL, psb_xhw_init_ioctl,
++ DRM_ROOT_ONLY),
++ DRM_IOCTL_DEF(DRM_PSB_XHW_IOCTL, psb_xhw_ioctl, DRM_ROOT_ONLY),
++ DRM_IOCTL_DEF(DRM_PSB_SCENE_UNREF_IOCTL, drm_psb_scene_unref_ioctl,
++ DRM_AUTH),
++ DRM_IOCTL_DEF(DRM_PSB_KMS_OFF_IOCTL, psbfb_kms_off_ioctl,
++ DRM_ROOT_ONLY),
++ DRM_IOCTL_DEF(DRM_PSB_KMS_ON_IOCTL, psbfb_kms_on_ioctl, DRM_ROOT_ONLY),
++ DRM_IOCTL_DEF(DRM_PSB_HW_INFO_IOCTL, psb_hw_info_ioctl, DRM_AUTH),
++};
++static int psb_max_ioctl = DRM_ARRAY_SIZE(psb_ioctls);
+
-+ /* Switch crtc and output back off if necessary */
-+ if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
-+ if (encoder->crtc == crtc)
-+ encoder_funcs->dpms(encoder, dpms_mode);
-+ crtc_funcs->dpms(crtc, dpms_mode);
-+ }
-+}
++static int probe(struct pci_dev *pdev, const struct pci_device_id *ent);
+
-+/* Returns the clock of the currently programmed mode of the given pipe. */
-+static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
++#ifdef USE_PAT_WC
++#warning Init pat
++static int __cpuinit psb_cpu_callback(struct notifier_block *nfb,
++ unsigned long action,
++ void *hcpu)
+{
-+ DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
-+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-+ int pipe = intel_crtc->pipe;
-+ u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
-+ u32 fp;
-+ intel_clock_t clock;
-+
-+ if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
-+ fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
-+ else
-+ fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
-+
-+ clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
-+ clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
-+ clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
-+ if (IS_I9XX(dev)) {
-+ clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
-+ DPLL_FPA01_P1_POST_DIV_SHIFT);
-+
-+ switch (dpll & DPLL_MODE_MASK) {
-+ case DPLLB_MODE_DAC_SERIAL:
-+ clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
-+ 5 : 10;
-+ break;
-+ case DPLLB_MODE_LVDS:
-+ clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
-+ 7 : 14;
-+ break;
-+ default:
-+ DRM_DEBUG("Unknown DPLL mode %08x in programmed "
-+ "mode\n", (int)(dpll & DPLL_MODE_MASK));
-+ return 0;
-+ }
-+
-+ /* XXX: Handle the 100Mhz refclk */
-+ i9xx_clock(96000, &clock);
-+ } else {
-+ bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
-+
-+ if (is_lvds) {
-+ clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
-+ DPLL_FPA01_P1_POST_DIV_SHIFT);
-+ clock.p2 = 14;
-+
-+ if ((dpll & PLL_REF_INPUT_MASK) ==
-+ PLLB_REF_INPUT_SPREADSPECTRUMIN) {
-+ /* XXX: might not be 66MHz */
-+ i8xx_clock(66000, &clock);
-+ } else
-+ i8xx_clock(48000, &clock);
-+ } else {
-+ if (dpll & PLL_P1_DIVIDE_BY_TWO)
-+ clock.p1 = 2;
-+ else {
-+ clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
-+ DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
-+ }
-+ if (dpll & PLL_P2_DIVIDE_BY_4)
-+ clock.p2 = 4;
-+ else
-+ clock.p2 = 2;
-+
-+ i8xx_clock(48000, &clock);
-+ }
-+ }
-+
-+ /* XXX: It would be nice to validate the clocks, but we can't reuse
-+ * i830PllIsValid() because it relies on the xf86_config connector
-+ * configuration being accurate, which it isn't necessarily.
-+ */
++ if (action == CPU_ONLINE)
++ drm_init_pat();
+
-+ return clock.dot;
++ return 0;
+}
+
-+/** Returns the currently programmed mode of the given pipe. */
-+struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
-+ struct drm_crtc *crtc)
-+{
-+ DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
-+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-+ int pipe = intel_crtc->pipe;
-+ struct drm_display_mode *mode;
-+ int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
-+ int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
-+ int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
-+ int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
-+
-+ mode = kzalloc(sizeof(*mode), GFP_KERNEL);
-+ if (!mode)
-+ return NULL;
-+
-+ mode->clock = intel_crtc_clock_get(dev, crtc);
-+ mode->hdisplay = (htot & 0xffff) + 1;
-+ mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
-+ mode->hsync_start = (hsync & 0xffff) + 1;
-+ mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
-+ mode->vdisplay = (vtot & 0xffff) + 1;
-+ mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
-+ mode->vsync_start = (vsync & 0xffff) + 1;
-+ mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
-+
-+ drm_mode_set_name(mode);
-+ drm_mode_set_crtcinfo(mode, 0);
++static struct notifier_block __cpuinitdata psb_nb = {
++ .notifier_call = psb_cpu_callback,
++ .priority = 1
++};
++#endif
+
-+ return mode;
++static int dri_library_name(struct drm_device *dev, char *buf)
++{
++ return snprintf(buf, PAGE_SIZE, "psb\n");
+}
+
-+static void intel_crtc_destroy(struct drm_crtc *crtc)
++static void psb_set_uopt(struct drm_psb_uopt *uopt)
+{
-+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-+
-+ drm_crtc_cleanup(crtc);
-+ kfree(intel_crtc);
++ uopt->clock_gating = drm_psb_clock_gating;
+}
+
-+static const struct drm_crtc_helper_funcs intel_helper_funcs = {
-+ .dpms = intel_crtc_dpms,
-+ .mode_fixup = intel_crtc_mode_fixup,
-+ .mode_set = intel_crtc_mode_set,
-+ .mode_set_base = intel_pipe_set_base,
-+ .prepare = intel_crtc_prepare,
-+ .commit = intel_crtc_commit,
-+};
-+
-+static const struct drm_crtc_funcs intel_crtc_funcs = {
-+ .cursor_set = intel_crtc_cursor_set,
-+ .cursor_move = intel_crtc_cursor_move,
-+ .gamma_set = intel_crtc_gamma_set,
-+ .set_config = drm_crtc_helper_set_config,
-+ .destroy = intel_crtc_destroy,
-+};
-+
-+
-+static void intel_crtc_init(struct drm_device *dev, int pipe)
++static void psb_lastclose(struct drm_device *dev)
+{
-+ struct intel_crtc *intel_crtc;
-+ int i;
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
+
-+ intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
-+ if (intel_crtc == NULL)
++ if (!dev->dev_private)
+ return;
+
-+ drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
-+
-+ intel_crtc->pipe = pipe;
-+ for (i = 0; i < 256; i++) {
-+ intel_crtc->lut_r[i] = i;
-+ intel_crtc->lut_g[i] = i;
-+ intel_crtc->lut_b[i] = i;
++ mutex_lock(&dev->struct_mutex);
++ if (dev_priv->ta_mem)
++ psb_ta_mem_unref_devlocked(&dev_priv->ta_mem);
++ mutex_unlock(&dev->struct_mutex);
++ mutex_lock(&dev_priv->cmdbuf_mutex);
++ if (dev_priv->buffers) {
++ vfree(dev_priv->buffers);
++ dev_priv->buffers = NULL;
+ }
-+
-+ intel_crtc->cursor_addr = 0;
-+ intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
-+ drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
-+
-+ intel_crtc->mode_set.crtc = &intel_crtc->base;
-+ intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1);
-+ intel_crtc->mode_set.num_connectors = 0;
-+
++ mutex_unlock(&dev_priv->cmdbuf_mutex);
+}
+
-+struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
++static void psb_do_takedown(struct drm_device *dev)
+{
-+ struct drm_crtc *crtc = NULL;
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
+
-+ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-+ if (intel_crtc->pipe == pipe)
-+ break;
++ mutex_lock(&dev->struct_mutex);
++ if (dev->bm.initialized) {
++ if (dev_priv->have_mem_rastgeom) {
++ drm_bo_clean_mm(dev, DRM_PSB_MEM_RASTGEOM);
++ dev_priv->have_mem_rastgeom = 0;
++ }
++ if (dev_priv->have_mem_mmu) {
++ drm_bo_clean_mm(dev, DRM_PSB_MEM_MMU);
++ dev_priv->have_mem_mmu = 0;
++ }
++ if (dev_priv->have_mem_aper) {
++ drm_bo_clean_mm(dev, DRM_PSB_MEM_APER);
++ dev_priv->have_mem_aper = 0;
++ }
++ if (dev_priv->have_tt) {
++ drm_bo_clean_mm(dev, DRM_BO_MEM_TT);
++ dev_priv->have_tt = 0;
++ }
++ if (dev_priv->have_vram) {
++ drm_bo_clean_mm(dev, DRM_BO_MEM_VRAM);
++ dev_priv->have_vram = 0;
++ }
+ }
-+ return crtc;
-+}
++ mutex_unlock(&dev->struct_mutex);
+
-+static int intel_connector_clones(struct drm_device *dev, int type_mask)
-+{
-+ int index_mask = 0;
-+ struct drm_connector *connector;
-+ int entry = 0;
++ if (dev_priv->has_msvdx)
++ psb_msvdx_uninit(dev);
+
-+ list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-+ struct intel_output *intel_output = to_intel_output(connector);
-+ if (type_mask & (1 << intel_output->type))
-+ index_mask |= (1 << entry);
-+ entry++;
++ if (dev_priv->comm) {
++ kunmap(dev_priv->comm_page);
++ dev_priv->comm = NULL;
++ }
++ if (dev_priv->comm_page) {
++ __free_page(dev_priv->comm_page);
++ dev_priv->comm_page = NULL;
+ }
-+ return index_mask;
+}
+
-+
-+static void intel_setup_outputs(struct drm_device *dev)
++void psb_clockgating(struct drm_psb_private *dev_priv)
+{
-+ struct drm_connector *connector;
++ uint32_t clock_gating;
+
-+ if (!IS_POULSBO(dev))
-+ intel_crt_init(dev);
++ if (dev_priv->uopt.clock_gating == 1) {
++ PSB_DEBUG_INIT("Disabling clock gating.\n");
+
-+ /* Set up integrated LVDS */
-+ if (IS_MOBILE(dev) && !IS_I830(dev))
-+ intel_lvds_init(dev);
++ clock_gating = (_PSB_C_CLKGATECTL_CLKG_DISABLED <<
++ _PSB_C_CLKGATECTL_2D_CLKG_SHIFT) |
++ (_PSB_C_CLKGATECTL_CLKG_DISABLED <<
++ _PSB_C_CLKGATECTL_ISP_CLKG_SHIFT) |
++ (_PSB_C_CLKGATECTL_CLKG_DISABLED <<
++ _PSB_C_CLKGATECTL_TSP_CLKG_SHIFT) |
++ (_PSB_C_CLKGATECTL_CLKG_DISABLED <<
++ _PSB_C_CLKGATECTL_TA_CLKG_SHIFT) |
++ (_PSB_C_CLKGATECTL_CLKG_DISABLED <<
++ _PSB_C_CLKGATECTL_DPM_CLKG_SHIFT) |
++ (_PSB_C_CLKGATECTL_CLKG_DISABLED <<
++ _PSB_C_CLKGATECTL_USE_CLKG_SHIFT);
+
-+ if (IS_I9XX(dev)) {
-+ intel_sdvo_init(dev, SDVOB);
-+ intel_sdvo_init(dev, SDVOC);
-+ }
++ } else if (dev_priv->uopt.clock_gating == 2) {
++ PSB_DEBUG_INIT("Enabling clock gating.\n");
+
-+ list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-+ struct intel_output *intel_output = to_intel_output(connector);
-+ struct drm_encoder *encoder = &intel_output->enc;
-+ int crtc_mask = 0, clone_mask = 0;
++ clock_gating = (_PSB_C_CLKGATECTL_CLKG_AUTO <<
++ _PSB_C_CLKGATECTL_2D_CLKG_SHIFT) |
++ (_PSB_C_CLKGATECTL_CLKG_AUTO <<
++ _PSB_C_CLKGATECTL_ISP_CLKG_SHIFT) |
++ (_PSB_C_CLKGATECTL_CLKG_AUTO <<
++ _PSB_C_CLKGATECTL_TSP_CLKG_SHIFT) |
++ (_PSB_C_CLKGATECTL_CLKG_AUTO <<
++ _PSB_C_CLKGATECTL_TA_CLKG_SHIFT) |
++ (_PSB_C_CLKGATECTL_CLKG_AUTO <<
++ _PSB_C_CLKGATECTL_DPM_CLKG_SHIFT) |
++ (_PSB_C_CLKGATECTL_CLKG_AUTO <<
++ _PSB_C_CLKGATECTL_USE_CLKG_SHIFT);
++ } else
++ clock_gating = PSB_RSGX32(PSB_CR_CLKGATECTL);
+
-+ /* valid crtcs */
-+ switch(intel_output->type) {
-+ case INTEL_OUTPUT_HDMI:
-+ crtc_mask = ((1 << 0)|
-+ (1 << 1));
-+ clone_mask = ((1 << INTEL_OUTPUT_HDMI));
-+ break;
-+ case INTEL_OUTPUT_DVO:
-+ case INTEL_OUTPUT_SDVO:
-+ crtc_mask = ((1 << 0)|
-+ (1 << 1));
-+ clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
-+ (1 << INTEL_OUTPUT_DVO) |
-+ (1 << INTEL_OUTPUT_SDVO));
-+ break;
-+ case INTEL_OUTPUT_ANALOG:
-+ crtc_mask = ((1 << 0)|
-+ (1 << 1));
-+ clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
-+ (1 << INTEL_OUTPUT_DVO) |
-+ (1 << INTEL_OUTPUT_SDVO));
-+ break;
-+ case INTEL_OUTPUT_LVDS:
-+ crtc_mask = (1 << 1);
-+ clone_mask = (1 << INTEL_OUTPUT_LVDS);
-+ break;
-+ case INTEL_OUTPUT_TVOUT:
-+ crtc_mask = ((1 << 0) |
-+ (1 << 1));
-+ clone_mask = (1 << INTEL_OUTPUT_TVOUT);
-+ break;
-+ }
-+ encoder->possible_crtcs = crtc_mask;
-+ encoder->possible_clones = intel_connector_clones(dev, clone_mask);
-+ }
++#ifdef FIX_TG_2D_CLOCKGATE
++ clock_gating &= ~_PSB_C_CLKGATECTL_2D_CLKG_MASK;
++ clock_gating |= (_PSB_C_CLKGATECTL_CLKG_DISABLED <<
++ _PSB_C_CLKGATECTL_2D_CLKG_SHIFT);
++#endif
++ PSB_WSGX32(clock_gating, PSB_CR_CLKGATECTL);
++ (void)PSB_RSGX32(PSB_CR_CLKGATECTL);
+}
+
-+static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
++static int psb_do_init(struct drm_device *dev)
+{
-+ struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
-+ struct drm_device *dev = fb->dev;
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
++ struct psb_gtt *pg = dev_priv->pg;
+
-+ //if (fb->fbdev)
-+ // intelfb_remove(dev, fb);
++ uint32_t stolen_gtt;
++ uint32_t tt_start;
++ uint32_t tt_pages;
+
-+ drm_framebuffer_cleanup(fb);
-+ mutex_lock(&dev->struct_mutex);
-+ drm_gem_object_unreference(intel_fb->obj);
-+ mutex_unlock(&dev->struct_mutex);
++ int ret = -ENOMEM;
+
-+ kfree(intel_fb);
-+}
++ DRM_ERROR("Debug is 0x%08x\n", drm_psb_debug);
+
-+static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
-+ struct drm_file *file_priv,
-+ unsigned int *handle)
-+{
-+ struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
-+ struct drm_gem_object *object = intel_fb->obj;
++ dev_priv->ta_mem_pages =
++ PSB_ALIGN_TO(drm_psb_ta_mem_size * 1024, PAGE_SIZE) >> PAGE_SHIFT;
++ dev_priv->comm_page = alloc_page(GFP_KERNEL);
++ if (!dev_priv->comm_page)
++ goto out_err;
+
-+ return drm_gem_handle_create(file_priv, object, handle);
-+}
++ dev_priv->comm = kmap(dev_priv->comm_page);
++ memset((void *)dev_priv->comm, 0, PAGE_SIZE);
+
-+static const struct drm_framebuffer_funcs intel_fb_funcs = {
-+ .destroy = intel_user_framebuffer_destroy,
-+ .create_handle = intel_user_framebuffer_create_handle,
-+};
++ dev_priv->has_msvdx = 1;
++ if (psb_msvdx_init(dev))
++ dev_priv->has_msvdx = 0;
+
-+int intel_framebuffer_create(struct drm_device *dev,
-+ struct drm_mode_fb_cmd *mode_cmd,
-+ struct drm_framebuffer **fb,
-+ struct drm_gem_object *obj)
-+{
-+ struct intel_framebuffer *intel_fb;
-+ int ret;
++ /*
++ * Initialize sequence numbers for the different command
++ * submission mechanisms.
++ */
+
-+ intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
-+ if (!intel_fb)
-+ return -ENOMEM;
++ dev_priv->sequence[PSB_ENGINE_2D] = 0;
++ dev_priv->sequence[PSB_ENGINE_RASTERIZER] = 0;
++ dev_priv->sequence[PSB_ENGINE_TA] = 0;
++ dev_priv->sequence[PSB_ENGINE_HPRAST] = 0;
+
-+ ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
-+ if (ret) {
-+ DRM_ERROR("framebuffer init failed %d\n", ret);
-+ return ret;
++ if (pg->gatt_start & 0x0FFFFFFF) {
++ DRM_ERROR("Gatt must be 256M aligned. This is a bug.\n");
++ ret = -EINVAL;
++ goto out_err;
+ }
+
-+ drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
++ stolen_gtt = (pg->stolen_size >> PAGE_SHIFT) * 4;
++ stolen_gtt = (stolen_gtt + PAGE_SIZE - 1) >> PAGE_SHIFT;
++ stolen_gtt = (stolen_gtt < pg->gtt_pages) ? stolen_gtt : pg->gtt_pages;
+
-+ intel_fb->obj = obj;
++ dev_priv->gatt_free_offset = pg->gatt_start +
++ (stolen_gtt << PAGE_SHIFT) * 1024;
+
-+ *fb = &intel_fb->base;
++ /*
++ * Insert a cache-coherent communications page in mmu space
++ * just after the stolen area. Will be used for fencing etc.
++ */
+
-+ return 0;
-+}
++ dev_priv->comm_mmu_offset = dev_priv->gatt_free_offset;
++ dev_priv->gatt_free_offset += PAGE_SIZE;
++
++ ret = psb_mmu_insert_pages(psb_mmu_get_default_pd(dev_priv->mmu),
++ &dev_priv->comm_page,
++ dev_priv->comm_mmu_offset, 1, 0, 0,
++ PSB_MMU_CACHED_MEMORY);
+
++ if (ret)
++ goto out_err;
+
-+static struct drm_framebuffer *
-+intel_user_framebuffer_create(struct drm_device *dev,
-+ struct drm_file *filp,
-+ struct drm_mode_fb_cmd *mode_cmd)
-+{
-+ struct drm_gem_object *obj;
-+ struct drm_framebuffer *fb;
-+ int ret;
++ if (1 || drm_debug) {
++ uint32_t core_id = PSB_RSGX32(PSB_CR_CORE_ID);
++ uint32_t core_rev = PSB_RSGX32(PSB_CR_CORE_REVISION);
++ DRM_INFO("SGX core id = 0x%08x\n", core_id);
++ DRM_INFO("SGX core rev major = 0x%02x, minor = 0x%02x\n",
++ (core_rev & _PSB_CC_REVISION_MAJOR_MASK) >>
++ _PSB_CC_REVISION_MAJOR_SHIFT,
++ (core_rev & _PSB_CC_REVISION_MINOR_MASK) >>
++ _PSB_CC_REVISION_MINOR_SHIFT);
++ DRM_INFO
++ ("SGX core rev maintenance = 0x%02x, designer = 0x%02x\n",
++ (core_rev & _PSB_CC_REVISION_MAINTENANCE_MASK) >>
++ _PSB_CC_REVISION_MAINTENANCE_SHIFT,
++ (core_rev & _PSB_CC_REVISION_DESIGNER_MASK) >>
++ _PSB_CC_REVISION_DESIGNER_SHIFT);
++ }
+
-+ obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
-+ if (!obj)
-+ return NULL;
++ dev_priv->irqmask_lock = SPIN_LOCK_UNLOCKED;
++ dev_priv->fence0_irq_on = 0;
+
-+ ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
-+ if (ret) {
-+ drm_gem_object_unreference(obj);
-+ return NULL;
++ tt_pages = (pg->gatt_pages < PSB_TT_PRIV0_PLIMIT) ?
++ pg->gatt_pages : PSB_TT_PRIV0_PLIMIT;
++ tt_start = dev_priv->gatt_free_offset - pg->gatt_start;
++ tt_pages -= tt_start >> PAGE_SHIFT;
++
++ mutex_lock(&dev->struct_mutex);
++
++ if (!drm_bo_init_mm(dev, DRM_BO_MEM_VRAM, 0,
++ pg->stolen_size >> PAGE_SHIFT)) {
++ dev_priv->have_vram = 1;
+ }
+
-+ return fb;
-+}
++ if (!drm_bo_init_mm(dev, DRM_BO_MEM_TT, tt_start >> PAGE_SHIFT,
++ tt_pages)) {
++ dev_priv->have_tt = 1;
++ }
+
-+static const struct drm_mode_config_funcs intel_mode_funcs = {
-+ .fb_create = intel_user_framebuffer_create,
-+// .fb_changed = intelfb_probe,
-+};
++ if (!drm_bo_init_mm(dev, DRM_PSB_MEM_MMU, 0x00000000,
++ (pg->gatt_start -
++ PSB_MEM_MMU_START) >> PAGE_SHIFT)) {
++ dev_priv->have_mem_mmu = 1;
++ }
++
++ if (!drm_bo_init_mm(dev, DRM_PSB_MEM_RASTGEOM, 0x00000000,
++ (PSB_MEM_MMU_START -
++ PSB_MEM_RASTGEOM_START) >> PAGE_SHIFT)) {
++ dev_priv->have_mem_rastgeom = 1;
++ }
++#if 0
++ if (pg->gatt_pages > PSB_TT_PRIV0_PLIMIT) {
++ if (!drm_bo_init_mm(dev, DRM_PSB_MEM_APER, PSB_TT_PRIV0_PLIMIT,
++ pg->gatt_pages - PSB_TT_PRIV0_PLIMIT)) {
++ dev_priv->have_mem_aper = 1;
++ }
++ }
++#endif
++
++ mutex_unlock(&dev->struct_mutex);
++
++ return 0;
++ out_err:
++ psb_do_takedown(dev);
++ return ret;
++}
+
-+void intel_modeset_init(struct drm_device *dev)
++static int psb_driver_unload(struct drm_device *dev)
+{
-+ int num_pipe;
-+ int i;
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
+
-+ drm_mode_config_init(dev);
++ intel_modeset_cleanup(dev);
+
-+ dev->mode_config.min_width = 0;
-+ dev->mode_config.min_height = 0;
++ if (dev_priv) {
++ psb_watchdog_takedown(dev_priv);
++ psb_do_takedown(dev);
++ psb_xhw_takedown(dev_priv);
++ psb_scheduler_takedown(&dev_priv->scheduler);
+
-+ dev->mode_config.funcs = (void *)&intel_mode_funcs;
++ mutex_lock(&dev->struct_mutex);
++ if (dev_priv->have_mem_pds) {
++ drm_bo_clean_mm(dev, DRM_PSB_MEM_PDS);
++ dev_priv->have_mem_pds = 0;
++ }
++ if (dev_priv->have_mem_kernel) {
++ drm_bo_clean_mm(dev, DRM_PSB_MEM_KERNEL);
++ dev_priv->have_mem_kernel = 0;
++ }
++ mutex_unlock(&dev->struct_mutex);
+
-+ dev->mode_config.max_width = 2048;
-+ dev->mode_config.max_height = 2048;
++ (void)drm_bo_driver_finish(dev);
+
-+ /* set memory base */
-+ if (IS_I9XX(dev))
-+ dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
-+ else
-+ dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
++ if (dev_priv->pf_pd) {
++ psb_mmu_free_pagedir(dev_priv->pf_pd);
++ dev_priv->pf_pd = NULL;
++ }
++ if (dev_priv->mmu) {
++ struct psb_gtt *pg = dev_priv->pg;
+
-+ if (IS_MOBILE(dev) || IS_I9XX(dev))
-+ num_pipe = 2;
-+ else
-+ num_pipe = 1;
-+ DRM_DEBUG("%d display pipe%s available.\n",
-+ num_pipe, num_pipe > 1 ? "s" : "");
++ down_read(&pg->sem);
++ psb_mmu_remove_pfn_sequence(psb_mmu_get_default_pd
++ (dev_priv->mmu),
++ pg->gatt_start,
++ pg->
++ stolen_size >> PAGE_SHIFT);
++ up_read(&pg->sem);
++ psb_mmu_driver_takedown(dev_priv->mmu);
++ dev_priv->mmu = NULL;
++ }
++ psb_gtt_takedown(dev_priv->pg, 1);
++ if (dev_priv->scratch_page) {
++ __free_page(dev_priv->scratch_page);
++ dev_priv->scratch_page = NULL;
++ }
++ psb_takedown_use_base(dev_priv);
++ if (dev_priv->vdc_reg) {
++ iounmap(dev_priv->vdc_reg);
++ dev_priv->vdc_reg = NULL;
++ }
++ if (dev_priv->sgx_reg) {
++ iounmap(dev_priv->sgx_reg);
++ dev_priv->sgx_reg = NULL;
++ }
++ if (dev_priv->msvdx_reg) {
++ iounmap(dev_priv->msvdx_reg);
++ dev_priv->msvdx_reg = NULL;
++ }
+
-+ for (i = 0; i < num_pipe; i++) {
-+ intel_crtc_init(dev, i);
++ drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
++ dev->dev_private = NULL;
+ }
-+
-+ intel_setup_outputs(dev);
++ return 0;
+}
+
-+void intel_modeset_cleanup(struct drm_device *dev)
-+{
-+ drm_mode_config_cleanup(dev);
-+}
+
++extern int drm_pick_crtcs(struct drm_device *dev);
++extern char drm_init_mode[32];
+
-+/* current intel driver doesn't take advantage of encoders
-+ always give back the encoder for the connector
-+*/
-+struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
++static int psb_initial_config(struct drm_device *dev, bool can_grow)
+{
-+ struct intel_output *intel_output = to_intel_output(connector);
++ struct drm_psb_private *dev_priv = dev->dev_private;
++ struct drm_connector *output;
++ struct drm_crtc *crtc;
++ int ret = false;
+
-+ return &intel_output->enc;
-+}
-Index: linux-2.6.28/drivers/gpu/drm/psb/intel_drv.h
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/psb/intel_drv.h 2009-02-12 09:14:41.000000000 +0000
-@@ -0,0 +1,7 @@
-+#include "../i915/intel_drv.h"
-+extern void intel_modeset_init(struct drm_device *dev);
-+extern void intel_modeset_cleanup(struct drm_device *dev);
++ mutex_lock(&dev->mode_config.mutex);
+
-+extern void intel_crtc_mode_restore(struct drm_crtc *crtc);
-+extern void intel_crtc_mode_save(struct drm_crtc *crtc);
++ drm_helper_probe_connector_modes(dev, 2048, 2048);
+
-Index: linux-2.6.28/drivers/gpu/drm/psb/psb_buffer.c
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/psb/psb_buffer.c 2009-02-12 09:14:41.000000000 +0000
-@@ -0,0 +1,437 @@
-+/**************************************************************************
-+ * Copyright (c) 2007, Intel Corporation.
-+ * All Rights Reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms and conditions of the GNU General Public License,
-+ * version 2, as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
-+ *
-+ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
-+ * develop this driver.
-+ *
-+ **************************************************************************/
-+/*
-+ * Authors: Thomas Hellstrom <thomas-at-tungstengraphics.com>
-+ */
-+#include "drmP.h"
-+#include "psb_drv.h"
-+#include "psb_schedule.h"
++ /* strncpy(drm_init_mode, psb_init_mode, strlen(psb_init_mode)); */
+
-+struct drm_psb_ttm_backend {
-+ struct drm_ttm_backend base;
-+ struct page **pages;
-+ unsigned int desired_tile_stride;
-+ unsigned int hw_tile_stride;
-+ int mem_type;
-+ unsigned long offset;
-+ unsigned long num_pages;
-+};
++ drm_pick_crtcs(dev);
+
-+int psb_fence_types(struct drm_buffer_object *bo, uint32_t * class,
-+ uint32_t * type)
-+{
-+ switch (*class) {
-+ case PSB_ENGINE_TA:
-+ *type = DRM_FENCE_TYPE_EXE |
-+ _PSB_FENCE_TYPE_TA_DONE | _PSB_FENCE_TYPE_RASTER_DONE;
-+ if (bo->mem.mask & PSB_BO_FLAG_TA)
-+ *type &= ~_PSB_FENCE_TYPE_RASTER_DONE;
-+ if (bo->mem.mask & PSB_BO_FLAG_SCENE)
-+ *type |= _PSB_FENCE_TYPE_SCENE_DONE;
-+ if (bo->mem.mask & PSB_BO_FLAG_FEEDBACK)
-+ *type |= _PSB_FENCE_TYPE_FEEDBACK;
-+ break;
-+ default:
-+ *type = DRM_FENCE_TYPE_EXE;
-+ }
-+ return 0;
-+}
++ if ((I915_READ(PIPEACONF) & PIPEACONF_ENABLE) && !drm_psb_force_pipeb)
++ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
++ if (!crtc->desired_mode)
++ continue;
+
-+static inline size_t drm_size_align(size_t size)
-+{
-+ size_t tmpSize = 4;
-+ if (size > PAGE_SIZE)
-+ return PAGE_ALIGN(size);
-+ while (tmpSize < size)
-+ tmpSize <<= 1;
++ dev->driver->fb_probe(dev, crtc);
++ } else
++ list_for_each_entry_reverse(crtc, &dev->mode_config.crtc_list,
++ head) {
++ if (!crtc->desired_mode)
++ continue;
+
-+ return (size_t) tmpSize;
-+}
++ dev->driver->fb_probe(dev, crtc);
++ }
+
-+/*
-+ * Poulsbo GPU virtual space looks like this
-+ * (We currently use only one MMU context).
-+ *
-+ * gatt_start = Start of GATT aperture in bus space.
-+ * stolen_end = End of GATT populated by stolen memory in bus space.
-+ * gatt_end = End of GATT
-+ * twod_end = MIN(gatt_start + 256_MEM, gatt_end)
-+ *
-+ * 0x00000000 -> 0x10000000 Temporary mapping space for tiling- and copy operations.
-+ * This space is not managed and is protected by the
-+ * temp_mem mutex.
-+ *
-+ * 0x10000000 -> 0x20000000 DRM_PSB_MEM_KERNEL For kernel buffers.
-+ *
-+ * 0x20000000 -> gatt_start DRM_PSB_MEM_MMU For generic MMU-only use.
-+ *
-+ * gatt_start -> stolen_end DRM_BO_MEM_VRAM Pre-populated GATT pages.
-+ *
-+ * stolen_end -> twod_end DRM_BO_MEM_TT GATT memory usable by 2D engine.
-+ *
-+ * twod_end -> gatt_end DRM_BO_MEM_APER GATT memory not usable by 2D engine.
-+ *
-+ * gatt_end -> 0xffffffff Currently unused.
-+ */
++ list_for_each_entry(output, &dev->mode_config.connector_list, head) {
+
-+int psb_init_mem_type(struct drm_device *dev, uint32_t type,
-+ struct drm_mem_type_manager *man)
-+{
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
-+ struct psb_gtt *pg = dev_priv->pg;
++ if (!output->encoder->crtc || !output->encoder->crtc->desired_mode)
++ continue;
+
-+ switch (type) {
-+ case DRM_BO_MEM_LOCAL:
-+ man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
-+ _DRM_FLAG_MEMTYPE_CACHED;
-+ man->drm_bus_maptype = 0;
-+ break;
-+ case DRM_PSB_MEM_KERNEL:
-+ man->io_offset = 0x00000000;
-+ man->io_size = 0x00000000;
-+ man->io_addr = NULL;
-+ man->drm_bus_maptype = _DRM_TTM;
-+ man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
-+ _DRM_FLAG_MEMTYPE_CSELECT | _DRM_FLAG_MEMTYPE_CMA;
-+ man->gpu_offset = PSB_MEM_KERNEL_START;
-+ break;
-+ case DRM_PSB_MEM_MMU:
-+ man->io_offset = 0x00000000;
-+ man->io_size = 0x00000000;
-+ man->io_addr = NULL;
-+ man->drm_bus_maptype = _DRM_TTM;
-+ man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
-+ _DRM_FLAG_MEMTYPE_CSELECT | _DRM_FLAG_MEMTYPE_CMA;
-+ man->gpu_offset = PSB_MEM_MMU_START;
-+ break;
-+ case DRM_PSB_MEM_PDS:
-+ man->io_offset = 0x00000000;
-+ man->io_size = 0x00000000;
-+ man->io_addr = NULL;
-+ man->drm_bus_maptype = _DRM_TTM;
-+ man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
-+ _DRM_FLAG_MEMTYPE_CSELECT | _DRM_FLAG_MEMTYPE_CMA;
-+ man->gpu_offset = PSB_MEM_PDS_START;
-+ break;
-+ case DRM_PSB_MEM_RASTGEOM:
-+ man->io_offset = 0x00000000;
-+ man->io_size = 0x00000000;
-+ man->io_addr = NULL;
-+ man->drm_bus_maptype = _DRM_TTM;
-+ man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
-+ _DRM_FLAG_MEMTYPE_CSELECT | _DRM_FLAG_MEMTYPE_CMA;
-+ man->gpu_offset = PSB_MEM_RASTGEOM_START;
-+ break;
-+ case DRM_BO_MEM_VRAM:
-+ man->io_addr = NULL;
-+ man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
-+ _DRM_FLAG_MEMTYPE_FIXED | _DRM_FLAG_NEEDS_IOREMAP;
-+#ifdef PSB_WORKING_HOST_MMU_ACCESS
-+ man->drm_bus_maptype = _DRM_AGP;
-+ man->io_offset = pg->gatt_start;
-+ man->io_size = pg->gatt_pages << PAGE_SHIFT;
-+#else
-+ man->drm_bus_maptype = _DRM_TTM; /* Forces uncached */
-+ man->io_offset = pg->stolen_base;
-+ man->io_size = pg->stolen_size;
-+#endif
-+ man->gpu_offset = pg->gatt_start;
-+ break;
-+ case DRM_BO_MEM_TT: /* Mappable GATT memory */
-+ man->io_offset = pg->gatt_start;
-+ man->io_size = pg->gatt_pages << PAGE_SHIFT;
-+ man->io_addr = NULL;
-+#ifdef PSB_WORKING_HOST_MMU_ACCESS
-+ man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
-+ _DRM_FLAG_MEMTYPE_CSELECT | _DRM_FLAG_NEEDS_IOREMAP;
-+ man->drm_bus_maptype = _DRM_AGP;
-+#else
-+ man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
-+ _DRM_FLAG_MEMTYPE_CSELECT | _DRM_FLAG_MEMTYPE_CMA;
-+ man->drm_bus_maptype = _DRM_TTM;
-+#endif
-+ man->gpu_offset = pg->gatt_start;
-+ break;
-+ case DRM_PSB_MEM_APER: /*MMU memory. Mappable. Not usable for 2D. */
-+ man->io_offset = pg->gatt_start;
-+ man->io_size = pg->gatt_pages << PAGE_SHIFT;
-+ man->io_addr = NULL;
-+#ifdef PSB_WORKING_HOST_MMU_ACCESS
-+ man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
-+ _DRM_FLAG_MEMTYPE_CSELECT | _DRM_FLAG_NEEDS_IOREMAP;
-+ man->drm_bus_maptype = _DRM_AGP;
++ if (output->encoder->crtc->fb)
++ drm_crtc_helper_set_mode(output->encoder->crtc,
++ output->encoder->crtc->desired_mode, 0, 0, NULL);
++ }
++
++#ifdef SII_1392_WA
++ if((SII_1392 != 1) || (drm_psb_no_fb==0))
++ drm_helper_disable_unused_functions(dev);
+#else
-+ man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
-+ _DRM_FLAG_MEMTYPE_CSELECT | _DRM_FLAG_MEMTYPE_CMA;
-+ man->drm_bus_maptype = _DRM_TTM;
++ drm_helper_disable_unused_functions(dev);
+#endif
-+ man->gpu_offset = pg->gatt_start;
-+ break;
-+ default:
-+ DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
-+ return -EINVAL;
-+ }
-+ return 0;
-+}
+
-+uint32_t psb_evict_mask(struct drm_buffer_object * bo)
-+{
-+ switch (bo->mem.mem_type) {
-+ case DRM_BO_MEM_VRAM:
-+ return DRM_BO_FLAG_MEM_TT;
-+ default:
-+ return DRM_BO_FLAG_MEM_LOCAL;
-+ }
-+}
+
-+int psb_invalidate_caches(struct drm_device *dev, uint64_t flags)
-+{
-+ return 0;
++ mutex_unlock(&dev->mode_config.mutex);
++
++ return ret;
++
+}
+
-+static int psb_move_blit(struct drm_buffer_object *bo,
-+ int evict, int no_wait, struct drm_bo_mem_reg *new_mem)
++static void psb_user_framebuffer_destroy(struct drm_framebuffer *fb)
+{
-+ struct drm_bo_mem_reg *old_mem = &bo->mem;
-+ int dir = 0;
++ struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
++ struct drm_device *dev = fb->dev;
+
-+ if ((old_mem->mem_type == new_mem->mem_type) &&
-+ (new_mem->mm_node->start <
-+ old_mem->mm_node->start + old_mem->mm_node->size)) {
-+ dir = 1;
-+ }
++ //if (fb->fbdev)
++ // intelfb_remove(dev, fb);
+
-+ psb_emit_2d_copy_blit(bo->dev,
-+ old_mem->mm_node->start << PAGE_SHIFT,
-+ new_mem->mm_node->start << PAGE_SHIFT,
-+ new_mem->num_pages, dir);
++ drm_framebuffer_cleanup(fb);
++ mutex_lock(&dev->struct_mutex);
++ drm_gem_object_unreference(intel_fb->obj);
++ mutex_unlock(&dev->struct_mutex);
+
-+ return drm_bo_move_accel_cleanup(bo, evict, no_wait, 0,
-+ DRM_FENCE_TYPE_EXE, 0, new_mem);
++ kfree(intel_fb);
+}
+
-+/*
-+ * Flip destination ttm into cached-coherent GATT,
-+ * then blit and subsequently move out again.
-+ */
-+
-+static int psb_move_flip(struct drm_buffer_object *bo,
-+ int evict, int no_wait, struct drm_bo_mem_reg *new_mem)
++static int psb_user_framebuffer_create_handle(struct drm_framebuffer *fb,
++ struct drm_file *file_priv,
++ unsigned int *handle)
+{
-+ struct drm_device *dev = bo->dev;
-+ struct drm_bo_mem_reg tmp_mem;
-+ int ret;
++ struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
++ struct drm_gem_object *object = intel_fb->obj;
+
-+ tmp_mem = *new_mem;
-+ tmp_mem.mm_node = NULL;
-+ tmp_mem.mask = DRM_BO_FLAG_MEM_TT |
-+ DRM_BO_FLAG_CACHED | DRM_BO_FLAG_FORCE_CACHING;
++ return drm_gem_handle_create(file_priv, object, handle);
++}
+
-+ ret = drm_bo_mem_space(bo, &tmp_mem, no_wait);
-+ if (ret)
-+ return ret;
-+ ret = drm_bind_ttm(bo->ttm, &tmp_mem);
-+ if (ret)
-+ goto out_cleanup;
-+ ret = psb_move_blit(bo, 1, no_wait, &tmp_mem);
-+ if (ret)
-+ goto out_cleanup;
-+
-+ ret = drm_bo_move_ttm(bo, evict, no_wait, new_mem);
-+ out_cleanup:
-+ if (tmp_mem.mm_node) {
-+ mutex_lock(&dev->struct_mutex);
-+ if (tmp_mem.mm_node != bo->pinned_node)
-+ drm_mm_put_block(tmp_mem.mm_node);
-+ tmp_mem.mm_node = NULL;
-+ mutex_unlock(&dev->struct_mutex);
-+ }
-+ return ret;
-+}
++static const struct drm_framebuffer_funcs psb_fb_funcs = {
++ .destroy = psb_user_framebuffer_destroy,
++ .create_handle = psb_user_framebuffer_create_handle,
++};
+
-+int psb_move(struct drm_buffer_object *bo,
-+ int evict, int no_wait, struct drm_bo_mem_reg *new_mem)
++int psb_framebuffer_create(struct drm_device *dev,
++ struct drm_mode_fb_cmd *mode_cmd,
++ struct drm_framebuffer **fb,
++ struct drm_gem_object *obj)
+{
-+ struct drm_bo_mem_reg *old_mem = &bo->mem;
++ struct intel_framebuffer *intel_fb;
++ int ret;
+
-+ if (old_mem->mem_type == DRM_BO_MEM_LOCAL) {
-+ return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
-+ } else if (new_mem->mem_type == DRM_BO_MEM_LOCAL) {
-+ if (psb_move_flip(bo, evict, no_wait, new_mem))
-+ return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
-+ } else {
-+ if (psb_move_blit(bo, evict, no_wait, new_mem))
-+ return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
++ intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
++ if (!intel_fb)
++ return -ENOMEM;
++
++ ret = drm_framebuffer_init(dev, &intel_fb->base, &psb_fb_funcs);
++ if (ret) {
++ DRM_ERROR("framebuffer init failed %d\n", ret);
++ return ret;
+ }
-+ return 0;
-+}
+
-+static int drm_psb_tbe_nca(struct drm_ttm_backend *backend)
-+{
-+ return ((backend->flags & DRM_BE_FLAG_BOUND_CACHED) ? 0 : 1);
-+}
++ drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
+
-+static int drm_psb_tbe_populate(struct drm_ttm_backend *backend,
-+ unsigned long num_pages, struct page **pages)
-+{
-+ struct drm_psb_ttm_backend *psb_be =
-+ container_of(backend, struct drm_psb_ttm_backend, base);
++ intel_fb->obj = obj;
++
++ *fb = &intel_fb->base;
+
-+ psb_be->pages = pages;
+ return 0;
+}
+
-+static int drm_psb_tbe_unbind(struct drm_ttm_backend *backend)
-+{
-+ struct drm_device *dev = backend->dev;
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
-+ struct drm_psb_ttm_backend *psb_be =
-+ container_of(backend, struct drm_psb_ttm_backend, base);
-+ struct psb_mmu_pd *pd = psb_mmu_get_default_pd(dev_priv->mmu);
-+ struct drm_mem_type_manager *man = &dev->bm.man[psb_be->mem_type];
+
-+ PSB_DEBUG_RENDER("MMU unbind.\n");
++static struct drm_framebuffer *
++psb_user_framebuffer_create(struct drm_device *dev,
++ struct drm_file *filp,
++ struct drm_mode_fb_cmd *mode_cmd)
++{
++ struct drm_gem_object *obj;
++ struct drm_framebuffer *fb;
++ int ret;
+
-+ if (psb_be->mem_type == DRM_BO_MEM_TT) {
-+ uint32_t gatt_p_offset = (psb_be->offset - man->gpu_offset) >>
-+ PAGE_SHIFT;
++ obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
++ if (!obj)
++ return NULL;
+
-+ (void)psb_gtt_remove_pages(dev_priv->pg, gatt_p_offset,
-+ psb_be->num_pages,
-+ psb_be->desired_tile_stride,
-+ psb_be->hw_tile_stride);
++ ret = psb_framebuffer_create(dev, mode_cmd, &fb, obj);
++ if (ret) {
++ drm_gem_object_unreference(obj);
++ return NULL;
+ }
+
-+ psb_mmu_remove_pages(pd, psb_be->offset,
-+ psb_be->num_pages,
-+ psb_be->desired_tile_stride,
-+ psb_be->hw_tile_stride);
++ return fb;
++}
++
+
++int psbfb_probe2(struct drm_device *dev)
++{
+ return 0;
+}
+
-+static int drm_psb_tbe_bind(struct drm_ttm_backend *backend,
-+ struct drm_bo_mem_reg *bo_mem)
++static const struct drm_mode_config_funcs psb_mode_funcs = {
++ .fb_create = psb_user_framebuffer_create,
++ .fb_changed = psbfb_probe2,
++};
++
++static int psb_driver_load(struct drm_device *dev, unsigned long chipset)
+{
-+ struct drm_device *dev = backend->dev;
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
-+ struct drm_psb_ttm_backend *psb_be =
-+ container_of(backend, struct drm_psb_ttm_backend, base);
-+ struct psb_mmu_pd *pd = psb_mmu_get_default_pd(dev_priv->mmu);
-+ struct drm_mem_type_manager *man = &dev->bm.man[bo_mem->mem_type];
-+ int type;
-+ int ret = 0;
++ struct drm_psb_private *dev_priv;
++ unsigned long resource_start;
++ struct psb_gtt *pg;
++ int ret = -ENOMEM;
+
-+ psb_be->mem_type = bo_mem->mem_type;
-+ psb_be->num_pages = bo_mem->num_pages;
-+ psb_be->desired_tile_stride = bo_mem->desired_tile_stride;
-+ psb_be->hw_tile_stride = bo_mem->hw_tile_stride;
-+ psb_be->desired_tile_stride = 0;
-+ psb_be->hw_tile_stride = 0;
-+ psb_be->offset = (bo_mem->mm_node->start << PAGE_SHIFT) +
-+ man->gpu_offset;
++ DRM_INFO("psb - %s\n", PSB_PACKAGE_VERSION);
++ dev_priv = drm_calloc(1, sizeof(*dev_priv), DRM_MEM_DRIVER);
++ if (dev_priv == NULL)
++ return -ENOMEM;
+
-+ type = (bo_mem->flags & DRM_BO_FLAG_CACHED) ? PSB_MMU_CACHED_MEMORY : 0;
++ mutex_init(&dev_priv->temp_mem);
++ mutex_init(&dev_priv->cmdbuf_mutex);
++ mutex_init(&dev_priv->reset_mutex);
++ psb_init_disallowed();
+
-+ PSB_DEBUG_RENDER("MMU bind.\n");
-+ if (psb_be->mem_type == DRM_BO_MEM_TT) {
-+ uint32_t gatt_p_offset = (psb_be->offset - man->gpu_offset) >>
-+ PAGE_SHIFT;
++ atomic_set(&dev_priv->msvdx_mmu_invaldc, 0);
+
-+ ret = psb_gtt_insert_pages(dev_priv->pg, psb_be->pages,
-+ gatt_p_offset,
-+ psb_be->num_pages,
-+ psb_be->desired_tile_stride,
-+ psb_be->hw_tile_stride, type);
-+ }
++#ifdef FIX_TG_16
++ atomic_set(&dev_priv->lock_2d, 0);
++ atomic_set(&dev_priv->ta_wait_2d, 0);
++ atomic_set(&dev_priv->ta_wait_2d_irq, 0);
++ atomic_set(&dev_priv->waiters_2d, 0);;
++ DRM_INIT_WAITQUEUE(&dev_priv->queue_2d);
++#else
++ mutex_init(&dev_priv->mutex_2d);
++#endif
+
-+ ret = psb_mmu_insert_pages(pd, psb_be->pages,
-+ psb_be->offset, psb_be->num_pages,
-+ psb_be->desired_tile_stride,
-+ psb_be->hw_tile_stride, type);
-+ if (ret)
-+ goto out_err;
++ spin_lock_init(&dev_priv->reloc_lock);
+
-+ DRM_FLAG_MASKED(backend->flags, (bo_mem->flags & DRM_BO_FLAG_CACHED) ?
-+ DRM_BE_FLAG_BOUND_CACHED : 0, DRM_BE_FLAG_BOUND_CACHED);
++ DRM_INIT_WAITQUEUE(&dev_priv->rel_mapped_queue);
++ DRM_INIT_WAITQUEUE(&dev_priv->event_2d_queue);
+
-+ return 0;
-+ out_err:
-+ drm_psb_tbe_unbind(backend);
-+ return ret;
++ dev->dev_private = (void *)dev_priv;
++ dev_priv->chipset = chipset;
++ psb_set_uopt(&dev_priv->uopt);
+
-+}
++ psb_watchdog_init(dev_priv);
++ psb_scheduler_init(dev, &dev_priv->scheduler);
+
-+static void drm_psb_tbe_clear(struct drm_ttm_backend *backend)
-+{
-+ struct drm_psb_ttm_backend *psb_be =
-+ container_of(backend, struct drm_psb_ttm_backend, base);
++ resource_start = pci_resource_start(dev->pdev, PSB_MMIO_RESOURCE);
+
-+ psb_be->pages = NULL;
-+ return;
-+}
++ dev_priv->msvdx_reg =
++ ioremap(resource_start + PSB_MSVDX_OFFSET, PSB_MSVDX_SIZE);
++ if (!dev_priv->msvdx_reg)
++ goto out_err;
+
-+static void drm_psb_tbe_destroy(struct drm_ttm_backend *backend)
-+{
-+ struct drm_psb_ttm_backend *psb_be =
-+ container_of(backend, struct drm_psb_ttm_backend, base);
++ dev_priv->vdc_reg =
++ ioremap(resource_start + PSB_VDC_OFFSET, PSB_VDC_SIZE);
++ if (!dev_priv->vdc_reg)
++ goto out_err;
+
-+ if (backend)
-+ drm_free(psb_be, sizeof(*psb_be), DRM_MEM_TTM);
-+}
++ dev_priv->sgx_reg =
++ ioremap(resource_start + PSB_SGX_OFFSET, PSB_SGX_SIZE);
++ if (!dev_priv->sgx_reg)
++ goto out_err;
+
-+static struct drm_ttm_backend_func psb_ttm_backend = {
-+ .needs_ub_cache_adjust = drm_psb_tbe_nca,
-+ .populate = drm_psb_tbe_populate,
-+ .clear = drm_psb_tbe_clear,
-+ .bind = drm_psb_tbe_bind,
-+ .unbind = drm_psb_tbe_unbind,
-+ .destroy = drm_psb_tbe_destroy,
-+};
++ psb_clockgating(dev_priv);
++ if (psb_init_use_base(dev_priv, 3, 13))
++ goto out_err;
+
-+struct drm_ttm_backend *drm_psb_tbe_init(struct drm_device *dev)
-+{
-+ struct drm_psb_ttm_backend *psb_be;
++ dev_priv->scratch_page = alloc_page(GFP_DMA32 | __GFP_ZERO);
++ if (!dev_priv->scratch_page)
++ goto out_err;
+
-+ psb_be = drm_calloc(1, sizeof(*psb_be), DRM_MEM_TTM);
-+ if (!psb_be)
-+ return NULL;
-+ psb_be->pages = NULL;
-+ psb_be->base.func = &psb_ttm_backend;
-+ psb_be->base.dev = dev;
++ dev_priv->pg = psb_gtt_alloc(dev);
++ if (!dev_priv->pg)
++ goto out_err;
+
-+ return &psb_be->base;
-+}
++ ret = psb_gtt_init(dev_priv->pg, 0);
++ if (ret)
++ goto out_err;
++
++ dev_priv->mmu = psb_mmu_driver_init(dev_priv->sgx_reg,
++ drm_psb_trap_pagefaults, 0,
++ &dev_priv->msvdx_mmu_invaldc);
++ if (!dev_priv->mmu)
++ goto out_err;
++
++ pg = dev_priv->pg;
+
-+int psb_tbe_size(struct drm_device *dev, unsigned long num_pages)
-+{
+ /*
-+ * Return the size of the structures themselves and the
-+ * estimated size of the pagedir and pagetable entries.
++ * Make sgx MMU aware of the stolen memory area we call VRAM.
+ */
+
-+ return drm_size_align(sizeof(struct drm_psb_ttm_backend)) +
-+ 8*num_pages;
-+}
-Index: linux-2.6.28/drivers/gpu/drm/psb/psb_drm.h
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/psb/psb_drm.h 2009-02-12 09:14:41.000000000 +0000
-@@ -0,0 +1,370 @@
-+/**************************************************************************
-+ * Copyright (c) 2007, Intel Corporation.
-+ * All Rights Reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms and conditions of the GNU General Public License,
-+ * version 2, as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
-+ *
-+ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
-+ * develop this driver.
-+ *
-+ **************************************************************************/
-+/*
-+ */
++ down_read(&pg->sem);
++ ret =
++ psb_mmu_insert_pfn_sequence(psb_mmu_get_default_pd(dev_priv->mmu),
++ pg->stolen_base >> PAGE_SHIFT,
++ pg->gatt_start,
++ pg->stolen_size >> PAGE_SHIFT, 0);
++ up_read(&pg->sem);
++ if (ret)
++ goto out_err;
+
-+#ifndef _PSB_DRM_H_
-+#define _PSB_DRM_H_
++ dev_priv->pf_pd = psb_mmu_alloc_pd(dev_priv->mmu, 1, 0);
++ if (!dev_priv->pf_pd)
++ goto out_err;
+
-+#if defined(__linux__) && !defined(__KERNEL__)
-+#include<stdint.h>
-+#endif
++ /*
++ * Make all presumably unused requestors page-fault by making them
++ * use context 1 which does not have any valid mappings.
++ */
+
-+/*
-+ * Intel Poulsbo driver package version.
-+ *
-+ */
-+/* #define PSB_PACKAGE_VERSION "ED"__DATE__*/
-+#define PSB_PACKAGE_VERSION "2.1.0.32L.0019"
++ PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK0);
++ PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK1);
++ PSB_RSGX32(PSB_CR_BIF_BANK1);
+
-+#define DRM_PSB_SAREA_MAJOR 0
-+#define DRM_PSB_SAREA_MINOR 1
-+#define PSB_FIXED_SHIFT 16
++ psb_mmu_set_pd_context(psb_mmu_get_default_pd(dev_priv->mmu), 0);
++ psb_mmu_set_pd_context(dev_priv->pf_pd, 1);
++ psb_mmu_enable_requestor(dev_priv->mmu, _PSB_MMU_ER_MASK);
+
-+/*
-+ * Public memory types.
-+ */
++ psb_init_2d(dev_priv);
+
-+#define DRM_PSB_MEM_MMU DRM_BO_MEM_PRIV1
-+#define DRM_PSB_FLAG_MEM_MMU DRM_BO_FLAG_MEM_PRIV1
-+#define DRM_PSB_MEM_PDS DRM_BO_MEM_PRIV2
-+#define DRM_PSB_FLAG_MEM_PDS DRM_BO_FLAG_MEM_PRIV2
-+#define DRM_PSB_MEM_APER DRM_BO_MEM_PRIV3
-+#define DRM_PSB_FLAG_MEM_APER DRM_BO_FLAG_MEM_PRIV3
-+#define DRM_PSB_MEM_RASTGEOM DRM_BO_MEM_PRIV4
-+#define DRM_PSB_FLAG_MEM_RASTGEOM DRM_BO_FLAG_MEM_PRIV4
-+#define PSB_MEM_RASTGEOM_START 0x30000000
++ ret = drm_bo_driver_init(dev);
++ if (ret)
++ goto out_err;
+
-+typedef int32_t psb_fixed;
-+typedef uint32_t psb_ufixed;
++ ret = drm_bo_init_mm(dev, DRM_PSB_MEM_KERNEL, 0x00000000,
++ (PSB_MEM_PDS_START - PSB_MEM_KERNEL_START)
++ >> PAGE_SHIFT);
++ if (ret)
++ goto out_err;
++ dev_priv->have_mem_kernel = 1;
+
-+static inline psb_fixed psb_int_to_fixed(int a)
-+{
-+ return a * (1 << PSB_FIXED_SHIFT);
-+}
++ ret = drm_bo_init_mm(dev, DRM_PSB_MEM_PDS, 0x00000000,
++ (PSB_MEM_RASTGEOM_START - PSB_MEM_PDS_START)
++ >> PAGE_SHIFT);
++ if (ret)
++ goto out_err;
++ dev_priv->have_mem_pds = 1;
+
-+static inline psb_ufixed psb_unsigned_to_ufixed(unsigned int a)
-+{
-+ return a << PSB_FIXED_SHIFT;
-+}
++ ret = psb_do_init(dev);
++ if (ret)
++ return ret;
+
-+/*Status of the command sent to the gfx device.*/
-+typedef enum {
-+ DRM_CMD_SUCCESS,
-+ DRM_CMD_FAILED,
-+ DRM_CMD_HANG
-+} drm_cmd_status_t;
++ ret = psb_xhw_init(dev);
++ if (ret)
++ return ret;
+
-+struct drm_psb_scanout {
-+ uint32_t buffer_id; /* DRM buffer object ID */
-+ uint32_t rotation; /* Rotation as in RR_rotation definitions */
-+ uint32_t stride; /* Buffer stride in bytes */
-+ uint32_t depth; /* Buffer depth in bits (NOT) bpp */
-+ uint32_t width; /* Buffer width in pixels */
-+ uint32_t height; /* Buffer height in lines */
-+ psb_fixed transform[3][3]; /* Buffer composite transform */
-+ /* (scaling, rot, reflect) */
-+};
++ PSB_WSGX32(PSB_MEM_PDS_START, PSB_CR_PDS_EXEC_BASE);
++ PSB_WSGX32(PSB_MEM_RASTGEOM_START, PSB_CR_BIF_3D_REQ_BASE);
+
-+#define DRM_PSB_SAREA_OWNERS 16
-+#define DRM_PSB_SAREA_OWNER_2D 0
-+#define DRM_PSB_SAREA_OWNER_3D 1
++ intel_modeset_init(dev);
+
-+#define DRM_PSB_SAREA_SCANOUTS 3
++ dev->mode_config.funcs = (void *)&psb_mode_funcs;
+
-+struct drm_psb_sarea {
-+ /* Track changes of this data structure */
++ drm_helper_initial_config(dev, false);
+
-+ uint32_t major;
-+ uint32_t minor;
+
-+ /* Last context to touch part of hw */
-+ uint32_t ctx_owners[DRM_PSB_SAREA_OWNERS];
++#ifdef USE_PAT_WC
++#warning Init pat
++ register_cpu_notifier(&psb_nb);
++#endif
+
-+ /* Definition of front- and rotated buffers */
-+ uint32_t num_scanouts;
-+ struct drm_psb_scanout scanouts[DRM_PSB_SAREA_SCANOUTS];
++ return 0;
++ out_err:
++ psb_driver_unload(dev);
++ return ret;
++}
+
-+ int pipeA_x;
-+ int pipeA_y;
-+ int pipeA_w;
-+ int pipeA_h;
-+ int pipeB_x;
-+ int pipeB_y;
-+ int pipeB_w;
-+ int pipeB_h;
-+ uint32_t msvdx_state;
-+ uint32_t msvdx_context;
-+};
++int psb_driver_device_is_agp(struct drm_device *dev)
++{
++ return 0;
++}
+
-+#define PSB_RELOC_MAGIC 0x67676767
-+#define PSB_RELOC_SHIFT_MASK 0x0000FFFF
-+#define PSB_RELOC_SHIFT_SHIFT 0
-+#define PSB_RELOC_ALSHIFT_MASK 0xFFFF0000
-+#define PSB_RELOC_ALSHIFT_SHIFT 16
++static int psb_prepare_msvdx_suspend(struct drm_device *dev)
++{
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
++ struct drm_fence_manager *fm = &dev->fm;
++ struct drm_fence_class_manager *fc = &fm->fence_class[PSB_ENGINE_VIDEO];
++ struct drm_fence_object *fence;
++ int ret = 0;
++ int signaled = 0;
++ int count = 0;
++ unsigned long _end = jiffies + 3 * DRM_HZ;
+
-+#define PSB_RELOC_OP_OFFSET 0 /* Offset of the indicated
-+ * buffer
-+ */
-+#define PSB_RELOC_OP_2D_OFFSET 1 /* Offset of the indicated
-+ * buffer, relative to 2D
-+ * base address
-+ */
-+#define PSB_RELOC_OP_PDS_OFFSET 2 /* Offset of the indicated buffer,
-+ * relative to PDS base address
-+ */
-+#define PSB_RELOC_OP_STRIDE 3 /* Stride of the indicated
-+ * buffer (for tiling)
-+ */
-+#define PSB_RELOC_OP_USE_OFFSET 4 /* Offset of USE buffer
-+ * relative to base reg
-+ */
-+#define PSB_RELOC_OP_USE_REG 5 /* Base reg of USE buffer */
++ PSB_DEBUG_GENERAL("MSVDXACPI Entering psb_prepare_msvdx_suspend....\n");
+
-+struct drm_psb_reloc {
-+ uint32_t reloc_op;
-+ uint32_t where; /* offset in destination buffer */
-+ uint32_t buffer; /* Buffer reloc applies to */
-+ uint32_t mask; /* Destination format: */
-+ uint32_t shift; /* Destination format: */
-+ uint32_t pre_add; /* Destination format: */
-+ uint32_t background; /* Destination add */
-+ uint32_t dst_buffer; /* Destination buffer. Index into buffer_list */
-+ uint32_t arg0; /* Reloc-op dependant */
-+ uint32_t arg1;
-+};
++ /*set the msvdx-reset flag here.. */
++ dev_priv->msvdx_needs_reset = 1;
+
-+#define PSB_BO_FLAG_TA (1ULL << 48)
-+#define PSB_BO_FLAG_SCENE (1ULL << 49)
-+#define PSB_BO_FLAG_FEEDBACK (1ULL << 50)
-+#define PSB_BO_FLAG_USSE (1ULL << 51)
++ /*Ensure that all pending IRQs are serviced, */
++ list_for_each_entry(fence, &fc->ring, ring) {
++ count++;
++ do {
++ DRM_WAIT_ON(ret, fc->fence_queue, 3 * DRM_HZ,
++ (signaled =
++ drm_fence_object_signaled(fence,
++ DRM_FENCE_TYPE_EXE)));
++ if (signaled)
++ break;
++ if (time_after_eq(jiffies, _end))
++ PSB_DEBUG_GENERAL
++ ("MSVDXACPI: fence 0x%x didn't get signaled for 3 secs; we will suspend anyways\n",
++ (unsigned int)fence);
++ } while (ret == -EINTR);
+
-+#define PSB_ENGINE_2D 0
-+#define PSB_ENGINE_VIDEO 1
-+#define PSB_ENGINE_RASTERIZER 2
-+#define PSB_ENGINE_TA 3
-+#define PSB_ENGINE_HPRAST 4
++ }
+
-+/*
-+ * For this fence class we have a couple of
-+ * fence types.
-+ */
++ /* Issue software reset */
++ PSB_WMSVDX32 (msvdx_sw_reset_all, MSVDX_CONTROL);
+
-+#define _PSB_FENCE_EXE_SHIFT 0
-+#define _PSB_FENCE_TA_DONE_SHIFT 1
-+#define _PSB_FENCE_RASTER_DONE_SHIFT 2
-+#define _PSB_FENCE_SCENE_DONE_SHIFT 3
-+#define _PSB_FENCE_FEEDBACK_SHIFT 4
++ ret = psb_wait_for_register (dev_priv, MSVDX_CONTROL, 0,
++ MSVDX_CONTROL_CR_MSVDX_SOFT_RESET_MASK);
+
-+#define _PSB_ENGINE_TA_FENCE_TYPES 5
-+#define _PSB_FENCE_TYPE_TA_DONE (1 << _PSB_FENCE_TA_DONE_SHIFT)
-+#define _PSB_FENCE_TYPE_RASTER_DONE (1 << _PSB_FENCE_RASTER_DONE_SHIFT)
-+#define _PSB_FENCE_TYPE_SCENE_DONE (1 << _PSB_FENCE_SCENE_DONE_SHIFT)
-+#define _PSB_FENCE_TYPE_FEEDBACK (1 << _PSB_FENCE_FEEDBACK_SHIFT)
++ PSB_DEBUG_GENERAL("MSVDXACPI: All MSVDX IRQs (%d) serviced...\n",
++ count);
++ return 0;
++}
+
-+#define PSB_ENGINE_HPRAST 4
-+#define PSB_NUM_ENGINES 5
++static int psb_suspend(struct pci_dev *pdev, pm_message_t state)
++{
++ struct drm_device *dev = pci_get_drvdata(pdev);
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
++ struct drm_connector *output;
+
-+#define PSB_TA_FLAG_FIRSTPASS (1 << 0)
-+#define PSB_TA_FLAG_LASTPASS (1 << 1)
++ if (drm_psb_no_fb == 0)
++ psbfb_suspend(dev);
++ else {
++ if(num_registered_fb)
++ {
++ list_for_each_entry(output, &dev->mode_config.connector_list, head) {
++ //if(output->encoder->crtc != NULL)
++ // intel_crtc_mode_save(output->encoder->crtc);
++ //if(output->funcs->save)
++ // output->funcs->save(output);
++ }
++ }
++ }
+
-+#define PSB_FEEDBACK_OP_VISTEST (1 << 0)
++ dev_priv->saveCLOCKGATING = PSB_RSGX32(PSB_CR_CLKGATECTL);
++ (void)psb_idle_3d(dev);
++ (void)psb_idle_2d(dev);
++ flush_scheduled_work();
+
-+struct drm_psb_scene {
-+ int handle_valid;
-+ uint32_t handle;
-+ uint32_t w;
-+ uint32_t h;
-+ uint32_t num_buffers;
-+};
++ psb_takedown_use_base(dev_priv);
+
-+struct drm_psb_hw_info
-+{
-+ uint32_t rev_id;
-+ uint32_t caps;
-+};
++ if (dev_priv->has_msvdx)
++ psb_prepare_msvdx_suspend(dev);
+
-+typedef struct drm_psb_cmdbuf_arg {
-+ uint64_t buffer_list; /* List of buffers to validate */
-+ uint64_t clip_rects; /* See i915 counterpart */
-+ uint64_t scene_arg;
-+ uint64_t fence_arg;
++ pci_save_state(pdev);
++ pci_disable_device(pdev);
++ pci_set_power_state(pdev, PCI_D3hot);
+
-+ uint32_t ta_flags;
++ return 0;
++}
+
-+ uint32_t ta_handle; /* TA reg-value pairs */
-+ uint32_t ta_offset;
-+ uint32_t ta_size;
++static int psb_resume(struct pci_dev *pdev)
++{
++ struct drm_device *dev = pci_get_drvdata(pdev);
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
++ struct psb_gtt *pg = dev_priv->pg;
++ struct drm_connector *output;
++ int ret;
+
-+ uint32_t oom_handle;
-+ uint32_t oom_offset;
-+ uint32_t oom_size;
++ pci_set_power_state(pdev, PCI_D0);
++ pci_restore_state(pdev);
++ ret = pci_enable_device(pdev);
++ if (ret)
++ return ret;
+
-+ uint32_t cmdbuf_handle; /* 2D Command buffer object or, */
-+ uint32_t cmdbuf_offset; /* rasterizer reg-value pairs */
-+ uint32_t cmdbuf_size;
++#ifdef USE_PAT_WC
++#warning Init pat
++ /* for single CPU's we do it here, then for more than one CPU we
++ * use the CPU notifier to reinit PAT on those CPU's.
++ */
++ drm_init_pat();
++#endif
+
-+ uint32_t reloc_handle; /* Reloc buffer object */
-+ uint32_t reloc_offset;
-+ uint32_t num_relocs;
++ INIT_LIST_HEAD(&dev_priv->resume_buf.head);
++ dev_priv->msvdx_needs_reset = 1;
+
-+ int32_t damage; /* Damage front buffer with cliprects */
-+ /* Not implemented yet */
-+ uint32_t fence_flags;
-+ uint32_t engine;
++ PSB_WVDC32(pg->pge_ctl | _PSB_PGETBL_ENABLED, PSB_PGETBL_CTL);
++ pci_write_config_word(pdev, PSB_GMCH_CTRL,
++ pg->gmch_ctrl | _PSB_GMCH_ENABLED);
+
+ /*
-+ * Feedback;
++ * The GTT page tables are probably not saved.
++ * However, TT and VRAM is empty at this point.
+ */
+
-+ uint32_t feedback_ops;
-+ uint32_t feedback_handle;
-+ uint32_t feedback_offset;
-+ uint32_t feedback_breakpoints;
-+ uint32_t feedback_size;
-+} drm_psb_cmdbuf_arg_t;
++ psb_gtt_init(dev_priv->pg, 1);
+
-+struct drm_psb_xhw_init_arg {
-+ uint32_t operation;
-+ uint32_t buffer_handle;
-+};
++ /*
++ * The SGX loses it's register contents.
++ * Restore BIF registers. The MMU page tables are
++ * "normal" pages, so their contents should be kept.
++ */
+
-+/*
-+ * Feedback components:
-+ */
++ PSB_WSGX32(dev_priv->saveCLOCKGATING, PSB_CR_CLKGATECTL);
++ PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK0);
++ PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK1);
++ PSB_RSGX32(PSB_CR_BIF_BANK1);
+
-+/*
-+ * Vistest component. The number of these in the feedback buffer
-+ * equals the number of vistest breakpoints + 1.
-+ * This is currently the only feedback component.
-+ */
++ psb_mmu_set_pd_context(psb_mmu_get_default_pd(dev_priv->mmu), 0);
++ psb_mmu_set_pd_context(dev_priv->pf_pd, 1);
++ psb_mmu_enable_requestor(dev_priv->mmu, _PSB_MMU_ER_MASK);
+
-+struct drm_psb_vistest {
-+ uint32_t vt[8];
-+};
++ /*
++ * 2D Base registers..
++ */
++ psb_init_2d(dev_priv);
+
-+#define PSB_HW_COOKIE_SIZE 16
-+#define PSB_HW_FEEDBACK_SIZE 8
-+#define PSB_HW_OOM_CMD_SIZE 6
++ if (drm_psb_no_fb == 0) {
++ list_for_each_entry(output, &dev->mode_config.connector_list, head) {
++ if(output->encoder->crtc != NULL)
++ drm_crtc_helper_set_mode(output->encoder->crtc, &output->encoder->crtc->mode,
++ output->encoder->crtc->x, output->encoder->crtc->y, NULL);
++ }
++ }
+
-+struct drm_psb_xhw_arg {
-+ uint32_t op;
-+ int ret;
-+ uint32_t irq_op;
-+ uint32_t issue_irq;
-+ uint32_t cookie[PSB_HW_COOKIE_SIZE];
-+ union {
-+ struct {
-+ uint32_t w;
-+ uint32_t h;
-+ uint32_t size;
-+ uint32_t clear_p_start;
-+ uint32_t clear_num_pages;
-+ } si;
-+ struct {
-+ uint32_t fire_flags;
-+ uint32_t hw_context;
-+ uint32_t offset;
-+ uint32_t engine;
-+ uint32_t flags;
-+ uint32_t rca;
-+ uint32_t num_oom_cmds;
-+ uint32_t oom_cmds[PSB_HW_OOM_CMD_SIZE];
-+ } sb;
-+ struct {
-+ uint32_t pages;
-+ uint32_t size;
-+ } bi;
-+ struct {
-+ uint32_t bca;
-+ uint32_t rca;
-+ uint32_t flags;
-+ } oom;
-+ struct {
-+ uint32_t pt_offset;
-+ uint32_t param_offset;
-+ uint32_t flags;
-+ } bl;
-+ struct {
-+ uint32_t value;
-+ } cl;
-+ uint32_t feedback[PSB_HW_FEEDBACK_SIZE];
-+ } arg;
-+};
++ /*
++ * Persistant 3D base registers and USSE base registers..
++ */
+
-+#define DRM_PSB_CMDBUF 0x00
-+#define DRM_PSB_XHW_INIT 0x01
-+#define DRM_PSB_XHW 0x02
-+#define DRM_PSB_SCENE_UNREF 0x03
-+/* Controlling the kernel modesetting buffers */
-+#define DRM_PSB_KMS_OFF 0x04
-+#define DRM_PSB_KMS_ON 0x05
-+#define DRM_PSB_HW_INFO 0x06
++ PSB_WSGX32(PSB_MEM_PDS_START, PSB_CR_PDS_EXEC_BASE);
++ PSB_WSGX32(PSB_MEM_RASTGEOM_START, PSB_CR_BIF_3D_REQ_BASE);
++ psb_init_use_base(dev_priv, 3, 13);
+
-+#define PSB_XHW_INIT 0x00
-+#define PSB_XHW_TAKEDOWN 0x01
++ /*
++ * Now, re-initialize the 3D engine.
++ */
+
-+#define PSB_XHW_FIRE_RASTER 0x00
-+#define PSB_XHW_SCENE_INFO 0x01
-+#define PSB_XHW_SCENE_BIND_FIRE 0x02
-+#define PSB_XHW_TA_MEM_INFO 0x03
-+#define PSB_XHW_RESET_DPM 0x04
-+#define PSB_XHW_OOM 0x05
-+#define PSB_XHW_TERMINATE 0x06
-+#define PSB_XHW_VISTEST 0x07
-+#define PSB_XHW_RESUME 0x08
-+#define PSB_XHW_TA_MEM_LOAD 0x09
-+#define PSB_XHW_CHECK_LOCKUP 0x0a
++ psb_xhw_resume(dev_priv, &dev_priv->resume_buf);
+
-+#define PSB_SCENE_FLAG_DIRTY (1 << 0)
-+#define PSB_SCENE_FLAG_COMPLETE (1 << 1)
-+#define PSB_SCENE_FLAG_SETUP (1 << 2)
-+#define PSB_SCENE_FLAG_SETUP_ONLY (1 << 3)
-+#define PSB_SCENE_FLAG_CLEARED (1 << 4)
++ psb_scheduler_ta_mem_check(dev_priv);
++ if (dev_priv->ta_mem && !dev_priv->force_ta_mem_load) {
++ psb_xhw_ta_mem_load(dev_priv, &dev_priv->resume_buf,
++ PSB_TA_MEM_FLAG_TA |
++ PSB_TA_MEM_FLAG_RASTER |
++ PSB_TA_MEM_FLAG_HOSTA |
++ PSB_TA_MEM_FLAG_HOSTD |
++ PSB_TA_MEM_FLAG_INIT,
++ dev_priv->ta_mem->ta_memory->offset,
++ dev_priv->ta_mem->hw_data->offset,
++ dev_priv->ta_mem->hw_cookie);
++ }
+
-+#define PSB_TA_MEM_FLAG_TA (1 << 0)
-+#define PSB_TA_MEM_FLAG_RASTER (1 << 1)
-+#define PSB_TA_MEM_FLAG_HOSTA (1 << 2)
-+#define PSB_TA_MEM_FLAG_HOSTD (1 << 3)
-+#define PSB_TA_MEM_FLAG_INIT (1 << 4)
-+#define PSB_TA_MEM_FLAG_NEW_PT_OFFSET (1 << 5)
++ if (drm_psb_no_fb == 0)
++ psbfb_resume(dev);
+
-+/*Raster fire will deallocate memory */
-+#define PSB_FIRE_FLAG_RASTER_DEALLOC (1 << 0)
-+/*Isp reset needed due to change in ZLS format */
-+#define PSB_FIRE_FLAG_NEEDS_ISP_RESET (1 << 1)
-+/*These are set by Xpsb. */
-+#define PSB_FIRE_FLAG_XHW_MASK 0xff000000
-+/*The task has had at least one OOM and Xpsb will
-+ send back messages on each fire. */
-+#define PSB_FIRE_FLAG_XHW_OOM (1 << 24)
++ else {
++ if(num_registered_fb)
++ {
++ struct fb_info *fb_info=registered_fb[0];
++ list_for_each_entry(output, &dev->mode_config.connector_list, head) {
++ //if(output->encoder->crtc != NULL)
++ // intel_crtc_mode_restore(output->encoder->crtc);
++ }
++ if(fb_info)
++ {
++ fb_set_suspend(fb_info, 0);
++ printk("set the fb_set_suspend resume end\n");
++ }
++ }
++ }
+
-+#define PSB_SCENE_ENGINE_TA 0
-+#define PSB_SCENE_ENGINE_RASTER 1
-+#define PSB_SCENE_NUM_ENGINES 2
+
-+struct drm_psb_dev_info_arg {
-+ uint32_t num_use_attribute_registers;
++ return 0;
++}
++
++/* always available as we are SIGIO'd */
++static unsigned int psb_poll(struct file *filp, struct poll_table_struct *wait)
++{
++ return (POLLIN | POLLRDNORM);
++}
++
++static int psb_release(struct inode *inode, struct file *filp)
++{
++ struct drm_file *file_priv = (struct drm_file *)filp->private_data;
++ struct drm_device *dev = file_priv->minor->dev;
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
++
++ if (dev_priv && dev_priv->xhw_file) {
++ psb_xhw_init_takedown(dev_priv, file_priv, 1);
++ }
++ return drm_release(inode, filp);
++}
++
++extern struct drm_fence_driver psb_fence_driver;
++
++/*
++ * Use this memory type priority if no eviction is needed.
++ */
++static uint32_t psb_mem_prios[] = { DRM_BO_MEM_VRAM,
++ DRM_BO_MEM_TT,
++ DRM_PSB_MEM_KERNEL,
++ DRM_PSB_MEM_MMU,
++ DRM_PSB_MEM_RASTGEOM,
++ DRM_PSB_MEM_PDS,
++ DRM_PSB_MEM_APER,
++ DRM_BO_MEM_LOCAL
+};
-+#define DRM_PSB_DEVINFO 0x01
+
-+#endif
-Index: linux-2.6.28/drivers/gpu/drm/psb/psb_drv.c
++/*
++ * Use this memory type priority if need to evict.
++ */
++static uint32_t psb_busy_prios[] = { DRM_BO_MEM_TT,
++ DRM_BO_MEM_VRAM,
++ DRM_PSB_MEM_KERNEL,
++ DRM_PSB_MEM_MMU,
++ DRM_PSB_MEM_RASTGEOM,
++ DRM_PSB_MEM_PDS,
++ DRM_PSB_MEM_APER,
++ DRM_BO_MEM_LOCAL
++};
++
++static struct drm_bo_driver psb_bo_driver = {
++ .mem_type_prio = psb_mem_prios,
++ .mem_busy_prio = psb_busy_prios,
++ .num_mem_type_prio = ARRAY_SIZE(psb_mem_prios),
++ .num_mem_busy_prio = ARRAY_SIZE(psb_busy_prios),
++ .create_ttm_backend_entry = drm_psb_tbe_init,
++ .fence_type = psb_fence_types,
++ .invalidate_caches = psb_invalidate_caches,
++ .init_mem_type = psb_init_mem_type,
++ .evict_mask = psb_evict_mask,
++ .move = psb_move,
++ .backend_size = psb_tbe_size,
++ .command_stream_barrier = NULL,
++};
++
++static struct drm_driver driver = {
++ .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
++ DRIVER_IRQ_VBL | DRIVER_IRQ_VBL2,
++ .load = psb_driver_load,
++ .unload = psb_driver_unload,
++ .dri_library_name = dri_library_name,
++ .get_reg_ofs = drm_core_get_reg_ofs,
++ .ioctls = psb_ioctls,
++ .device_is_agp = psb_driver_device_is_agp,
++ .vblank_wait = psb_vblank_wait,
++ .vblank_wait2 = psb_vblank_wait2,
++ .irq_preinstall = psb_irq_preinstall,
++ .irq_postinstall = psb_irq_postinstall,
++ .irq_uninstall = psb_irq_uninstall,
++ .irq_handler = psb_irq_handler,
++ .fb_probe = psbfb_probe,
++ .fb_remove = psbfb_remove,
++ .firstopen = NULL,
++ .lastclose = psb_lastclose,
++ .fops = {
++ .owner = THIS_MODULE,
++ .open = drm_open,
++ .release = psb_release,
++ .ioctl = drm_ioctl,
++ .mmap = drm_mmap,
++ .poll = psb_poll,
++ .fasync = drm_fasync,
++ },
++ .pci_driver = {
++ .name = DRIVER_NAME,
++ .id_table = pciidlist,
++ .probe = probe,
++ .remove = __devexit_p(drm_cleanup_pci),
++ .resume = psb_resume,
++ .suspend = psb_suspend,
++ },
++ .fence_driver = &psb_fence_driver,
++ .bo_driver = &psb_bo_driver,
++ .name = DRIVER_NAME,
++ .desc = DRIVER_DESC,
++ .date = PSB_DRM_DRIVER_DATE,
++ .major = PSB_DRM_DRIVER_MAJOR,
++ .minor = PSB_DRM_DRIVER_MINOR,
++ .patchlevel = PSB_DRM_DRIVER_PATCHLEVEL
++};
++
++static int probe(struct pci_dev *pdev, const struct pci_device_id *ent)
++{
++ return drm_get_dev(pdev, ent, &driver);
++}
++
++static int __init psb_init(void)
++{
++ driver.num_ioctls = psb_max_ioctl;
++
++ return drm_init(&driver);
++}
++
++static void __exit psb_exit(void)
++{
++ drm_exit(&driver);
++}
++
++module_init(psb_init);
++module_exit(psb_exit);
++
++MODULE_AUTHOR(DRIVER_AUTHOR);
++MODULE_DESCRIPTION(DRIVER_DESC);
++MODULE_LICENSE("GPL");
+Index: linux-2.6.28/drivers/gpu/drm/psb/psb_drv.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/psb/psb_drv.c 2009-02-12 09:14:41.000000000 +0000
-@@ -0,0 +1,1096 @@
++++ linux-2.6.28/drivers/gpu/drm/psb/psb_drv.h 2009-02-12 10:10:55.000000000 +0000
+@@ -0,0 +1,549 @@
+/**************************************************************************
+ * Copyright (c) 2007, Intel Corporation.
+ * All Rights Reserved.
+ **************************************************************************/
+/*
+ */
++#ifndef _PSB_DRV_H_
++#define _PSB_DRV_H_
+
+#include "drmP.h"
-+#include "drm.h"
+#include "psb_drm.h"
-+#include "psb_drv.h"
+#include "psb_reg.h"
-+#include "i915_reg.h"
-+#include "psb_msvdx.h"
-+#include "drm_pciids.h"
-+#include "psb_scene.h"
-+#include "drm_crtc.h"
-+#include "drm_crtc_helper.h"
-+#include <linux/cpu.h>
-+#include <linux/notifier.h>
-+#include <linux/fb.h>
++#include "psb_schedule.h"
++#include "psb_priv.h"
++#include "../i915/intel_drv.h"
+
-+extern int drm_helper_probe_connector_modes(struct drm_device *dev, uint32_t maxX, uint32_t maxY);
+
-+int drm_psb_debug = 0;
-+EXPORT_SYMBOL(drm_psb_debug);
-+static int drm_psb_trap_pagefaults = 0;
-+static int drm_psb_clock_gating = 0;
-+static int drm_psb_ta_mem_size = 32 * 1024;
-+int drm_psb_disable_vsync = 1;
-+int drm_psb_no_fb = 0;
-+int drm_psb_force_pipeb = 0;
-+char* psb_init_mode;
++enum {
++ CHIP_PSB_8108 = 0,
++ CHIP_PSB_8109 = 1
++};
++
+/*
-+ *
++ * Hardware bugfixes
+ */
-+#define SII_1392_WA
-+#ifdef SII_1392_WA
-+extern int SII_1392;
-+#endif
+
-+MODULE_PARM_DESC(debug, "Enable debug output");
-+MODULE_PARM_DESC(clock_gating, "clock gating");
-+MODULE_PARM_DESC(no_fb, "Disable FBdev");
-+MODULE_PARM_DESC(trap_pagefaults, "Error and reset on MMU pagefaults");
-+MODULE_PARM_DESC(disable_vsync, "Disable vsync interrupts");
-+MODULE_PARM_DESC(force_pipeb, "Forces PIPEB to become primary fb");
-+MODULE_PARM_DESC(ta_mem_size, "TA memory size in kiB");
-+MODULE_PARM_DESC(mode, "initial mode name");
-+MODULE_PARM_DESC(xres, "initial mode width");
-+MODULE_PARM_DESC(yres, "initial mode height");
++#define FIX_TG_16
++#define FIX_TG_2D_CLOCKGATE
+
-+module_param_named(debug, drm_psb_debug, int, 0600);
-+module_param_named(clock_gating, drm_psb_clock_gating, int, 0600);
-+module_param_named(no_fb, drm_psb_no_fb, int, 0600);
-+module_param_named(trap_pagefaults, drm_psb_trap_pagefaults, int, 0600);
-+module_param_named(disable_vsync, drm_psb_disable_vsync, int, 0600);
-+module_param_named(force_pipeb, drm_psb_force_pipeb, int, 0600);
-+module_param_named(ta_mem_size, drm_psb_ta_mem_size, int, 0600);
-+module_param_named(mode, psb_init_mode, charp, 0600);
++#define DRIVER_NAME "psb"
++#define DRIVER_DESC "drm driver for the Intel GMA500"
++#define DRIVER_AUTHOR "Tungsten Graphics Inc."
+
-+static struct pci_device_id pciidlist[] = {
-+ psb_PCI_IDS
-+};
++#define PSB_DRM_DRIVER_DATE "20080613"
++#define PSB_DRM_DRIVER_MAJOR 4
++#define PSB_DRM_DRIVER_MINOR 12
++#define PSB_DRM_DRIVER_PATCHLEVEL 0
+
-+#define DRM_PSB_CMDBUF_IOCTL DRM_IOW(DRM_PSB_CMDBUF, \
-+ struct drm_psb_cmdbuf_arg)
-+#define DRM_PSB_XHW_INIT_IOCTL DRM_IOR(DRM_PSB_XHW_INIT, \
-+ struct drm_psb_xhw_init_arg)
-+#define DRM_PSB_XHW_IOCTL DRM_IO(DRM_PSB_XHW)
++#define PSB_VDC_OFFSET 0x00000000
++#define PSB_VDC_SIZE 0x000080000
++#define PSB_SGX_SIZE 0x8000
++#define PSB_SGX_OFFSET 0x00040000
++#define PSB_MMIO_RESOURCE 0
++#define PSB_GATT_RESOURCE 2
++#define PSB_GTT_RESOURCE 3
++#define PSB_GMCH_CTRL 0x52
++#define PSB_BSM 0x5C
++#define _PSB_GMCH_ENABLED 0x4
++#define PSB_PGETBL_CTL 0x2020
++#define _PSB_PGETBL_ENABLED 0x00000001
++#define PSB_SGX_2D_SLAVE_PORT 0x4000
++#define PSB_TT_PRIV0_LIMIT (256*1024*1024)
++#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
++#define PSB_NUM_VALIDATE_BUFFERS 1024
++#define PSB_MEM_KERNEL_START 0x10000000
++#define PSB_MEM_PDS_START 0x20000000
++#define PSB_MEM_MMU_START 0x40000000
+
-+#define DRM_PSB_SCENE_UNREF_IOCTL DRM_IOWR(DRM_PSB_SCENE_UNREF, \
-+ struct drm_psb_scene)
-+#define DRM_PSB_HW_INFO_IOCTL DRM_IOR(DRM_PSB_HW_INFO, \
-+ struct drm_psb_hw_info)
++#define DRM_PSB_MEM_KERNEL DRM_BO_MEM_PRIV0
++#define DRM_PSB_FLAG_MEM_KERNEL DRM_BO_FLAG_MEM_PRIV0
+
-+#define DRM_PSB_KMS_OFF_IOCTL DRM_IO(DRM_PSB_KMS_OFF)
-+#define DRM_PSB_KMS_ON_IOCTL DRM_IO(DRM_PSB_KMS_ON)
-+
-+static struct drm_ioctl_desc psb_ioctls[] = {
-+ DRM_IOCTL_DEF(DRM_PSB_CMDBUF_IOCTL, psb_cmdbuf_ioctl, DRM_AUTH),
-+ DRM_IOCTL_DEF(DRM_PSB_XHW_INIT_IOCTL, psb_xhw_init_ioctl,
-+ DRM_ROOT_ONLY),
-+ DRM_IOCTL_DEF(DRM_PSB_XHW_IOCTL, psb_xhw_ioctl, DRM_ROOT_ONLY),
-+ DRM_IOCTL_DEF(DRM_PSB_SCENE_UNREF_IOCTL, drm_psb_scene_unref_ioctl,
-+ DRM_AUTH),
-+ DRM_IOCTL_DEF(DRM_PSB_KMS_OFF_IOCTL, psbfb_kms_off_ioctl,
-+ DRM_ROOT_ONLY),
-+ DRM_IOCTL_DEF(DRM_PSB_KMS_ON_IOCTL, psbfb_kms_on_ioctl, DRM_ROOT_ONLY),
-+ DRM_IOCTL_DEF(DRM_PSB_HW_INFO_IOCTL, psb_hw_info_ioctl, DRM_AUTH),
-+};
-+static int psb_max_ioctl = DRM_ARRAY_SIZE(psb_ioctls);
++/*
++ * Flags for external memory type field.
++ */
+
-+static int probe(struct pci_dev *pdev, const struct pci_device_id *ent);
++#define PSB_MSVDX_OFFSET 0x50000 /*MSVDX Base offset */
++#define PSB_MSVDX_SIZE 0x8000 /*MSVDX MMIO region is 0x50000 - 0x57fff ==> 32KB */
+
-+#ifdef USE_PAT_WC
-+#warning Init pat
-+static int __cpuinit psb_cpu_callback(struct notifier_block *nfb,
-+ unsigned long action,
-+ void *hcpu)
-+{
-+ if (action == CPU_ONLINE)
-+ drm_init_pat();
++#define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
++#define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
++#define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
+
-+ return 0;
-+}
++/*
++ * PTE's and PDE's
++ */
+
-+static struct notifier_block __cpuinitdata psb_nb = {
-+ .notifier_call = psb_cpu_callback,
-+ .priority = 1
-+};
-+#endif
++#define PSB_PDE_MASK 0x003FFFFF
++#define PSB_PDE_SHIFT 22
++#define PSB_PTE_SHIFT 12
+
-+static int dri_library_name(struct drm_device *dev, char *buf)
-+{
-+ return snprintf(buf, PAGE_SIZE, "psb\n");
-+}
++#define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
++#define PSB_PTE_WO 0x0002 /* Write only */
++#define PSB_PTE_RO 0x0004 /* Read only */
++#define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
+
-+static void psb_set_uopt(struct drm_psb_uopt *uopt)
-+{
-+ uopt->clock_gating = drm_psb_clock_gating;
-+}
++/*
++ * VDC registers and bits
++ */
++#define PSB_HWSTAM 0x2098
++#define PSB_INSTPM 0x20C0
++#define PSB_INT_IDENTITY_R 0x20A4
++#define _PSB_VSYNC_PIPEB_FLAG (1<<5)
++#define _PSB_VSYNC_PIPEA_FLAG (1<<7)
++#define _PSB_IRQ_SGX_FLAG (1<<18)
++#define _PSB_IRQ_MSVDX_FLAG (1<<19)
++#define PSB_INT_MASK_R 0x20A8
++#define PSB_INT_ENABLE_R 0x20A0
++#define PSB_PIPEASTAT 0x70024
++#define _PSB_VBLANK_INTERRUPT_ENABLE (1 << 17)
++#define _PSB_VBLANK_CLEAR (1 << 1)
++#define PSB_PIPEBSTAT 0x71024
+
-+static void psb_lastclose(struct drm_device *dev)
-+{
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
++#define _PSB_MMU_ER_MASK 0x0001FF00
++#define _PSB_MMU_ER_HOST (1 << 16)
++#define GPIOA 0x5010
++#define GPIOB 0x5014
++#define GPIOC 0x5018
++#define GPIOD 0x501c
++#define GPIOE 0x5020
++#define GPIOF 0x5024
++#define GPIOG 0x5028
++#define GPIOH 0x502c
++#define GPIO_CLOCK_DIR_MASK (1 << 0)
++#define GPIO_CLOCK_DIR_IN (0 << 1)
++#define GPIO_CLOCK_DIR_OUT (1 << 1)
++#define GPIO_CLOCK_VAL_MASK (1 << 2)
++#define GPIO_CLOCK_VAL_OUT (1 << 3)
++#define GPIO_CLOCK_VAL_IN (1 << 4)
++#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
++#define GPIO_DATA_DIR_MASK (1 << 8)
++#define GPIO_DATA_DIR_IN (0 << 9)
++#define GPIO_DATA_DIR_OUT (1 << 9)
++#define GPIO_DATA_VAL_MASK (1 << 10)
++#define GPIO_DATA_VAL_OUT (1 << 11)
++#define GPIO_DATA_VAL_IN (1 << 12)
++#define GPIO_DATA_PULLUP_DISABLE (1 << 13)
+
-+ if (!dev->dev_private)
-+ return;
++#define VCLK_DIVISOR_VGA0 0x6000
++#define VCLK_DIVISOR_VGA1 0x6004
++#define VCLK_POST_DIV 0x6010
+
-+ mutex_lock(&dev->struct_mutex);
-+ if (dev_priv->ta_mem)
-+ psb_ta_mem_unref_devlocked(&dev_priv->ta_mem);
-+ mutex_unlock(&dev->struct_mutex);
-+ mutex_lock(&dev_priv->cmdbuf_mutex);
-+ if (dev_priv->buffers) {
-+ vfree(dev_priv->buffers);
-+ dev_priv->buffers = NULL;
-+ }
-+ mutex_unlock(&dev_priv->cmdbuf_mutex);
-+}
++#define I915_WRITE(_offs, _val) \
++ iowrite32(_val, dev_priv->vdc_reg + (_offs))
++#define I915_READ(_offs) \
++ ioread32(dev_priv->vdc_reg + (_offs))
+
-+static void psb_do_takedown(struct drm_device *dev)
-+{
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
++#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
++#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
++#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
++#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
++#define PSB_COMM_USER_IRQ (1024 >> 2)
++#define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
++#define PSB_COMM_FW (2048 >> 2)
+
-+ mutex_lock(&dev->struct_mutex);
-+ if (dev->bm.initialized) {
-+ if (dev_priv->have_mem_rastgeom) {
-+ drm_bo_clean_mm(dev, DRM_PSB_MEM_RASTGEOM);
-+ dev_priv->have_mem_rastgeom = 0;
-+ }
-+ if (dev_priv->have_mem_mmu) {
-+ drm_bo_clean_mm(dev, DRM_PSB_MEM_MMU);
-+ dev_priv->have_mem_mmu = 0;
-+ }
-+ if (dev_priv->have_mem_aper) {
-+ drm_bo_clean_mm(dev, DRM_PSB_MEM_APER);
-+ dev_priv->have_mem_aper = 0;
-+ }
-+ if (dev_priv->have_tt) {
-+ drm_bo_clean_mm(dev, DRM_BO_MEM_TT);
-+ dev_priv->have_tt = 0;
-+ }
-+ if (dev_priv->have_vram) {
-+ drm_bo_clean_mm(dev, DRM_BO_MEM_VRAM);
-+ dev_priv->have_vram = 0;
-+ }
-+ }
-+ mutex_unlock(&dev->struct_mutex);
++#define PSB_UIRQ_VISTEST 1
++#define PSB_UIRQ_OOM_REPLY 2
++#define PSB_UIRQ_FIRE_TA_REPLY 3
++#define PSB_UIRQ_FIRE_RASTER_REPLY 4
+
-+ if (dev_priv->has_msvdx)
-+ psb_msvdx_uninit(dev);
++#define PSB_2D_SIZE (256*1024*1024)
++#define PSB_MAX_RELOC_PAGES 1024
+
-+ if (dev_priv->comm) {
-+ kunmap(dev_priv->comm_page);
-+ dev_priv->comm = NULL;
-+ }
-+ if (dev_priv->comm_page) {
-+ __free_page(dev_priv->comm_page);
-+ dev_priv->comm_page = NULL;
-+ }
-+}
++#define PSB_LOW_REG_OFFS 0x0204
++#define PSB_HIGH_REG_OFFS 0x0600
+
-+void psb_clockgating(struct drm_psb_private *dev_priv)
-+{
-+ uint32_t clock_gating;
++#define PSB_NUM_VBLANKS 2
+
-+ if (dev_priv->uopt.clock_gating == 1) {
-+ PSB_DEBUG_INIT("Disabling clock gating.\n");
++#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
++#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
++#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
++#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
++#define PSB_COMM_FW (2048 >> 2)
+
-+ clock_gating = (_PSB_C_CLKGATECTL_CLKG_DISABLED <<
-+ _PSB_C_CLKGATECTL_2D_CLKG_SHIFT) |
-+ (_PSB_C_CLKGATECTL_CLKG_DISABLED <<
-+ _PSB_C_CLKGATECTL_ISP_CLKG_SHIFT) |
-+ (_PSB_C_CLKGATECTL_CLKG_DISABLED <<
-+ _PSB_C_CLKGATECTL_TSP_CLKG_SHIFT) |
-+ (_PSB_C_CLKGATECTL_CLKG_DISABLED <<
-+ _PSB_C_CLKGATECTL_TA_CLKG_SHIFT) |
-+ (_PSB_C_CLKGATECTL_CLKG_DISABLED <<
-+ _PSB_C_CLKGATECTL_DPM_CLKG_SHIFT) |
-+ (_PSB_C_CLKGATECTL_CLKG_DISABLED <<
-+ _PSB_C_CLKGATECTL_USE_CLKG_SHIFT);
++#define PSB_2D_SIZE (256*1024*1024)
++#define PSB_MAX_RELOC_PAGES 1024
+
-+ } else if (dev_priv->uopt.clock_gating == 2) {
-+ PSB_DEBUG_INIT("Enabling clock gating.\n");
++#define PSB_LOW_REG_OFFS 0x0204
++#define PSB_HIGH_REG_OFFS 0x0600
+
-+ clock_gating = (_PSB_C_CLKGATECTL_CLKG_AUTO <<
-+ _PSB_C_CLKGATECTL_2D_CLKG_SHIFT) |
-+ (_PSB_C_CLKGATECTL_CLKG_AUTO <<
-+ _PSB_C_CLKGATECTL_ISP_CLKG_SHIFT) |
-+ (_PSB_C_CLKGATECTL_CLKG_AUTO <<
-+ _PSB_C_CLKGATECTL_TSP_CLKG_SHIFT) |
-+ (_PSB_C_CLKGATECTL_CLKG_AUTO <<
-+ _PSB_C_CLKGATECTL_TA_CLKG_SHIFT) |
-+ (_PSB_C_CLKGATECTL_CLKG_AUTO <<
-+ _PSB_C_CLKGATECTL_DPM_CLKG_SHIFT) |
-+ (_PSB_C_CLKGATECTL_CLKG_AUTO <<
-+ _PSB_C_CLKGATECTL_USE_CLKG_SHIFT);
-+ } else
-+ clock_gating = PSB_RSGX32(PSB_CR_CLKGATECTL);
++#define PSB_NUM_VBLANKS 2
++#define PSB_WATCHDOG_DELAY (DRM_HZ / 10)
+
-+#ifdef FIX_TG_2D_CLOCKGATE
-+ clock_gating &= ~_PSB_C_CLKGATECTL_2D_CLKG_MASK;
-+ clock_gating |= (_PSB_C_CLKGATECTL_CLKG_DISABLED <<
-+ _PSB_C_CLKGATECTL_2D_CLKG_SHIFT);
-+#endif
-+ PSB_WSGX32(clock_gating, PSB_CR_CLKGATECTL);
-+ (void)PSB_RSGX32(PSB_CR_CLKGATECTL);
-+}
++/*
++ * User options.
++ */
+
-+static int psb_do_init(struct drm_device *dev)
-+{
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
-+ struct psb_gtt *pg = dev_priv->pg;
+
-+ uint32_t stolen_gtt;
-+ uint32_t tt_start;
-+ uint32_t tt_pages;
++struct psb_gtt {
++ struct drm_device *dev;
++ int initialized;
++ uint32_t gatt_start;
++ uint32_t gtt_start;
++ uint32_t gtt_phys_start;
++ unsigned gtt_pages;
++ unsigned gatt_pages;
++ uint32_t stolen_base;
++ uint32_t pge_ctl;
++ u16 gmch_ctrl;
++ unsigned long stolen_size;
++ uint32_t *gtt_map;
++ struct rw_semaphore sem;
++};
+
-+ int ret = -ENOMEM;
-+
-+ DRM_ERROR("Debug is 0x%08x\n", drm_psb_debug);
-+
-+ dev_priv->ta_mem_pages =
-+ PSB_ALIGN_TO(drm_psb_ta_mem_size * 1024, PAGE_SIZE) >> PAGE_SHIFT;
-+ dev_priv->comm_page = alloc_page(GFP_KERNEL);
-+ if (!dev_priv->comm_page)
-+ goto out_err;
++struct psb_use_base {
++ struct list_head head;
++ struct drm_fence_object *fence;
++ unsigned int reg;
++ unsigned long offset;
++ unsigned int dm;
++};
+
-+ dev_priv->comm = kmap(dev_priv->comm_page);
-+ memset((void *)dev_priv->comm, 0, PAGE_SIZE);
++struct psb_buflist_item;
+
-+ dev_priv->has_msvdx = 1;
-+ if (psb_msvdx_init(dev))
-+ dev_priv->has_msvdx = 0;
++struct psb_msvdx_cmd_queue {
++ struct list_head head;
++ void *cmd;
++ unsigned long cmd_size;
++ uint32_t sequence;
++};
+
-+ /*
-+ * Initialize sequence numbers for the different command
-+ * submission mechanisms.
-+ */
+
-+ dev_priv->sequence[PSB_ENGINE_2D] = 0;
-+ dev_priv->sequence[PSB_ENGINE_RASTERIZER] = 0;
-+ dev_priv->sequence[PSB_ENGINE_TA] = 0;
-+ dev_priv->sequence[PSB_ENGINE_HPRAST] = 0;
++struct psb_mmu_driver;
+
-+ if (pg->gatt_start & 0x0FFFFFFF) {
-+ DRM_ERROR("Gatt must be 256M aligned. This is a bug.\n");
-+ ret = -EINVAL;
-+ goto out_err;
-+ }
++extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
++ int trap_pagefaults,
++ int invalid_type,
++ atomic_t *msvdx_mmu_invaldc);
++extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
++extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver *driver);
++extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
++ uint32_t gtt_start, uint32_t gtt_pages);
++extern void psb_mmu_test(struct psb_mmu_driver *driver, uint32_t offset);
++extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
++ int trap_pagefaults,
++ int invalid_type);
++extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
++extern void psb_mmu_flush(struct psb_mmu_driver *driver);
++extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
++ unsigned long address,
++ uint32_t num_pages);
++extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
++ uint32_t start_pfn,
++ unsigned long address,
++ uint32_t num_pages, int type);
++extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
++ unsigned long *pfn);
+
-+ stolen_gtt = (pg->stolen_size >> PAGE_SHIFT) * 4;
-+ stolen_gtt = (stolen_gtt + PAGE_SIZE - 1) >> PAGE_SHIFT;
-+ stolen_gtt = (stolen_gtt < pg->gtt_pages) ? stolen_gtt : pg->gtt_pages;
++/*
++ * Enable / disable MMU for different requestors.
++ */
+
-+ dev_priv->gatt_free_offset = pg->gatt_start +
-+ (stolen_gtt << PAGE_SHIFT) * 1024;
++extern void psb_mmu_enable_requestor(struct psb_mmu_driver *driver,
++ uint32_t mask);
++extern void psb_mmu_disable_requestor(struct psb_mmu_driver *driver,
++ uint32_t mask);
++extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
++extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
++ unsigned long address, uint32_t num_pages,
++ uint32_t desired_tile_stride,
++ uint32_t hw_tile_stride, int type);
++extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd, unsigned long address,
++ uint32_t num_pages,
++ uint32_t desired_tile_stride,
++ uint32_t hw_tile_stride);
++/*
++ * psb_sgx.c
++ */
+
-+ /*
-+ * Insert a cache-coherent communications page in mmu space
-+ * just after the stolen area. Will be used for fencing etc.
-+ */
++extern int psb_blit_sequence(struct drm_psb_private *dev_priv,
++ uint32_t sequence);
++extern void psb_init_2d(struct drm_psb_private *dev_priv);
++extern int psb_idle_2d(struct drm_device *dev);
++extern int psb_idle_3d(struct drm_device *dev);
++extern int psb_emit_2d_copy_blit(struct drm_device *dev,
++ uint32_t src_offset,
++ uint32_t dst_offset, uint32_t pages,
++ int direction);
++extern int psb_cmdbuf_ioctl(struct drm_device *dev, void *data,
++ struct drm_file *file_priv);
++extern int psb_reg_submit(struct drm_psb_private *dev_priv, uint32_t * regs,
++ unsigned int cmds);
++extern int psb_submit_copy_cmdbuf(struct drm_device *dev,
++ struct drm_buffer_object *cmd_buffer,
++ unsigned long cmd_offset,
++ unsigned long cmd_size, int engine,
++ uint32_t * copy_buffer);
++extern void psb_fence_or_sync(struct drm_file *priv,
++ int engine,
++ struct drm_psb_cmdbuf_arg *arg,
++ struct drm_fence_arg *fence_arg,
++ struct drm_fence_object **fence_p);
++extern void psb_init_disallowed(void);
+
-+ dev_priv->comm_mmu_offset = dev_priv->gatt_free_offset;
-+ dev_priv->gatt_free_offset += PAGE_SIZE;
++/*
++ * psb_irq.c
++ */
+
-+ ret = psb_mmu_insert_pages(psb_mmu_get_default_pd(dev_priv->mmu),
-+ &dev_priv->comm_page,
-+ dev_priv->comm_mmu_offset, 1, 0, 0,
-+ PSB_MMU_CACHED_MEMORY);
++extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
++extern void psb_irq_preinstall(struct drm_device *dev);
++extern int psb_irq_postinstall(struct drm_device *dev);
++extern void psb_irq_uninstall(struct drm_device *dev);
++extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
++extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
+
-+ if (ret)
-+ goto out_err;
++/*
++ * psb_fence.c
++ */
+
-+ if (1 || drm_debug) {
-+ uint32_t core_id = PSB_RSGX32(PSB_CR_CORE_ID);
-+ uint32_t core_rev = PSB_RSGX32(PSB_CR_CORE_REVISION);
-+ DRM_INFO("SGX core id = 0x%08x\n", core_id);
-+ DRM_INFO("SGX core rev major = 0x%02x, minor = 0x%02x\n",
-+ (core_rev & _PSB_CC_REVISION_MAJOR_MASK) >>
-+ _PSB_CC_REVISION_MAJOR_SHIFT,
-+ (core_rev & _PSB_CC_REVISION_MINOR_MASK) >>
-+ _PSB_CC_REVISION_MINOR_SHIFT);
-+ DRM_INFO
-+ ("SGX core rev maintenance = 0x%02x, designer = 0x%02x\n",
-+ (core_rev & _PSB_CC_REVISION_MAINTENANCE_MASK) >>
-+ _PSB_CC_REVISION_MAINTENANCE_SHIFT,
-+ (core_rev & _PSB_CC_REVISION_DESIGNER_MASK) >>
-+ _PSB_CC_REVISION_DESIGNER_SHIFT);
-+ }
++extern void psb_fence_handler(struct drm_device *dev, uint32_t class);
++extern void psb_2D_irq_off(struct drm_psb_private *dev_priv);
++extern void psb_2D_irq_on(struct drm_psb_private *dev_priv);
++extern uint32_t psb_fence_advance_sequence(struct drm_device *dev,
++ uint32_t class);
++extern int psb_fence_emit_sequence(struct drm_device *dev, uint32_t fence_class,
++ uint32_t flags, uint32_t * sequence,
++ uint32_t * native_type);
++extern void psb_fence_error(struct drm_device *dev,
++ uint32_t class,
++ uint32_t sequence, uint32_t type, int error);
+
-+ dev_priv->irqmask_lock = SPIN_LOCK_UNLOCKED;
-+ dev_priv->fence0_irq_on = 0;
++/*MSVDX stuff*/
++extern void psb_msvdx_irq_off(struct drm_psb_private *dev_priv);
++extern void psb_msvdx_irq_on(struct drm_psb_private *dev_priv);
++extern int psb_hw_info_ioctl(struct drm_device *dev, void *data,
++ struct drm_file *file_priv);
+
-+ tt_pages = (pg->gatt_pages < PSB_TT_PRIV0_PLIMIT) ?
-+ pg->gatt_pages : PSB_TT_PRIV0_PLIMIT;
-+ tt_start = dev_priv->gatt_free_offset - pg->gatt_start;
-+ tt_pages -= tt_start >> PAGE_SHIFT;
++/*
++ * psb_buffer.c
++ */
++extern struct drm_ttm_backend *drm_psb_tbe_init(struct drm_device *dev);
++extern int psb_fence_types(struct drm_buffer_object *bo, uint32_t * class,
++ uint32_t * type);
++extern uint32_t psb_evict_mask(struct drm_buffer_object *bo);
++extern int psb_invalidate_caches(struct drm_device *dev, uint64_t flags);
++extern int psb_init_mem_type(struct drm_device *dev, uint32_t type,
++ struct drm_mem_type_manager *man);
++extern int psb_move(struct drm_buffer_object *bo,
++ int evict, int no_wait, struct drm_bo_mem_reg *new_mem);
++extern int psb_tbe_size(struct drm_device *dev, unsigned long num_pages);
+
-+ mutex_lock(&dev->struct_mutex);
++/*
++ * psb_gtt.c
++ */
++extern int psb_gtt_init(struct psb_gtt *pg, int resume);
++extern int psb_gtt_insert_pages(struct psb_gtt *pg, struct page **pages,
++ unsigned offset_pages, unsigned num_pages,
++ unsigned desired_tile_stride,
++ unsigned hw_tile_stride, int type);
++extern int psb_gtt_remove_pages(struct psb_gtt *pg, unsigned offset_pages,
++ unsigned num_pages,
++ unsigned desired_tile_stride,
++ unsigned hw_tile_stride);
+
-+ if (!drm_bo_init_mm(dev, DRM_BO_MEM_VRAM, 0,
-+ pg->stolen_size >> PAGE_SHIFT)) {
-+ dev_priv->have_vram = 1;
-+ }
++extern struct psb_gtt *psb_gtt_alloc(struct drm_device *dev);
++extern void psb_gtt_takedown(struct psb_gtt *pg, int free);
+
-+ if (!drm_bo_init_mm(dev, DRM_BO_MEM_TT, tt_start >> PAGE_SHIFT,
-+ tt_pages)) {
-+ dev_priv->have_tt = 1;
-+ }
++/*
++ * psb_fb.c
++ */
++extern int psbfb_probe(struct drm_device *dev, struct drm_crtc *crtc);
++extern int psbfb_remove(struct drm_device *dev, struct drm_crtc *crtc);
++extern int psbfb_kms_off_ioctl(struct drm_device *dev, void *data,
++ struct drm_file *file_priv);
++extern int psbfb_kms_on_ioctl(struct drm_device *dev, void *data,
++ struct drm_file *file_priv);
++extern void psbfb_suspend(struct drm_device *dev);
++extern void psbfb_resume(struct drm_device *dev);
+
-+ if (!drm_bo_init_mm(dev, DRM_PSB_MEM_MMU, 0x00000000,
-+ (pg->gatt_start -
-+ PSB_MEM_MMU_START) >> PAGE_SHIFT)) {
-+ dev_priv->have_mem_mmu = 1;
-+ }
++/*
++ * psb_reset.c
++ */
+
-+ if (!drm_bo_init_mm(dev, DRM_PSB_MEM_RASTGEOM, 0x00000000,
-+ (PSB_MEM_MMU_START -
-+ PSB_MEM_RASTGEOM_START) >> PAGE_SHIFT)) {
-+ dev_priv->have_mem_rastgeom = 1;
-+ }
-+#if 0
-+ if (pg->gatt_pages > PSB_TT_PRIV0_PLIMIT) {
-+ if (!drm_bo_init_mm(dev, DRM_PSB_MEM_APER, PSB_TT_PRIV0_PLIMIT,
-+ pg->gatt_pages - PSB_TT_PRIV0_PLIMIT)) {
-+ dev_priv->have_mem_aper = 1;
-+ }
-+ }
-+#endif
++extern void psb_reset(struct drm_psb_private *dev_priv, int reset_2d);
++extern void psb_schedule_watchdog(struct drm_psb_private *dev_priv);
++extern void psb_watchdog_init(struct drm_psb_private *dev_priv);
++extern void psb_watchdog_takedown(struct drm_psb_private *dev_priv);
++extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
+
-+ mutex_unlock(&dev->struct_mutex);
++/*
++ * psb_regman.c
++ */
+
-+ return 0;
-+ out_err:
-+ psb_do_takedown(dev);
-+ return ret;
-+}
-+
-+static int psb_driver_unload(struct drm_device *dev)
-+{
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
-+
-+ intel_modeset_cleanup(dev);
-+
-+ if (dev_priv) {
-+ psb_watchdog_takedown(dev_priv);
-+ psb_do_takedown(dev);
-+ psb_xhw_takedown(dev_priv);
-+ psb_scheduler_takedown(&dev_priv->scheduler);
-+
-+ mutex_lock(&dev->struct_mutex);
-+ if (dev_priv->have_mem_pds) {
-+ drm_bo_clean_mm(dev, DRM_PSB_MEM_PDS);
-+ dev_priv->have_mem_pds = 0;
-+ }
-+ if (dev_priv->have_mem_kernel) {
-+ drm_bo_clean_mm(dev, DRM_PSB_MEM_KERNEL);
-+ dev_priv->have_mem_kernel = 0;
-+ }
-+ mutex_unlock(&dev->struct_mutex);
-+
-+ (void)drm_bo_driver_finish(dev);
++extern void psb_takedown_use_base(struct drm_psb_private *dev_priv);
++extern int psb_grab_use_base(struct drm_psb_private *dev_priv,
++ unsigned long dev_virtual,
++ unsigned long size,
++ unsigned int data_master,
++ uint32_t fence_class,
++ uint32_t fence_type,
++ int no_wait,
++ int ignore_signals,
++ int *r_reg, uint32_t * r_offset);
++extern int psb_init_use_base(struct drm_psb_private *dev_priv,
++ unsigned int reg_start, unsigned int reg_num);
+
-+ if (dev_priv->pf_pd) {
-+ psb_mmu_free_pagedir(dev_priv->pf_pd);
-+ dev_priv->pf_pd = NULL;
-+ }
-+ if (dev_priv->mmu) {
-+ struct psb_gtt *pg = dev_priv->pg;
++/*
++ * psb_xhw.c
++ */
+
-+ down_read(&pg->sem);
-+ psb_mmu_remove_pfn_sequence(psb_mmu_get_default_pd
-+ (dev_priv->mmu),
-+ pg->gatt_start,
-+ pg->
-+ stolen_size >> PAGE_SHIFT);
-+ up_read(&pg->sem);
-+ psb_mmu_driver_takedown(dev_priv->mmu);
-+ dev_priv->mmu = NULL;
-+ }
-+ psb_gtt_takedown(dev_priv->pg, 1);
-+ if (dev_priv->scratch_page) {
-+ __free_page(dev_priv->scratch_page);
-+ dev_priv->scratch_page = NULL;
-+ }
-+ psb_takedown_use_base(dev_priv);
-+ if (dev_priv->vdc_reg) {
-+ iounmap(dev_priv->vdc_reg);
-+ dev_priv->vdc_reg = NULL;
-+ }
-+ if (dev_priv->sgx_reg) {
-+ iounmap(dev_priv->sgx_reg);
-+ dev_priv->sgx_reg = NULL;
-+ }
-+ if (dev_priv->msvdx_reg) {
-+ iounmap(dev_priv->msvdx_reg);
-+ dev_priv->msvdx_reg = NULL;
-+ }
++extern int psb_xhw_ioctl(struct drm_device *dev, void *data,
++ struct drm_file *file_priv);
++extern int psb_xhw_init_ioctl(struct drm_device *dev, void *data,
++ struct drm_file *file_priv);
++extern int psb_xhw_init(struct drm_device *dev);
++extern void psb_xhw_takedown(struct drm_psb_private *dev_priv);
++extern void psb_xhw_init_takedown(struct drm_psb_private *dev_priv,
++ struct drm_file *file_priv, int closing);
++extern int psb_xhw_scene_bind_fire(struct drm_psb_private *dev_priv,
++ struct psb_xhw_buf *buf,
++ uint32_t fire_flags,
++ uint32_t hw_context,
++ uint32_t * cookie,
++ uint32_t * oom_cmds,
++ uint32_t num_oom_cmds,
++ uint32_t offset,
++ uint32_t engine, uint32_t flags);
++extern int psb_xhw_fire_raster(struct drm_psb_private *dev_priv,
++ struct psb_xhw_buf *buf, uint32_t fire_flags);
++extern int psb_xhw_scene_info(struct drm_psb_private *dev_priv,
++ struct psb_xhw_buf *buf,
++ uint32_t w,
++ uint32_t h,
++ uint32_t * hw_cookie,
++ uint32_t * bo_size,
++ uint32_t * clear_p_start,
++ uint32_t * clear_num_pages);
+
-+ drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
-+ dev->dev_private = NULL;
-+ }
-+ return 0;
-+}
++extern int psb_xhw_reset_dpm(struct drm_psb_private *dev_priv,
++ struct psb_xhw_buf *buf);
++extern int psb_xhw_check_lockup(struct drm_psb_private *dev_priv,
++ struct psb_xhw_buf *buf, uint32_t * value);
++extern int psb_xhw_ta_mem_info(struct drm_psb_private *dev_priv,
++ struct psb_xhw_buf *buf,
++ uint32_t pages,
++ uint32_t * hw_cookie, uint32_t * size);
++extern int psb_xhw_ta_oom(struct drm_psb_private *dev_priv,
++ struct psb_xhw_buf *buf, uint32_t * cookie);
++extern void psb_xhw_ta_oom_reply(struct drm_psb_private *dev_priv,
++ struct psb_xhw_buf *buf,
++ uint32_t * cookie,
++ uint32_t * bca,
++ uint32_t * rca, uint32_t * flags);
++extern int psb_xhw_vistest(struct drm_psb_private *dev_priv,
++ struct psb_xhw_buf *buf);
++extern int psb_xhw_handler(struct drm_psb_private *dev_priv);
++extern int psb_xhw_resume(struct drm_psb_private *dev_priv,
++ struct psb_xhw_buf *buf);
++extern void psb_xhw_fire_reply(struct drm_psb_private *dev_priv,
++ struct psb_xhw_buf *buf, uint32_t * cookie);
++extern int psb_xhw_ta_mem_load(struct drm_psb_private *dev_priv,
++ struct psb_xhw_buf *buf,
++ uint32_t flags,
++ uint32_t param_offset,
++ uint32_t pt_offset, uint32_t * hw_cookie);
++extern void psb_xhw_clean_buf(struct drm_psb_private *dev_priv,
++ struct psb_xhw_buf *buf);
+
++/*
++ * psb_schedule.c: HW bug fixing.
++ */
+
-+extern int drm_pick_crtcs(struct drm_device *dev);
-+extern char drm_init_mode[32];
++#ifdef FIX_TG_16
+
-+static int psb_initial_config(struct drm_device *dev, bool can_grow)
-+{
-+ struct drm_psb_private *dev_priv = dev->dev_private;
-+ struct drm_connector *output;
-+ struct drm_crtc *crtc;
-+ int ret = false;
++extern void psb_2d_unlock(struct drm_psb_private *dev_priv);
++extern void psb_2d_lock(struct drm_psb_private *dev_priv);
++extern void psb_resume_ta_2d_idle(struct drm_psb_private *dev_priv);
+
-+ mutex_lock(&dev->mode_config.mutex);
++#else
+
-+ drm_helper_probe_connector_modes(dev, 2048, 2048);
++#define psb_2d_lock(_dev_priv) mutex_lock(&(_dev_priv)->mutex_2d)
++#define psb_2d_unlock(_dev_priv) mutex_unlock(&(_dev_priv)->mutex_2d)
+
-+ /* strncpy(drm_init_mode, psb_init_mode, strlen(psb_init_mode)); */
++#endif
+
-+ drm_pick_crtcs(dev);
++/*
++ * Utilities
++ */
+
-+ if ((I915_READ(PIPEACONF) & PIPEACONF_ENABLE) && !drm_psb_force_pipeb)
-+ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-+ if (!crtc->desired_mode)
-+ continue;
++#define PSB_ALIGN_TO(_val, _align) \
++ (((_val) + ((_align) - 1)) & ~((_align) - 1))
++#define PSB_WVDC32(_val, _offs) \
++ iowrite32(_val, dev_priv->vdc_reg + (_offs))
++#define PSB_RVDC32(_offs) \
++ ioread32(dev_priv->vdc_reg + (_offs))
++#define PSB_WSGX32(_val, _offs) \
++ iowrite32(_val, dev_priv->sgx_reg + (_offs))
++#define PSB_RSGX32(_offs) \
++ ioread32(dev_priv->sgx_reg + (_offs))
++#define PSB_WMSVDX32(_val, _offs) \
++ iowrite32(_val, dev_priv->msvdx_reg + (_offs))
++#define PSB_RMSVDX32(_offs) \
++ ioread32(dev_priv->msvdx_reg + (_offs))
+
-+ dev->driver->fb_probe(dev, crtc);
-+ } else
-+ list_for_each_entry_reverse(crtc, &dev->mode_config.crtc_list,
-+ head) {
-+ if (!crtc->desired_mode)
-+ continue;
++#define PSB_ALPL(_val, _base) \
++ (((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT))
++#define PSB_ALPLM(_val, _base) \
++ ((((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT)) & (_base ## _MASK))
+
-+ dev->driver->fb_probe(dev, crtc);
-+ }
++#define PSB_D_RENDER (1 << 16)
+
-+ list_for_each_entry(output, &dev->mode_config.connector_list, head) {
++#define PSB_D_GENERAL (1 << 0)
++#define PSB_D_INIT (1 << 1)
++#define PSB_D_IRQ (1 << 2)
++#define PSB_D_FW (1 << 3)
++#define PSB_D_PERF (1 << 4)
++#define PSB_D_TMP (1 << 5)
++#define PSB_D_RELOC (1 << 6)
+
-+ if (!output->encoder->crtc || !output->encoder->crtc->desired_mode)
-+ continue;
++extern int drm_psb_debug;
++extern int drm_psb_no_fb;
++extern int drm_psb_disable_vsync;
+
-+ if (output->encoder->crtc->fb)
-+ drm_crtc_helper_set_mode(output->encoder->crtc,
-+ output->encoder->crtc->desired_mode, 0, 0, NULL);
-+ }
++#define PSB_DEBUG_FW(_fmt, _arg...) \
++ PSB_DEBUG(PSB_D_FW, _fmt, ##_arg)
++#define PSB_DEBUG_GENERAL(_fmt, _arg...) \
++ PSB_DEBUG(PSB_D_GENERAL, _fmt, ##_arg)
++#define PSB_DEBUG_INIT(_fmt, _arg...) \
++ PSB_DEBUG(PSB_D_INIT, _fmt, ##_arg)
++#define PSB_DEBUG_IRQ(_fmt, _arg...) \
++ PSB_DEBUG(PSB_D_IRQ, _fmt, ##_arg)
++#define PSB_DEBUG_RENDER(_fmt, _arg...) \
++ PSB_DEBUG(PSB_D_RENDER, _fmt, ##_arg)
++#define PSB_DEBUG_PERF(_fmt, _arg...) \
++ PSB_DEBUG(PSB_D_PERF, _fmt, ##_arg)
++#define PSB_DEBUG_TMP(_fmt, _arg...) \
++ PSB_DEBUG(PSB_D_TMP, _fmt, ##_arg)
++#define PSB_DEBUG_RELOC(_fmt, _arg...) \
++ PSB_DEBUG(PSB_D_RELOC, _fmt, ##_arg)
+
-+#ifdef SII_1392_WA
-+ if((SII_1392 != 1) || (drm_psb_no_fb==0))
-+ drm_helper_disable_unused_functions(dev);
++#if DRM_DEBUG_CODE
++#define PSB_DEBUG(_flag, _fmt, _arg...) \
++ do { \
++ if (unlikely((_flag) & drm_psb_debug)) \
++ printk(KERN_DEBUG \
++ "[psb:0x%02x:%s] " _fmt , _flag, \
++ __FUNCTION__ , ##_arg); \
++ } while (0)
+#else
-+ drm_helper_disable_unused_functions(dev);
++#define PSB_DEBUG(_fmt, _arg...) do { } while (0)
+#endif
+
++#endif
+Index: linux-2.6.28/drivers/gpu/drm/psb/psb_fb.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.28/drivers/gpu/drm/psb/psb_fb.c 2009-02-12 09:14:41.000000000 +0000
+@@ -0,0 +1,1349 @@
++/**************************************************************************
++ * Copyright (c) 2007, Intel Corporation.
++ * All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
++ *
++ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
++ * develop this driver.
++ *
++ **************************************************************************/
+
-+ mutex_unlock(&dev->mode_config.mutex);
-+
-+ return ret;
-+
-+}
-+
-+static void psb_user_framebuffer_destroy(struct drm_framebuffer *fb)
-+{
-+ struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
-+ struct drm_device *dev = fb->dev;
-+
-+ //if (fb->fbdev)
-+ // intelfb_remove(dev, fb);
-+
-+ drm_framebuffer_cleanup(fb);
-+ mutex_lock(&dev->struct_mutex);
-+ drm_gem_object_unreference(intel_fb->obj);
-+ mutex_unlock(&dev->struct_mutex);
-+
-+ kfree(intel_fb);
-+}
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/errno.h>
++#include <linux/string.h>
++#include <linux/mm.h>
++#include <linux/tty.h>
++#include <linux/slab.h>
++#include <linux/delay.h>
++#include <linux/fb.h>
++#include <linux/init.h>
++#include <linux/console.h>
+
-+static int psb_user_framebuffer_create_handle(struct drm_framebuffer *fb,
-+ struct drm_file *file_priv,
-+ unsigned int *handle)
-+{
-+ struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
-+ struct drm_gem_object *object = intel_fb->obj;
++#include "drmP.h"
++#include "drm.h"
++#include "drm_crtc.h"
++#include "psb_drv.h"
+
-+ return drm_gem_handle_create(file_priv, object, handle);
-+}
++#define SII_1392_WA
++#ifdef SII_1392_WA
++extern int SII_1392;
++#endif
+
-+static const struct drm_framebuffer_funcs psb_fb_funcs = {
-+ .destroy = psb_user_framebuffer_destroy,
-+ .create_handle = psb_user_framebuffer_create_handle,
++struct psbfb_vm_info {
++ struct drm_buffer_object *bo;
++ struct address_space *f_mapping;
++ struct mutex vm_mutex;
++ atomic_t refcount;
+};
+
-+int psb_framebuffer_create(struct drm_device *dev,
-+ struct drm_mode_fb_cmd *mode_cmd,
-+ struct drm_framebuffer **fb,
-+ struct drm_gem_object *obj)
-+{
-+ struct intel_framebuffer *intel_fb;
-+ int ret;
-+
-+ intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
-+ if (!intel_fb)
-+ return -ENOMEM;
++struct psbfb_par {
++ struct drm_device *dev;
++ struct drm_crtc *crtc;
++ struct drm_connector *output;
++ struct psbfb_vm_info *vi;
++ int dpms_state;
++};
+
-+ ret = drm_framebuffer_init(dev, &intel_fb->base, &psb_fb_funcs);
-+ if (ret) {
-+ DRM_ERROR("framebuffer init failed %d\n", ret);
-+ return ret;
++static void psbfb_vm_info_deref(struct psbfb_vm_info **vi)
++{
++ struct psbfb_vm_info *tmp = *vi;
++ *vi = NULL;
++ if (atomic_dec_and_test(&tmp->refcount)) {
++ drm_bo_usage_deref_unlocked(&tmp->bo);
++ drm_free(tmp, sizeof(*tmp), DRM_MEM_MAPS);
+ }
-+
-+ drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
-+
-+ intel_fb->obj = obj;
-+
-+ *fb = &intel_fb->base;
-+
-+ return 0;
+}
+
-+
-+static struct drm_framebuffer *
-+psb_user_framebuffer_create(struct drm_device *dev,
-+ struct drm_file *filp,
-+ struct drm_mode_fb_cmd *mode_cmd)
++static struct psbfb_vm_info *psbfb_vm_info_ref(struct psbfb_vm_info *vi)
+{
-+ struct drm_gem_object *obj;
-+ struct drm_framebuffer *fb;
-+ int ret;
++ atomic_inc(&vi->refcount);
++ return vi;
++}
+
-+ obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
-+ if (!obj)
-+ return NULL;
++static struct psbfb_vm_info *psbfb_vm_info_create(void)
++{
++ struct psbfb_vm_info *vi;
+
-+ ret = psb_framebuffer_create(dev, mode_cmd, &fb, obj);
-+ if (ret) {
-+ drm_gem_object_unreference(obj);
++ vi = drm_calloc(1, sizeof(*vi), DRM_MEM_MAPS);
++ if (!vi)
+ return NULL;
-+ }
-+
-+ return fb;
-+}
+
-+
-+int psbfb_probe2(struct drm_device *dev)
-+{
-+ return 0;
++ mutex_init(&vi->vm_mutex);
++ atomic_set(&vi->refcount, 1);
++ return vi;
+}
+
-+static const struct drm_mode_config_funcs psb_mode_funcs = {
-+ .fb_create = psb_user_framebuffer_create,
-+ .fb_changed = psbfb_probe2,
-+};
++#define CMAP_TOHW(_val, _width) ((((_val) << (_width)) + 0x7FFF - (_val)) >> 16)
+
-+static int psb_driver_load(struct drm_device *dev, unsigned long chipset)
++static int psbfb_setcolreg(unsigned regno, unsigned red, unsigned green,
++ unsigned blue, unsigned transp, struct fb_info *info)
+{
-+ struct drm_psb_private *dev_priv;
-+ unsigned long resource_start;
-+ struct psb_gtt *pg;
-+ int ret = -ENOMEM;
++ struct psbfb_par *par = info->par;
++ struct drm_crtc *crtc = par->crtc;
++ uint32_t v;
+
-+ DRM_INFO("psb - %s\n", PSB_PACKAGE_VERSION);
-+ dev_priv = drm_calloc(1, sizeof(*dev_priv), DRM_MEM_DRIVER);
-+ if (dev_priv == NULL)
++ if (!crtc->fb)
+ return -ENOMEM;
+
-+ mutex_init(&dev_priv->temp_mem);
-+ mutex_init(&dev_priv->cmdbuf_mutex);
-+ mutex_init(&dev_priv->reset_mutex);
-+ psb_init_disallowed();
++ if (regno > 255)
++ return 1;
+
-+ atomic_set(&dev_priv->msvdx_mmu_invaldc, 0);
++ if (crtc->funcs->gamma_set)
++ crtc->funcs->gamma_set(crtc, red, green, blue, regno);
+
-+#ifdef FIX_TG_16
-+ atomic_set(&dev_priv->lock_2d, 0);
-+ atomic_set(&dev_priv->ta_wait_2d, 0);
-+ atomic_set(&dev_priv->ta_wait_2d_irq, 0);
-+ atomic_set(&dev_priv->waiters_2d, 0);;
-+ DRM_INIT_WAITQUEUE(&dev_priv->queue_2d);
-+#else
-+ mutex_init(&dev_priv->mutex_2d);
-+#endif
++ red = CMAP_TOHW(red, info->var.red.length);
++ blue = CMAP_TOHW(blue, info->var.blue.length);
++ green = CMAP_TOHW(green, info->var.green.length);
++ transp = CMAP_TOHW(transp, info->var.transp.length);
+
-+ spin_lock_init(&dev_priv->reloc_lock);
++ v = (red << info->var.red.offset) |
++ (green << info->var.green.offset) |
++ (blue << info->var.blue.offset) |
++ (transp << info->var.transp.offset);
+
-+ DRM_INIT_WAITQUEUE(&dev_priv->rel_mapped_queue);
-+ DRM_INIT_WAITQUEUE(&dev_priv->event_2d_queue);
++ switch (crtc->fb->bits_per_pixel) {
++ case 16:
++ ((uint32_t *) info->pseudo_palette)[regno] = v;
++ break;
++ case 24:
++ case 32:
++ ((uint32_t *) info->pseudo_palette)[regno] = v;
++ break;
++ }
+
-+ dev->dev_private = (void *)dev_priv;
-+ dev_priv->chipset = chipset;
-+ psb_set_uopt(&dev_priv->uopt);
++ return 0;
++}
+
-+ psb_watchdog_init(dev_priv);
-+ psb_scheduler_init(dev, &dev_priv->scheduler);
++static int psbfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
++{
++ struct psbfb_par *par = info->par;
++ struct drm_device *dev = par->dev;
++ struct drm_framebuffer *fb = par->crtc->fb;
++ struct drm_display_mode *drm_mode;
++ struct drm_connector *output;
++ int depth;
++ int pitch;
++ int bpp = var->bits_per_pixel;
+
-+ resource_start = pci_resource_start(dev->pdev, PSB_MMIO_RESOURCE);
++ if (!fb)
++ return -ENOMEM;
+
-+ dev_priv->msvdx_reg =
-+ ioremap(resource_start + PSB_MSVDX_OFFSET, PSB_MSVDX_SIZE);
-+ if (!dev_priv->msvdx_reg)
-+ goto out_err;
++ if (!var->pixclock)
++ return -EINVAL;
+
-+ dev_priv->vdc_reg =
-+ ioremap(resource_start + PSB_VDC_OFFSET, PSB_VDC_SIZE);
-+ if (!dev_priv->vdc_reg)
-+ goto out_err;
++ /* don't support virtuals for now */
++ if (var->xres_virtual > var->xres)
++ return -EINVAL;
+
-+ dev_priv->sgx_reg =
-+ ioremap(resource_start + PSB_SGX_OFFSET, PSB_SGX_SIZE);
-+ if (!dev_priv->sgx_reg)
-+ goto out_err;
++ if (var->yres_virtual > var->yres)
++ return -EINVAL;
+
-+ psb_clockgating(dev_priv);
-+ if (psb_init_use_base(dev_priv, 3, 13))
-+ goto out_err;
++ switch (bpp) {
++ case 8:
++ depth = 8;
++ break;
++ case 16:
++ depth = (var->green.length == 6) ? 16 : 15;
++ break;
++ case 24: /* assume this is 32bpp / depth 24 */
++ bpp = 32;
++ /* fallthrough */
++ case 32:
++ depth = (var->transp.length > 0) ? 32 : 24;
++ break;
++ default:
++ return -EINVAL;
++ }
+
-+ dev_priv->scratch_page = alloc_page(GFP_DMA32 | __GFP_ZERO);
-+ if (!dev_priv->scratch_page)
-+ goto out_err;
++ pitch = ((var->xres * ((bpp + 1) / 8)) + 0x3f) & ~0x3f;
+
-+ dev_priv->pg = psb_gtt_alloc(dev);
-+ if (!dev_priv->pg)
-+ goto out_err;
-+
-+ ret = psb_gtt_init(dev_priv->pg, 0);
-+ if (ret)
-+ goto out_err;
-+
-+ dev_priv->mmu = psb_mmu_driver_init(dev_priv->sgx_reg,
-+ drm_psb_trap_pagefaults, 0,
-+ &dev_priv->msvdx_mmu_invaldc);
-+ if (!dev_priv->mmu)
-+ goto out_err;
++ /* Check that we can resize */
++ if ((pitch * var->yres) > (fb->bo->num_pages << PAGE_SHIFT)) {
++#if 1
++ /* Need to resize the fb object.
++ * But the generic fbdev code doesn't really understand
++ * that we can do this. So disable for now.
++ */
++ DRM_INFO("Can't support requested size, too big!\n");
++ return -EINVAL;
++#else
++ int ret;
++ struct drm_buffer_object *fbo = NULL;
++ struct drm_bo_kmap_obj tmp_kmap;
+
-+ pg = dev_priv->pg;
++ /* a temporary BO to check if we could resize in setpar.
++ * Therefore no need to set NO_EVICT.
++ */
++ ret = drm_buffer_object_create(dev,
++ pitch * var->yres,
++ drm_bo_type_kernel,
++ DRM_BO_FLAG_READ |
++ DRM_BO_FLAG_WRITE |
++ DRM_BO_FLAG_MEM_TT |
++ DRM_BO_FLAG_MEM_VRAM,
++ DRM_BO_HINT_DONT_FENCE,
++ 0, 0, &fbo);
++ if (ret || !fbo)
++ return -ENOMEM;
+
-+ /*
-+ * Make sgx MMU aware of the stolen memory area we call VRAM.
-+ */
++ ret = drm_bo_kmap(fbo, 0, fbo->num_pages, &tmp_kmap);
++ if (ret) {
++ drm_bo_usage_deref_unlocked(&fbo);
++ return -EINVAL;
++ }
+
-+ down_read(&pg->sem);
-+ ret =
-+ psb_mmu_insert_pfn_sequence(psb_mmu_get_default_pd(dev_priv->mmu),
-+ pg->stolen_base >> PAGE_SHIFT,
-+ pg->gatt_start,
-+ pg->stolen_size >> PAGE_SHIFT, 0);
-+ up_read(&pg->sem);
-+ if (ret)
-+ goto out_err;
++ drm_bo_kunmap(&tmp_kmap);
++ /* destroy our current fbo! */
++ drm_bo_usage_deref_unlocked(&fbo);
++#endif
++ }
+
-+ dev_priv->pf_pd = psb_mmu_alloc_pd(dev_priv->mmu, 1, 0);
-+ if (!dev_priv->pf_pd)
-+ goto out_err;
++ switch (depth) {
++ case 8:
++ var->red.offset = 0;
++ var->green.offset = 0;
++ var->blue.offset = 0;
++ var->red.length = 8;
++ var->green.length = 8;
++ var->blue.length = 8;
++ var->transp.length = 0;
++ var->transp.offset = 0;
++ break;
++ case 15:
++ var->red.offset = 10;
++ var->green.offset = 5;
++ var->blue.offset = 0;
++ var->red.length = 5;
++ var->green.length = 5;
++ var->blue.length = 5;
++ var->transp.length = 1;
++ var->transp.offset = 15;
++ break;
++ case 16:
++ var->red.offset = 11;
++ var->green.offset = 5;
++ var->blue.offset = 0;
++ var->red.length = 5;
++ var->green.length = 6;
++ var->blue.length = 5;
++ var->transp.length = 0;
++ var->transp.offset = 0;
++ break;
++ case 24:
++ var->red.offset = 16;
++ var->green.offset = 8;
++ var->blue.offset = 0;
++ var->red.length = 8;
++ var->green.length = 8;
++ var->blue.length = 8;
++ var->transp.length = 0;
++ var->transp.offset = 0;
++ break;
++ case 32:
++ var->red.offset = 16;
++ var->green.offset = 8;
++ var->blue.offset = 0;
++ var->red.length = 8;
++ var->green.length = 8;
++ var->blue.length = 8;
++ var->transp.length = 8;
++ var->transp.offset = 24;
++ break;
++ default:
++ return -EINVAL;
++ }
+
-+ /*
-+ * Make all presumably unused requestors page-fault by making them
-+ * use context 1 which does not have any valid mappings.
++#if 0
++ /* Here we walk the output mode list and look for modes. If we haven't
++ * got it, then bail. Not very nice, so this is disabled.
++ * In the set_par code, we create our mode based on the incoming
++ * parameters. Nicer, but may not be desired by some.
+ */
++ list_for_each_entry(output, &dev->mode_config.connector_list, head) {
++ if (output->crtc == par->crtc)
++ break;
++ }
+
-+ PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK0);
-+ PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK1);
-+ PSB_RSGX32(PSB_CR_BIF_BANK1);
-+
-+ psb_mmu_set_pd_context(psb_mmu_get_default_pd(dev_priv->mmu), 0);
-+ psb_mmu_set_pd_context(dev_priv->pf_pd, 1);
-+ psb_mmu_enable_requestor(dev_priv->mmu, _PSB_MMU_ER_MASK);
-+
-+ psb_init_2d(dev_priv);
-+
-+ ret = drm_bo_driver_init(dev);
-+ if (ret)
-+ goto out_err;
-+
-+ ret = drm_bo_init_mm(dev, DRM_PSB_MEM_KERNEL, 0x00000000,
-+ (PSB_MEM_PDS_START - PSB_MEM_KERNEL_START)
-+ >> PAGE_SHIFT);
-+ if (ret)
-+ goto out_err;
-+ dev_priv->have_mem_kernel = 1;
-+
-+ ret = drm_bo_init_mm(dev, DRM_PSB_MEM_PDS, 0x00000000,
-+ (PSB_MEM_RASTGEOM_START - PSB_MEM_PDS_START)
-+ >> PAGE_SHIFT);
-+ if (ret)
-+ goto out_err;
-+ dev_priv->have_mem_pds = 1;
-+
-+ ret = psb_do_init(dev);
-+ if (ret)
-+ return ret;
-+
-+ ret = psb_xhw_init(dev);
-+ if (ret)
-+ return ret;
-+
-+ PSB_WSGX32(PSB_MEM_PDS_START, PSB_CR_PDS_EXEC_BASE);
-+ PSB_WSGX32(PSB_MEM_RASTGEOM_START, PSB_CR_BIF_3D_REQ_BASE);
-+
-+ intel_modeset_init(dev);
-+
-+ dev->mode_config.funcs = (void *)&psb_mode_funcs;
-+
-+ drm_helper_initial_config(dev, false);
-+
++ list_for_each_entry(drm_mode, &output->modes, head) {
++ if (drm_mode->hdisplay == var->xres &&
++ drm_mode->vdisplay == var->yres && drm_mode->clock != 0)
++ break;
++ }
+
-+#ifdef USE_PAT_WC
-+#warning Init pat
-+ register_cpu_notifier(&psb_nb);
++ if (!drm_mode)
++ return -EINVAL;
++#else
++ (void)dev; /* silence warnings */
++ (void)output;
++ (void)drm_mode;
+#endif
+
+ return 0;
-+ out_err:
-+ psb_driver_unload(dev);
-+ return ret;
-+}
-+
-+int psb_driver_device_is_agp(struct drm_device *dev)
-+{
-+ return 0;
+}
+
-+static int psb_prepare_msvdx_suspend(struct drm_device *dev)
++static int psbfb_move_fb_bo(struct fb_info *info, struct drm_buffer_object *bo,
++ uint64_t mem_type_flags)
+{
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
-+ struct drm_fence_manager *fm = &dev->fm;
-+ struct drm_fence_class_manager *fc = &fm->fence_class[PSB_ENGINE_VIDEO];
-+ struct drm_fence_object *fence;
-+ int ret = 0;
-+ int signaled = 0;
-+ int count = 0;
-+ unsigned long _end = jiffies + 3 * DRM_HZ;
-+
-+ PSB_DEBUG_GENERAL("MSVDXACPI Entering psb_prepare_msvdx_suspend....\n");
-+
-+ /*set the msvdx-reset flag here.. */
-+ dev_priv->msvdx_needs_reset = 1;
++ struct psbfb_par *par;
++ loff_t holelen;
++ int ret;
+
-+ /*Ensure that all pending IRQs are serviced, */
-+ list_for_each_entry(fence, &fc->ring, ring) {
-+ count++;
-+ do {
-+ DRM_WAIT_ON(ret, fc->fence_queue, 3 * DRM_HZ,
-+ (signaled =
-+ drm_fence_object_signaled(fence,
-+ DRM_FENCE_TYPE_EXE)));
-+ if (signaled)
-+ break;
-+ if (time_after_eq(jiffies, _end))
-+ PSB_DEBUG_GENERAL
-+ ("MSVDXACPI: fence 0x%x didn't get signaled for 3 secs; we will suspend anyways\n",
-+ (unsigned int)fence);
-+ } while (ret == -EINTR);
++ /*
++ * Kill all user-space mappings of this device. They will be
++ * faulted back using nopfn when accessed.
++ */
+
++ par = info->par;
++ holelen = ((loff_t) bo->mem.num_pages) << PAGE_SHIFT;
++ mutex_lock(&par->vi->vm_mutex);
++ if (par->vi->f_mapping) {
++ unmap_mapping_range(par->vi->f_mapping, 0, holelen, 1);
+ }
+
-+ /* Issue software reset */
-+ PSB_WMSVDX32 (msvdx_sw_reset_all, MSVDX_CONTROL);
++ ret = drm_bo_do_validate(bo,
++ mem_type_flags,
++ DRM_BO_MASK_MEM |
++ DRM_BO_FLAG_NO_EVICT,
++ DRM_BO_HINT_DONT_FENCE, 0, 1, NULL);
+
-+ ret = psb_wait_for_register (dev_priv, MSVDX_CONTROL, 0,
-+ MSVDX_CONTROL_CR_MSVDX_SOFT_RESET_MASK);
++ mutex_unlock(&par->vi->vm_mutex);
++ return ret;
++}
+
-+ PSB_DEBUG_GENERAL("MSVDXACPI: All MSVDX IRQs (%d) serviced...\n",
-+ count);
-+ return 0;
-+}
-+
-+static int psb_suspend(struct pci_dev *pdev, pm_message_t state)
++/* this will let fbcon do the mode init */
++static int psbfb_set_par(struct fb_info *info)
+{
-+ struct drm_device *dev = pci_get_drvdata(pdev);
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
-+ struct drm_connector *output;
++ struct psbfb_par *par = info->par;
++ struct drm_framebuffer *fb = par->crtc->fb;
++ struct drm_device *dev = par->dev;
++ struct drm_display_mode *drm_mode;
++ struct fb_var_screeninfo *var = &info->var;
++ struct drm_psb_private *dev_priv = dev->dev_private;
++ struct drm_connector *output;
++ int pitch;
++ int depth;
++ int bpp = var->bits_per_pixel;
+
-+ if (drm_psb_no_fb == 0)
-+ psbfb_suspend(dev);
-+ else {
-+ if(num_registered_fb)
-+ {
-+ list_for_each_entry(output, &dev->mode_config.connector_list, head) {
-+ //if(output->encoder->crtc != NULL)
-+ // intel_crtc_mode_save(output->encoder->crtc);
-+ //if(output->funcs->save)
-+ // output->funcs->save(output);
-+ }
-+ }
++ if (!fb)
++ return -ENOMEM;
++
++ switch (bpp) {
++ case 8:
++ depth = 8;
++ break;
++ case 16:
++ depth = (var->green.length == 6) ? 16 : 15;
++ break;
++ case 24: /* assume this is 32bpp / depth 24 */
++ bpp = 32;
++ /* fallthrough */
++ case 32:
++ depth = (var->transp.length > 0) ? 32 : 24;
++ break;
++ default:
++ return -EINVAL;
+ }
+
-+ dev_priv->saveCLOCKGATING = PSB_RSGX32(PSB_CR_CLKGATECTL);
-+ (void)psb_idle_3d(dev);
-+ (void)psb_idle_2d(dev);
-+ flush_scheduled_work();
++ pitch = ((var->xres * ((bpp + 1) / 8)) + 0x3f) & ~0x3f;
+
-+ psb_takedown_use_base(dev_priv);
++ if ((pitch * var->yres) > (fb->bo->num_pages << PAGE_SHIFT)) {
++#if 1
++ /* Need to resize the fb object.
++ * But the generic fbdev code doesn't really understand
++ * that we can do this. So disable for now.
++ */
++ DRM_INFO("Can't support requested size, too big!\n");
++ return -EINVAL;
++#else
++ int ret;
++ struct drm_buffer_object *fbo = NULL, *tfbo;
++ struct drm_bo_kmap_obj tmp_kmap, tkmap;
+
-+ if (dev_priv->has_msvdx)
-+ psb_prepare_msvdx_suspend(dev);
++ ret = drm_buffer_object_create(dev,
++ pitch * var->yres,
++ drm_bo_type_kernel,
++ DRM_BO_FLAG_READ |
++ DRM_BO_FLAG_WRITE |
++ DRM_BO_FLAG_MEM_TT |
++ DRM_BO_FLAG_MEM_VRAM |
++ DRM_BO_FLAG_NO_EVICT,
++ DRM_BO_HINT_DONT_FENCE,
++ 0, 0, &fbo);
++ if (ret || !fbo) {
++ DRM_ERROR
++ ("failed to allocate new resized framebuffer\n");
++ return -ENOMEM;
++ }
+
-+ pci_save_state(pdev);
-+ pci_disable_device(pdev);
-+ pci_set_power_state(pdev, PCI_D3hot);
++ ret = drm_bo_kmap(fbo, 0, fbo->num_pages, &tmp_kmap);
++ if (ret) {
++ DRM_ERROR("failed to kmap framebuffer.\n");
++ drm_bo_usage_deref_unlocked(&fbo);
++ return -EINVAL;
++ }
+
-+ return 0;
-+}
++ DRM_DEBUG("allocated %dx%d fb: 0x%08lx, bo %p\n", fb->width,
++ fb->height, fb->offset, fbo);
+
-+static int psb_resume(struct pci_dev *pdev)
-+{
-+ struct drm_device *dev = pci_get_drvdata(pdev);
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
-+ struct psb_gtt *pg = dev_priv->pg;
-+ struct drm_connector *output;
-+ int ret;
++ /* set new screen base */
++ info->screen_base = tmp_kmap.virtual;
+
-+ pci_set_power_state(pdev, PCI_D0);
-+ pci_restore_state(pdev);
-+ ret = pci_enable_device(pdev);
-+ if (ret)
-+ return ret;
++ tkmap = fb->kmap;
++ fb->kmap = tmp_kmap;
++ drm_bo_kunmap(&tkmap);
+
-+#ifdef USE_PAT_WC
-+#warning Init pat
-+ /* for single CPU's we do it here, then for more than one CPU we
-+ * use the CPU notifier to reinit PAT on those CPU's.
-+ */
-+ drm_init_pat();
++ tfbo = fb->bo;
++ fb->bo = fbo;
++ drm_bo_usage_deref_unlocked(&tfbo);
+#endif
++ }
+
-+ INIT_LIST_HEAD(&dev_priv->resume_buf.head);
-+ dev_priv->msvdx_needs_reset = 1;
++ fb->offset = fb->bo->offset - dev_priv->pg->gatt_start;
++ fb->width = var->xres;
++ fb->height = var->yres;
++ fb->bits_per_pixel = bpp;
++ fb->pitch = pitch;
++ fb->depth = depth;
+
-+ PSB_WVDC32(pg->pge_ctl | _PSB_PGETBL_ENABLED, PSB_PGETBL_CTL);
-+ pci_write_config_word(pdev, PSB_GMCH_CTRL,
-+ pg->gmch_ctrl | _PSB_GMCH_ENABLED);
++ info->fix.line_length = fb->pitch;
++ info->fix.visual =
++ (fb->depth == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
+
-+ /*
-+ * The GTT page tables are probably not saved.
-+ * However, TT and VRAM is empty at this point.
-+ */
++ /* some fbdev's apps don't want these to change */
++ info->fix.smem_start = dev->mode_config.fb_base + fb->offset;
+
-+ psb_gtt_init(dev_priv->pg, 1);
++ /* we have to align the output base address because the fb->bo
++ may be moved in the previous drm_bo_do_validate().
++ Otherwise the output screens may go black when exit the X
++ window and re-enter the console */
++ info->screen_base = fb->kmap.virtual;
+
-+ /*
-+ * The SGX loses it's register contents.
-+ * Restore BIF registers. The MMU page tables are
-+ * "normal" pages, so their contents should be kept.
-+ */
++#if 0
++ /* relates to resize - disable */
++ info->fix.smem_len = info->fix.line_length * var->yres;
++ info->screen_size = info->fix.smem_len; /* ??? */
++#endif
+
-+ PSB_WSGX32(dev_priv->saveCLOCKGATING, PSB_CR_CLKGATECTL);
-+ PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK0);
-+ PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK1);
-+ PSB_RSGX32(PSB_CR_BIF_BANK1);
++ /* Should we walk the output's modelist or just create our own ???
++ * For now, we create and destroy a mode based on the incoming
++ * parameters. But there's commented out code below which scans
++ * the output list too.
++ */
++#if 0
++ list_for_each_entry(output, &dev->mode_config.connector_list, head) {
++ if (output->crtc == par->crtc)
++ break;
++ }
+
-+ psb_mmu_set_pd_context(psb_mmu_get_default_pd(dev_priv->mmu), 0);
-+ psb_mmu_set_pd_context(dev_priv->pf_pd, 1);
-+ psb_mmu_enable_requestor(dev_priv->mmu, _PSB_MMU_ER_MASK);
++ list_for_each_entry(drm_mode, &output->modes, head) {
++ if (drm_mode->hdisplay == var->xres &&
++ drm_mode->vdisplay == var->yres && drm_mode->clock != 0)
++ break;
++ }
++#else
++ (void)output; /* silence warning */
+
-+ /*
-+ * 2D Base registers..
-+ */
-+ psb_init_2d(dev_priv);
++ drm_mode = drm_mode_create(dev);
++ drm_mode->hdisplay = var->xres;
++ drm_mode->hsync_start = drm_mode->hdisplay + var->right_margin;
++ drm_mode->hsync_end = drm_mode->hsync_start + var->hsync_len;
++ drm_mode->htotal = drm_mode->hsync_end + var->left_margin;
++ drm_mode->vdisplay = var->yres;
++ drm_mode->vsync_start = drm_mode->vdisplay + var->lower_margin;
++ drm_mode->vsync_end = drm_mode->vsync_start + var->vsync_len;
++ drm_mode->vtotal = drm_mode->vsync_end + var->upper_margin;
++ drm_mode->clock = PICOS2KHZ(var->pixclock);
++ drm_mode->vrefresh = drm_mode_vrefresh(drm_mode);
++ drm_mode_set_name(drm_mode);
++ drm_mode_set_crtcinfo(drm_mode, CRTC_INTERLACE_HALVE_V);
++#endif
+
-+ if (drm_psb_no_fb == 0) {
-+ list_for_each_entry(output, &dev->mode_config.connector_list, head) {
-+ if(output->encoder->crtc != NULL)
-+ drm_crtc_helper_set_mode(output->encoder->crtc, &output->encoder->crtc->mode,
-+ output->encoder->crtc->x, output->encoder->crtc->y, NULL);
-+ }
-+ }
++ if (!drm_crtc_helper_set_mode(par->crtc, drm_mode, 0, 0, NULL))
++ return -EINVAL;
+
-+ /*
-+ * Persistant 3D base registers and USSE base registers..
++ /* Have to destroy our created mode if we're not searching the mode
++ * list for it.
+ */
++#if 1
++ drm_mode_destroy(dev, drm_mode);
++#endif
+
-+ PSB_WSGX32(PSB_MEM_PDS_START, PSB_CR_PDS_EXEC_BASE);
-+ PSB_WSGX32(PSB_MEM_RASTGEOM_START, PSB_CR_BIF_3D_REQ_BASE);
-+ psb_init_use_base(dev_priv, 3, 13);
++ return 0;
++}
+
-+ /*
-+ * Now, re-initialize the 3D engine.
-+ */
++extern int psb_2d_submit(struct drm_psb_private *, uint32_t *, uint32_t);;
+
-+ psb_xhw_resume(dev_priv, &dev_priv->resume_buf);
++static int psb_accel_2d_fillrect(struct drm_psb_private *dev_priv,
++ uint32_t dst_offset, uint32_t dst_stride,
++ uint32_t dst_format, uint16_t dst_x,
++ uint16_t dst_y, uint16_t size_x,
++ uint16_t size_y, uint32_t fill)
++{
++ uint32_t buffer[10];
++ uint32_t *buf;
++ int ret;
+
-+ psb_scheduler_ta_mem_check(dev_priv);
-+ if (dev_priv->ta_mem && !dev_priv->force_ta_mem_load) {
-+ psb_xhw_ta_mem_load(dev_priv, &dev_priv->resume_buf,
-+ PSB_TA_MEM_FLAG_TA |
-+ PSB_TA_MEM_FLAG_RASTER |
-+ PSB_TA_MEM_FLAG_HOSTA |
-+ PSB_TA_MEM_FLAG_HOSTD |
-+ PSB_TA_MEM_FLAG_INIT,
-+ dev_priv->ta_mem->ta_memory->offset,
-+ dev_priv->ta_mem->hw_data->offset,
-+ dev_priv->ta_mem->hw_cookie);
-+ }
++ buf = buffer;
+
-+ if (drm_psb_no_fb == 0)
-+ psbfb_resume(dev);
-+
-+ else {
-+ if(num_registered_fb)
-+ {
-+ struct fb_info *fb_info=registered_fb[0];
-+ list_for_each_entry(output, &dev->mode_config.connector_list, head) {
-+ //if(output->encoder->crtc != NULL)
-+ // intel_crtc_mode_restore(output->encoder->crtc);
-+ }
-+ if(fb_info)
-+ {
-+ fb_set_suspend(fb_info, 0);
-+ printk("set the fb_set_suspend resume end\n");
-+ }
-+ }
-+ }
++ *buf++ = PSB_2D_FENCE_BH;
+
++ *buf++ =
++ PSB_2D_DST_SURF_BH | dst_format | (dst_stride <<
++ PSB_2D_DST_STRIDE_SHIFT);
++ *buf++ = dst_offset;
+
-+ return 0;
-+}
++ *buf++ =
++ PSB_2D_BLIT_BH |
++ PSB_2D_ROT_NONE |
++ PSB_2D_COPYORDER_TL2BR |
++ PSB_2D_DSTCK_DISABLE |
++ PSB_2D_SRCCK_DISABLE | PSB_2D_USE_FILL | PSB_2D_ROP3_PATCOPY;
+
-+/* always available as we are SIGIO'd */
-+static unsigned int psb_poll(struct file *filp, struct poll_table_struct *wait)
-+{
-+ return (POLLIN | POLLRDNORM);
-+}
++ *buf++ = fill << PSB_2D_FILLCOLOUR_SHIFT;
++ *buf++ =
++ (dst_x << PSB_2D_DST_XSTART_SHIFT) | (dst_y <<
++ PSB_2D_DST_YSTART_SHIFT);
++ *buf++ =
++ (size_x << PSB_2D_DST_XSIZE_SHIFT) | (size_y <<
++ PSB_2D_DST_YSIZE_SHIFT);
++ *buf++ = PSB_2D_FLUSH_BH;
+
-+static int psb_release(struct inode *inode, struct file *filp)
-+{
-+ struct drm_file *file_priv = (struct drm_file *)filp->private_data;
-+ struct drm_device *dev = file_priv->minor->dev;
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
++ psb_2d_lock(dev_priv);
++ ret = psb_2d_submit(dev_priv, buffer, buf - buffer);
++ psb_2d_unlock(dev_priv);
+
-+ if (dev_priv && dev_priv->xhw_file) {
-+ psb_xhw_init_takedown(dev_priv, file_priv, 1);
-+ }
-+ return drm_release(inode, filp);
++ return ret;
+}
+
-+extern struct drm_fence_driver psb_fence_driver;
-+
-+/*
-+ * Use this memory type priority if no eviction is needed.
-+ */
-+static uint32_t psb_mem_prios[] = { DRM_BO_MEM_VRAM,
-+ DRM_BO_MEM_TT,
-+ DRM_PSB_MEM_KERNEL,
-+ DRM_PSB_MEM_MMU,
-+ DRM_PSB_MEM_RASTGEOM,
-+ DRM_PSB_MEM_PDS,
-+ DRM_PSB_MEM_APER,
-+ DRM_BO_MEM_LOCAL
-+};
++static void psbfb_fillrect_accel(struct fb_info *info,
++ const struct fb_fillrect *r)
++{
++ struct psbfb_par *par = info->par;
++ struct drm_framebuffer *fb = par->crtc->fb;
++ struct drm_psb_private *dev_priv = par->dev->dev_private;
++ uint32_t offset;
++ uint32_t stride;
++ uint32_t format;
+
-+/*
-+ * Use this memory type priority if need to evict.
-+ */
-+static uint32_t psb_busy_prios[] = { DRM_BO_MEM_TT,
-+ DRM_BO_MEM_VRAM,
-+ DRM_PSB_MEM_KERNEL,
-+ DRM_PSB_MEM_MMU,
-+ DRM_PSB_MEM_RASTGEOM,
-+ DRM_PSB_MEM_PDS,
-+ DRM_PSB_MEM_APER,
-+ DRM_BO_MEM_LOCAL
-+};
++ if (!fb)
++ return;
+
-+static struct drm_bo_driver psb_bo_driver = {
-+ .mem_type_prio = psb_mem_prios,
-+ .mem_busy_prio = psb_busy_prios,
-+ .num_mem_type_prio = ARRAY_SIZE(psb_mem_prios),
-+ .num_mem_busy_prio = ARRAY_SIZE(psb_busy_prios),
-+ .create_ttm_backend_entry = drm_psb_tbe_init,
-+ .fence_type = psb_fence_types,
-+ .invalidate_caches = psb_invalidate_caches,
-+ .init_mem_type = psb_init_mem_type,
-+ .evict_mask = psb_evict_mask,
-+ .move = psb_move,
-+ .backend_size = psb_tbe_size,
-+ .command_stream_barrier = NULL,
-+};
++ offset = fb->offset;
++ stride = fb->pitch;
+
-+static struct drm_driver driver = {
-+ .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
-+ DRIVER_IRQ_VBL | DRIVER_IRQ_VBL2,
-+ .load = psb_driver_load,
-+ .unload = psb_driver_unload,
-+ .dri_library_name = dri_library_name,
-+ .get_reg_ofs = drm_core_get_reg_ofs,
-+ .ioctls = psb_ioctls,
-+ .device_is_agp = psb_driver_device_is_agp,
-+ .vblank_wait = psb_vblank_wait,
-+ .vblank_wait2 = psb_vblank_wait2,
-+ .irq_preinstall = psb_irq_preinstall,
-+ .irq_postinstall = psb_irq_postinstall,
-+ .irq_uninstall = psb_irq_uninstall,
-+ .irq_handler = psb_irq_handler,
-+ .fb_probe = psbfb_probe,
-+ .fb_remove = psbfb_remove,
-+ .firstopen = NULL,
-+ .lastclose = psb_lastclose,
-+ .fops = {
-+ .owner = THIS_MODULE,
-+ .open = drm_open,
-+ .release = psb_release,
-+ .ioctl = drm_ioctl,
-+ .mmap = drm_mmap,
-+ .poll = psb_poll,
-+ .fasync = drm_fasync,
-+ },
-+ .pci_driver = {
-+ .name = DRIVER_NAME,
-+ .id_table = pciidlist,
-+ .probe = probe,
-+ .remove = __devexit_p(drm_cleanup_pci),
-+ .resume = psb_resume,
-+ .suspend = psb_suspend,
-+ },
-+ .fence_driver = &psb_fence_driver,
-+ .bo_driver = &psb_bo_driver,
-+ .name = DRIVER_NAME,
-+ .desc = DRIVER_DESC,
-+ .date = PSB_DRM_DRIVER_DATE,
-+ .major = PSB_DRM_DRIVER_MAJOR,
-+ .minor = PSB_DRM_DRIVER_MINOR,
-+ .patchlevel = PSB_DRM_DRIVER_PATCHLEVEL
-+};
++ switch (fb->depth) {
++ case 8:
++ format = PSB_2D_DST_332RGB;
++ break;
++ case 15:
++ format = PSB_2D_DST_555RGB;
++ break;
++ case 16:
++ format = PSB_2D_DST_565RGB;
++ break;
++ case 24:
++ case 32:
++ /* this is wrong but since we don't do blending its okay */
++ format = PSB_2D_DST_8888ARGB;
++ break;
++ default:
++ /* software fallback */
++ cfb_fillrect(info, r);
++ return;
++ }
+
-+static int probe(struct pci_dev *pdev, const struct pci_device_id *ent)
-+{
-+ return drm_get_dev(pdev, ent, &driver);
++ psb_accel_2d_fillrect(dev_priv,
++ offset, stride, format,
++ r->dx, r->dy, r->width, r->height, r->color);
+}
+
-+static int __init psb_init(void)
++static void psbfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
+{
-+ driver.num_ioctls = psb_max_ioctl;
-+
-+ return drm_init(&driver);
++ if (info->state != FBINFO_STATE_RUNNING)
++ return;
++ if (info->flags & FBINFO_HWACCEL_DISABLED) {
++ cfb_fillrect(info, rect);
++ return;
++ }
++ if (in_interrupt() || in_atomic()) {
++ /*
++ * Catch case when we're shutting down.
++ */
++ cfb_fillrect(info, rect);
++ return;
++ }
++ psbfb_fillrect_accel(info, rect);
+}
+
-+static void __exit psb_exit(void)
++uint32_t psb_accel_2d_copy_direction(int xdir, int ydir)
+{
-+ drm_exit(&driver);
++ if (xdir < 0)
++ return ((ydir <
++ 0) ? PSB_2D_COPYORDER_BR2TL : PSB_2D_COPYORDER_TR2BL);
++ else
++ return ((ydir <
++ 0) ? PSB_2D_COPYORDER_BL2TR : PSB_2D_COPYORDER_TL2BR);
+}
+
-+module_init(psb_init);
-+module_exit(psb_exit);
-+
-+MODULE_AUTHOR(DRIVER_AUTHOR);
-+MODULE_DESCRIPTION(DRIVER_DESC);
-+MODULE_LICENSE("GPL");
-Index: linux-2.6.28/drivers/gpu/drm/psb/psb_drv.h
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/psb/psb_drv.h 2009-02-12 09:14:41.000000000 +0000
-@@ -0,0 +1,548 @@
-+/**************************************************************************
-+ * Copyright (c) 2007, Intel Corporation.
-+ * All Rights Reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms and conditions of the GNU General Public License,
-+ * version 2, as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
-+ *
-+ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
-+ * develop this driver.
-+ *
-+ **************************************************************************/
+/*
++ * @srcOffset in bytes
++ * @srcStride in bytes
++ * @srcFormat psb 2D format defines
++ * @dstOffset in bytes
++ * @dstStride in bytes
++ * @dstFormat psb 2D format defines
++ * @srcX offset in pixels
++ * @srcY offset in pixels
++ * @dstX offset in pixels
++ * @dstY offset in pixels
++ * @sizeX of the copied area
++ * @sizeY of the copied area
+ */
-+#ifndef _PSB_DRV_H_
-+#define _PSB_DRV_H_
-+
-+#include "drmP.h"
-+#include "psb_drm.h"
-+#include "psb_reg.h"
-+#include "psb_schedule.h"
-+#include "intel_drv.h"
-+#include "psb_priv.h"
++static int psb_accel_2d_copy(struct drm_psb_private *dev_priv,
++ uint32_t src_offset, uint32_t src_stride,
++ uint32_t src_format, uint32_t dst_offset,
++ uint32_t dst_stride, uint32_t dst_format,
++ uint16_t src_x, uint16_t src_y, uint16_t dst_x,
++ uint16_t dst_y, uint16_t size_x, uint16_t size_y)
++{
++ uint32_t blit_cmd;
++ uint32_t buffer[10];
++ uint32_t *buf;
++ uint32_t direction;
++ int ret;
+
-+enum {
-+ CHIP_PSB_8108 = 0,
-+ CHIP_PSB_8109 = 1
-+};
++ buf = buffer;
+
-+/*
-+ * Hardware bugfixes
-+ */
++ direction = psb_accel_2d_copy_direction(src_x - dst_x, src_y - dst_y);
+
-+#define FIX_TG_16
-+#define FIX_TG_2D_CLOCKGATE
++ if (direction == PSB_2D_COPYORDER_BR2TL ||
++ direction == PSB_2D_COPYORDER_TR2BL) {
++ src_x += size_x - 1;
++ dst_x += size_x - 1;
++ }
++ if (direction == PSB_2D_COPYORDER_BR2TL ||
++ direction == PSB_2D_COPYORDER_BL2TR) {
++ src_y += size_y - 1;
++ dst_y += size_y - 1;
++ }
+
-+#define DRIVER_NAME "psb"
-+#define DRIVER_DESC "drm driver for the Intel GMA500"
-+#define DRIVER_AUTHOR "Tungsten Graphics Inc."
++ blit_cmd =
++ PSB_2D_BLIT_BH |
++ PSB_2D_ROT_NONE |
++ PSB_2D_DSTCK_DISABLE |
++ PSB_2D_SRCCK_DISABLE |
++ PSB_2D_USE_PAT | PSB_2D_ROP3_SRCCOPY | direction;
+
-+#define PSB_DRM_DRIVER_DATE "20080613"
-+#define PSB_DRM_DRIVER_MAJOR 4
-+#define PSB_DRM_DRIVER_MINOR 12
-+#define PSB_DRM_DRIVER_PATCHLEVEL 0
++ *buf++ = PSB_2D_FENCE_BH;
++ *buf++ =
++ PSB_2D_DST_SURF_BH | dst_format | (dst_stride <<
++ PSB_2D_DST_STRIDE_SHIFT);
++ *buf++ = dst_offset;
++ *buf++ =
++ PSB_2D_SRC_SURF_BH | src_format | (src_stride <<
++ PSB_2D_SRC_STRIDE_SHIFT);
++ *buf++ = src_offset;
++ *buf++ =
++ PSB_2D_SRC_OFF_BH | (src_x << PSB_2D_SRCOFF_XSTART_SHIFT) | (src_y
++ <<
++ PSB_2D_SRCOFF_YSTART_SHIFT);
++ *buf++ = blit_cmd;
++ *buf++ =
++ (dst_x << PSB_2D_DST_XSTART_SHIFT) | (dst_y <<
++ PSB_2D_DST_YSTART_SHIFT);
++ *buf++ =
++ (size_x << PSB_2D_DST_XSIZE_SHIFT) | (size_y <<
++ PSB_2D_DST_YSIZE_SHIFT);
++ *buf++ = PSB_2D_FLUSH_BH;
+
-+#define PSB_VDC_OFFSET 0x00000000
-+#define PSB_VDC_SIZE 0x000080000
-+#define PSB_SGX_SIZE 0x8000
-+#define PSB_SGX_OFFSET 0x00040000
-+#define PSB_MMIO_RESOURCE 0
-+#define PSB_GATT_RESOURCE 2
-+#define PSB_GTT_RESOURCE 3
-+#define PSB_GMCH_CTRL 0x52
-+#define PSB_BSM 0x5C
-+#define _PSB_GMCH_ENABLED 0x4
-+#define PSB_PGETBL_CTL 0x2020
-+#define _PSB_PGETBL_ENABLED 0x00000001
-+#define PSB_SGX_2D_SLAVE_PORT 0x4000
-+#define PSB_TT_PRIV0_LIMIT (256*1024*1024)
-+#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
-+#define PSB_NUM_VALIDATE_BUFFERS 1024
-+#define PSB_MEM_KERNEL_START 0x10000000
-+#define PSB_MEM_PDS_START 0x20000000
-+#define PSB_MEM_MMU_START 0x40000000
++ psb_2d_lock(dev_priv);
++ ret = psb_2d_submit(dev_priv, buffer, buf - buffer);
++ psb_2d_unlock(dev_priv);
++ return ret;
++}
+
-+#define DRM_PSB_MEM_KERNEL DRM_BO_MEM_PRIV0
-+#define DRM_PSB_FLAG_MEM_KERNEL DRM_BO_FLAG_MEM_PRIV0
++static void psbfb_copyarea_accel(struct fb_info *info,
++ const struct fb_copyarea *a)
++{
++ struct psbfb_par *par = info->par;
++ struct drm_framebuffer *fb = par->crtc->fb;
++ struct drm_psb_private *dev_priv = par->dev->dev_private;
++ uint32_t offset;
++ uint32_t stride;
++ uint32_t src_format;
++ uint32_t dst_format;
+
-+/*
-+ * Flags for external memory type field.
-+ */
++ if (!fb)
++ return;
+
-+#define PSB_MSVDX_OFFSET 0x50000 /*MSVDX Base offset */
-+#define PSB_MSVDX_SIZE 0x8000 /*MSVDX MMIO region is 0x50000 - 0x57fff ==> 32KB */
++ offset = fb->offset;
++ stride = fb->pitch;
+
-+#define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
-+#define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
-+#define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
++ if (a->width == 8 || a->height == 8) {
++ psb_2d_lock(dev_priv);
++ psb_idle_2d(par->dev);
++ psb_2d_unlock(dev_priv);
++ cfb_copyarea(info, a);
++ return;
++ }
+
-+/*
-+ * PTE's and PDE's
-+ */
++ switch (fb->depth) {
++ case 8:
++ src_format = PSB_2D_SRC_332RGB;
++ dst_format = PSB_2D_DST_332RGB;
++ break;
++ case 15:
++ src_format = PSB_2D_SRC_555RGB;
++ dst_format = PSB_2D_DST_555RGB;
++ break;
++ case 16:
++ src_format = PSB_2D_SRC_565RGB;
++ dst_format = PSB_2D_DST_565RGB;
++ break;
++ case 24:
++ case 32:
++ /* this is wrong but since we don't do blending its okay */
++ src_format = PSB_2D_SRC_8888ARGB;
++ dst_format = PSB_2D_DST_8888ARGB;
++ break;
++ default:
++ /* software fallback */
++ cfb_copyarea(info, a);
++ return;
++ }
+
-+#define PSB_PDE_MASK 0x003FFFFF
-+#define PSB_PDE_SHIFT 22
-+#define PSB_PTE_SHIFT 12
++ psb_accel_2d_copy(dev_priv,
++ offset, stride, src_format,
++ offset, stride, dst_format,
++ a->sx, a->sy, a->dx, a->dy, a->width, a->height);
++}
+
-+#define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
-+#define PSB_PTE_WO 0x0002 /* Write only */
-+#define PSB_PTE_RO 0x0004 /* Read only */
-+#define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
++static void psbfb_copyarea(struct fb_info *info,
++ const struct fb_copyarea *region)
++{
++ if (info->state != FBINFO_STATE_RUNNING)
++ return;
++ if (info->flags & FBINFO_HWACCEL_DISABLED) {
++ cfb_copyarea(info, region);
++ return;
++ }
++ if (in_interrupt() || in_atomic()) {
++ /*
++ * Catch case when we're shutting down.
++ */
++ cfb_copyarea(info, region);
++ return;
++ }
+
-+/*
-+ * VDC registers and bits
-+ */
-+#define PSB_HWSTAM 0x2098
-+#define PSB_INSTPM 0x20C0
-+#define PSB_INT_IDENTITY_R 0x20A4
-+#define _PSB_VSYNC_PIPEB_FLAG (1<<5)
-+#define _PSB_VSYNC_PIPEA_FLAG (1<<7)
-+#define _PSB_IRQ_SGX_FLAG (1<<18)
-+#define _PSB_IRQ_MSVDX_FLAG (1<<19)
-+#define PSB_INT_MASK_R 0x20A8
-+#define PSB_INT_ENABLE_R 0x20A0
-+#define PSB_PIPEASTAT 0x70024
-+#define _PSB_VBLANK_INTERRUPT_ENABLE (1 << 17)
-+#define _PSB_VBLANK_CLEAR (1 << 1)
-+#define PSB_PIPEBSTAT 0x71024
++ psbfb_copyarea_accel(info, region);
++}
+
-+#define _PSB_MMU_ER_MASK 0x0001FF00
-+#define _PSB_MMU_ER_HOST (1 << 16)
-+#define GPIOA 0x5010
-+#define GPIOB 0x5014
-+#define GPIOC 0x5018
-+#define GPIOD 0x501c
-+#define GPIOE 0x5020
-+#define GPIOF 0x5024
-+#define GPIOG 0x5028
-+#define GPIOH 0x502c
-+#define GPIO_CLOCK_DIR_MASK (1 << 0)
-+#define GPIO_CLOCK_DIR_IN (0 << 1)
-+#define GPIO_CLOCK_DIR_OUT (1 << 1)
-+#define GPIO_CLOCK_VAL_MASK (1 << 2)
-+#define GPIO_CLOCK_VAL_OUT (1 << 3)
-+#define GPIO_CLOCK_VAL_IN (1 << 4)
-+#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
-+#define GPIO_DATA_DIR_MASK (1 << 8)
-+#define GPIO_DATA_DIR_IN (0 << 9)
-+#define GPIO_DATA_DIR_OUT (1 << 9)
-+#define GPIO_DATA_VAL_MASK (1 << 10)
-+#define GPIO_DATA_VAL_OUT (1 << 11)
-+#define GPIO_DATA_VAL_IN (1 << 12)
-+#define GPIO_DATA_PULLUP_DISABLE (1 << 13)
++void psbfb_imageblit(struct fb_info *info, const struct fb_image *image)
++{
++ if (info->state != FBINFO_STATE_RUNNING)
++ return;
++ if (info->flags & FBINFO_HWACCEL_DISABLED) {
++ cfb_imageblit(info, image);
++ return;
++ }
++ if (in_interrupt() || in_atomic()) {
++ cfb_imageblit(info, image);
++ return;
++ }
+
-+#define VCLK_DIVISOR_VGA0 0x6000
-+#define VCLK_DIVISOR_VGA1 0x6004
-+#define VCLK_POST_DIV 0x6010
++ cfb_imageblit(info, image);
++}
+
-+#define I915_WRITE(_offs, _val) \
-+ iowrite32(_val, dev_priv->vdc_reg + (_offs))
-+#define I915_READ(_offs) \
-+ ioread32(dev_priv->vdc_reg + (_offs))
++static int psbfb_blank(int blank_mode, struct fb_info *info)
++{
++ int dpms_mode;
++ struct psbfb_par *par = info->par;
++ struct drm_connector *output;
++ struct drm_crtc_helper_funcs *crtc_funcs;
+
-+#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
-+#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
-+#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
-+#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
-+#define PSB_COMM_USER_IRQ (1024 >> 2)
-+#define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
-+#define PSB_COMM_FW (2048 >> 2)
++ par->dpms_state = blank_mode;
+
-+#define PSB_UIRQ_VISTEST 1
-+#define PSB_UIRQ_OOM_REPLY 2
-+#define PSB_UIRQ_FIRE_TA_REPLY 3
-+#define PSB_UIRQ_FIRE_RASTER_REPLY 4
++ switch(blank_mode) {
++ case FB_BLANK_UNBLANK:
++ dpms_mode = DRM_MODE_DPMS_ON;
++ break;
++ case FB_BLANK_NORMAL:
++ if (!par->crtc)
++ return 0;
++ crtc_funcs = par->crtc->helper_private;
+
-+#define PSB_2D_SIZE (256*1024*1024)
-+#define PSB_MAX_RELOC_PAGES 1024
++ (*crtc_funcs->dpms)(par->crtc, DRM_MODE_DPMS_STANDBY);
++ return 0;
++ case FB_BLANK_HSYNC_SUSPEND:
++ default:
++ dpms_mode = DRM_MODE_DPMS_STANDBY;
++ break;
++ case FB_BLANK_VSYNC_SUSPEND:
++ dpms_mode = DRM_MODE_DPMS_SUSPEND;
++ break;
++ case FB_BLANK_POWERDOWN:
++ dpms_mode = DRM_MODE_DPMS_OFF;
++ break;
++ }
+
-+#define PSB_LOW_REG_OFFS 0x0204
-+#define PSB_HIGH_REG_OFFS 0x0600
++ if (!par->crtc)
++ return 0;
+
-+#define PSB_NUM_VBLANKS 2
++ crtc_funcs = par->crtc->helper_private;
+
-+#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
-+#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
-+#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
-+#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
-+#define PSB_COMM_FW (2048 >> 2)
++ list_for_each_entry(output, &par->dev->mode_config.connector_list, head) {
++ if (output->encoder->crtc == par->crtc)
++ (*output->funcs->dpms)(output, dpms_mode);
++ }
+
-+#define PSB_2D_SIZE (256*1024*1024)
-+#define PSB_MAX_RELOC_PAGES 1024
++ return 0;
++}
+
-+#define PSB_LOW_REG_OFFS 0x0204
-+#define PSB_HIGH_REG_OFFS 0x0600
+
-+#define PSB_NUM_VBLANKS 2
-+#define PSB_WATCHDOG_DELAY (DRM_HZ / 10)
++static int psbfb_kms_off(struct drm_device *dev, int suspend)
++{
++ struct drm_framebuffer *fb = 0;
++ struct drm_buffer_object *bo = 0;
++ struct drm_psb_private *dev_priv = dev->dev_private;
++ int ret = 0;
+
-+/*
-+ * User options.
-+ */
++ DRM_DEBUG("psbfb_kms_off_ioctl\n");
+
++ mutex_lock(&dev->mode_config.mutex);
++ list_for_each_entry(fb, &dev->mode_config.fb_list, head) {
++ struct fb_info *info = fb->fbdev;
++ struct psbfb_par *par = info->par;
++ int save_dpms_state;
+
-+struct psb_gtt {
-+ struct drm_device *dev;
-+ int initialized;
-+ uint32_t gatt_start;
-+ uint32_t gtt_start;
-+ uint32_t gtt_phys_start;
-+ unsigned gtt_pages;
-+ unsigned gatt_pages;
-+ uint32_t stolen_base;
-+ uint32_t pge_ctl;
-+ u16 gmch_ctrl;
-+ unsigned long stolen_size;
-+ uint32_t *gtt_map;
-+ struct rw_semaphore sem;
-+};
++ if (suspend)
++ fb_set_suspend(info, 1);
++ else
++ info->state &= ~FBINFO_STATE_RUNNING;
+
-+struct psb_use_base {
-+ struct list_head head;
-+ struct drm_fence_object *fence;
-+ unsigned int reg;
-+ unsigned long offset;
-+ unsigned int dm;
-+};
++ info->screen_base = NULL;
+
-+struct psb_buflist_item;
++ bo = fb->bo;
+
-+struct psb_msvdx_cmd_queue {
-+ struct list_head head;
-+ void *cmd;
-+ unsigned long cmd_size;
-+ uint32_t sequence;
-+};
++ if (!bo)
++ continue;
+
++ drm_bo_kunmap(&fb->kmap);
+
-+struct psb_mmu_driver;
++ /*
++ * We don't take the 2D lock here as we assume that the
++ * 2D engine will eventually idle anyway.
++ */
+
-+extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
-+ int trap_pagefaults,
-+ int invalid_type,
-+ atomic_t *msvdx_mmu_invaldc);
-+extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
-+extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver *driver);
-+extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
-+ uint32_t gtt_start, uint32_t gtt_pages);
-+extern void psb_mmu_test(struct psb_mmu_driver *driver, uint32_t offset);
-+extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
-+ int trap_pagefaults,
-+ int invalid_type);
-+extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
-+extern void psb_mmu_flush(struct psb_mmu_driver *driver);
-+extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
-+ unsigned long address,
-+ uint32_t num_pages);
-+extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
-+ uint32_t start_pfn,
-+ unsigned long address,
-+ uint32_t num_pages, int type);
-+extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
-+ unsigned long *pfn);
++ if (!suspend) {
++ uint32_t dummy2 = 0;
++ (void) psb_fence_emit_sequence(dev, PSB_ENGINE_2D, 0,
++ &dummy2, &dummy2);
++ psb_2d_lock(dev_priv);
++ (void)psb_idle_2d(dev);
++ psb_2d_unlock(dev_priv);
++ } else
++ psb_idle_2d(dev);
+
-+/*
-+ * Enable / disable MMU for different requestors.
-+ */
++ save_dpms_state = par->dpms_state;
++ psbfb_blank(FB_BLANK_NORMAL, info);
++ par->dpms_state = save_dpms_state;
+
-+extern void psb_mmu_enable_requestor(struct psb_mmu_driver *driver,
-+ uint32_t mask);
-+extern void psb_mmu_disable_requestor(struct psb_mmu_driver *driver,
-+ uint32_t mask);
-+extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
-+extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
-+ unsigned long address, uint32_t num_pages,
-+ uint32_t desired_tile_stride,
-+ uint32_t hw_tile_stride, int type);
-+extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd, unsigned long address,
-+ uint32_t num_pages,
-+ uint32_t desired_tile_stride,
-+ uint32_t hw_tile_stride);
-+/*
-+ * psb_sgx.c
-+ */
++ ret = psbfb_move_fb_bo(info, bo, DRM_BO_FLAG_MEM_LOCAL);
+
-+extern int psb_blit_sequence(struct drm_psb_private *dev_priv,
-+ uint32_t sequence);
-+extern void psb_init_2d(struct drm_psb_private *dev_priv);
-+extern int psb_idle_2d(struct drm_device *dev);
-+extern int psb_idle_3d(struct drm_device *dev);
-+extern int psb_emit_2d_copy_blit(struct drm_device *dev,
-+ uint32_t src_offset,
-+ uint32_t dst_offset, uint32_t pages,
-+ int direction);
-+extern int psb_cmdbuf_ioctl(struct drm_device *dev, void *data,
-+ struct drm_file *file_priv);
-+extern int psb_reg_submit(struct drm_psb_private *dev_priv, uint32_t * regs,
-+ unsigned int cmds);
-+extern int psb_submit_copy_cmdbuf(struct drm_device *dev,
-+ struct drm_buffer_object *cmd_buffer,
-+ unsigned long cmd_offset,
-+ unsigned long cmd_size, int engine,
-+ uint32_t * copy_buffer);
-+extern void psb_fence_or_sync(struct drm_file *priv,
-+ int engine,
-+ struct drm_psb_cmdbuf_arg *arg,
-+ struct drm_fence_arg *fence_arg,
-+ struct drm_fence_object **fence_p);
-+extern void psb_init_disallowed(void);
++ if (ret)
++ goto out_err;
++ }
++ out_err:
++ mutex_unlock(&dev->mode_config.mutex);
+
-+/*
-+ * psb_irq.c
-+ */
++ return ret;
++}
+
-+extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
-+extern void psb_irq_preinstall(struct drm_device *dev);
-+extern int psb_irq_postinstall(struct drm_device *dev);
-+extern void psb_irq_uninstall(struct drm_device *dev);
-+extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
-+extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
++int psbfb_kms_off_ioctl(struct drm_device *dev, void *data,
++ struct drm_file *file_priv)
++{
++ int ret;
+
-+/*
-+ * psb_fence.c
-+ */
++ acquire_console_sem();
++ ret = psbfb_kms_off(dev, 0);
++ release_console_sem();
+
-+extern void psb_fence_handler(struct drm_device *dev, uint32_t class);
-+extern void psb_2D_irq_off(struct drm_psb_private *dev_priv);
-+extern void psb_2D_irq_on(struct drm_psb_private *dev_priv);
-+extern uint32_t psb_fence_advance_sequence(struct drm_device *dev,
-+ uint32_t class);
-+extern int psb_fence_emit_sequence(struct drm_device *dev, uint32_t fence_class,
-+ uint32_t flags, uint32_t * sequence,
-+ uint32_t * native_type);
-+extern void psb_fence_error(struct drm_device *dev,
-+ uint32_t class,
-+ uint32_t sequence, uint32_t type, int error);
++ return ret;
++}
+
-+/*MSVDX stuff*/
-+extern void psb_msvdx_irq_off(struct drm_psb_private *dev_priv);
-+extern void psb_msvdx_irq_on(struct drm_psb_private *dev_priv);
-+extern int psb_hw_info_ioctl(struct drm_device *dev, void *data,
-+ struct drm_file *file_priv);
++static int psbfb_kms_on(struct drm_device *dev, int resume)
++{
++ struct drm_framebuffer *fb = 0;
++ struct drm_buffer_object *bo = 0;
++ struct drm_psb_private *dev_priv = dev->dev_private;
++ int ret = 0;
++ int dummy;
+
-+/*
-+ * psb_buffer.c
-+ */
-+extern struct drm_ttm_backend *drm_psb_tbe_init(struct drm_device *dev);
-+extern int psb_fence_types(struct drm_buffer_object *bo, uint32_t * class,
-+ uint32_t * type);
-+extern uint32_t psb_evict_mask(struct drm_buffer_object *bo);
-+extern int psb_invalidate_caches(struct drm_device *dev, uint64_t flags);
-+extern int psb_init_mem_type(struct drm_device *dev, uint32_t type,
-+ struct drm_mem_type_manager *man);
-+extern int psb_move(struct drm_buffer_object *bo,
-+ int evict, int no_wait, struct drm_bo_mem_reg *new_mem);
-+extern int psb_tbe_size(struct drm_device *dev, unsigned long num_pages);
++ DRM_DEBUG("psbfb_kms_on_ioctl\n");
+
-+/*
-+ * psb_gtt.c
-+ */
-+extern int psb_gtt_init(struct psb_gtt *pg, int resume);
-+extern int psb_gtt_insert_pages(struct psb_gtt *pg, struct page **pages,
-+ unsigned offset_pages, unsigned num_pages,
-+ unsigned desired_tile_stride,
-+ unsigned hw_tile_stride, int type);
-+extern int psb_gtt_remove_pages(struct psb_gtt *pg, unsigned offset_pages,
-+ unsigned num_pages,
-+ unsigned desired_tile_stride,
-+ unsigned hw_tile_stride);
-+
-+extern struct psb_gtt *psb_gtt_alloc(struct drm_device *dev);
-+extern void psb_gtt_takedown(struct psb_gtt *pg, int free);
++ if (!resume) {
++ uint32_t dummy2 = 0;
++ (void) psb_fence_emit_sequence(dev, PSB_ENGINE_2D, 0,
++ &dummy2, &dummy2);
++ psb_2d_lock(dev_priv);
++ (void)psb_idle_2d(dev);
++ psb_2d_unlock(dev_priv);
++ } else
++ psb_idle_2d(dev);
+
-+/*
-+ * psb_fb.c
-+ */
-+extern int psbfb_probe(struct drm_device *dev, struct drm_crtc *crtc);
-+extern int psbfb_remove(struct drm_device *dev, struct drm_crtc *crtc);
-+extern int psbfb_kms_off_ioctl(struct drm_device *dev, void *data,
-+ struct drm_file *file_priv);
-+extern int psbfb_kms_on_ioctl(struct drm_device *dev, void *data,
-+ struct drm_file *file_priv);
-+extern void psbfb_suspend(struct drm_device *dev);
-+extern void psbfb_resume(struct drm_device *dev);
++ mutex_lock(&dev->mode_config.mutex);
++ list_for_each_entry(fb, &dev->mode_config.fb_list, head) {
++ struct fb_info *info = fb->fbdev;
++ struct psbfb_par *par = info->par;
+
-+/*
-+ * psb_reset.c
-+ */
++ bo = fb->bo;
++ if (!bo)
++ continue;
+
-+extern void psb_reset(struct drm_psb_private *dev_priv, int reset_2d);
-+extern void psb_schedule_watchdog(struct drm_psb_private *dev_priv);
-+extern void psb_watchdog_init(struct drm_psb_private *dev_priv);
-+extern void psb_watchdog_takedown(struct drm_psb_private *dev_priv);
-+extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
++ ret = psbfb_move_fb_bo(info, bo,
++ DRM_BO_FLAG_MEM_TT |
++ DRM_BO_FLAG_MEM_VRAM |
++ DRM_BO_FLAG_NO_EVICT);
++ if (ret)
++ goto out_err;
+
-+/*
-+ * psb_regman.c
-+ */
++ ret = drm_bo_kmap(bo, 0, bo->num_pages, &fb->kmap);
++ if (ret)
++ goto out_err;
+
-+extern void psb_takedown_use_base(struct drm_psb_private *dev_priv);
-+extern int psb_grab_use_base(struct drm_psb_private *dev_priv,
-+ unsigned long dev_virtual,
-+ unsigned long size,
-+ unsigned int data_master,
-+ uint32_t fence_class,
-+ uint32_t fence_type,
-+ int no_wait,
-+ int ignore_signals,
-+ int *r_reg, uint32_t * r_offset);
-+extern int psb_init_use_base(struct drm_psb_private *dev_priv,
-+ unsigned int reg_start, unsigned int reg_num);
++ info->screen_base = drm_bmo_virtual(&fb->kmap, &dummy);
++ fb->offset = bo->offset - dev_priv->pg->gatt_start;
+
-+/*
-+ * psb_xhw.c
-+ */
++ if (ret)
++ goto out_err;
+
-+extern int psb_xhw_ioctl(struct drm_device *dev, void *data,
-+ struct drm_file *file_priv);
-+extern int psb_xhw_init_ioctl(struct drm_device *dev, void *data,
-+ struct drm_file *file_priv);
-+extern int psb_xhw_init(struct drm_device *dev);
-+extern void psb_xhw_takedown(struct drm_psb_private *dev_priv);
-+extern void psb_xhw_init_takedown(struct drm_psb_private *dev_priv,
-+ struct drm_file *file_priv, int closing);
-+extern int psb_xhw_scene_bind_fire(struct drm_psb_private *dev_priv,
-+ struct psb_xhw_buf *buf,
-+ uint32_t fire_flags,
-+ uint32_t hw_context,
-+ uint32_t * cookie,
-+ uint32_t * oom_cmds,
-+ uint32_t num_oom_cmds,
-+ uint32_t offset,
-+ uint32_t engine, uint32_t flags);
-+extern int psb_xhw_fire_raster(struct drm_psb_private *dev_priv,
-+ struct psb_xhw_buf *buf, uint32_t fire_flags);
-+extern int psb_xhw_scene_info(struct drm_psb_private *dev_priv,
-+ struct psb_xhw_buf *buf,
-+ uint32_t w,
-+ uint32_t h,
-+ uint32_t * hw_cookie,
-+ uint32_t * bo_size,
-+ uint32_t * clear_p_start,
-+ uint32_t * clear_num_pages);
++ if (resume)
++ fb_set_suspend(info, 0);
++ else
++ info->state |= FBINFO_STATE_RUNNING;
+
-+extern int psb_xhw_reset_dpm(struct drm_psb_private *dev_priv,
-+ struct psb_xhw_buf *buf);
-+extern int psb_xhw_check_lockup(struct drm_psb_private *dev_priv,
-+ struct psb_xhw_buf *buf, uint32_t * value);
-+extern int psb_xhw_ta_mem_info(struct drm_psb_private *dev_priv,
-+ struct psb_xhw_buf *buf,
-+ uint32_t pages,
-+ uint32_t * hw_cookie, uint32_t * size);
-+extern int psb_xhw_ta_oom(struct drm_psb_private *dev_priv,
-+ struct psb_xhw_buf *buf, uint32_t * cookie);
-+extern void psb_xhw_ta_oom_reply(struct drm_psb_private *dev_priv,
-+ struct psb_xhw_buf *buf,
-+ uint32_t * cookie,
-+ uint32_t * bca,
-+ uint32_t * rca, uint32_t * flags);
-+extern int psb_xhw_vistest(struct drm_psb_private *dev_priv,
-+ struct psb_xhw_buf *buf);
-+extern int psb_xhw_handler(struct drm_psb_private *dev_priv);
-+extern int psb_xhw_resume(struct drm_psb_private *dev_priv,
-+ struct psb_xhw_buf *buf);
-+extern void psb_xhw_fire_reply(struct drm_psb_private *dev_priv,
-+ struct psb_xhw_buf *buf, uint32_t * cookie);
-+extern int psb_xhw_ta_mem_load(struct drm_psb_private *dev_priv,
-+ struct psb_xhw_buf *buf,
-+ uint32_t flags,
-+ uint32_t param_offset,
-+ uint32_t pt_offset, uint32_t * hw_cookie);
-+extern void psb_xhw_clean_buf(struct drm_psb_private *dev_priv,
-+ struct psb_xhw_buf *buf);
++ /*
++ * Re-run modesetting here, since the VDS scanout offset may
++ * have changed.
++ */
+
-+/*
-+ * psb_schedule.c: HW bug fixing.
-+ */
++ if (par->crtc->enabled) {
++ psbfb_set_par(info);
++ psbfb_blank(par->dpms_state, info);
++ }
++ }
++ out_err:
++ mutex_unlock(&dev->mode_config.mutex);
+
-+#ifdef FIX_TG_16
++ return ret;
++}
+
-+extern void psb_2d_unlock(struct drm_psb_private *dev_priv);
-+extern void psb_2d_lock(struct drm_psb_private *dev_priv);
-+extern void psb_resume_ta_2d_idle(struct drm_psb_private *dev_priv);
++int psbfb_kms_on_ioctl(struct drm_device *dev, void *data,
++ struct drm_file *file_priv)
++{
++ int ret;
+
++ acquire_console_sem();
++ ret = psbfb_kms_on(dev, 0);
++ release_console_sem();
++#ifdef SII_1392_WA
++ if((SII_1392 != 1) || (drm_psb_no_fb==0))
++ drm_helper_disable_unused_functions(dev);
+#else
++ drm_helper_disable_unused_functions(dev);
++#endif
++ return ret;
++}
+
-+#define psb_2d_lock(_dev_priv) mutex_lock(&(_dev_priv)->mutex_2d)
-+#define psb_2d_unlock(_dev_priv) mutex_unlock(&(_dev_priv)->mutex_2d)
++void psbfb_suspend(struct drm_device *dev)
++{
++ acquire_console_sem();
++ psbfb_kms_off(dev, 1);
++ release_console_sem();
++}
+
++void psbfb_resume(struct drm_device *dev)
++{
++ acquire_console_sem();
++ psbfb_kms_on(dev, 1);
++ release_console_sem();
++#ifdef SII_1392_WA
++ if((SII_1392 != 1) || (drm_psb_no_fb==0))
++ drm_helper_disable_unused_functions(dev);
++#else
++ drm_helper_disable_unused_functions(dev);
+#endif
++}
+
+/*
-+ * Utilities
++ * FIXME: Before kernel inclusion, migrate nopfn to fault.
++ * Also, these should be the default vm ops for buffer object type fbs.
+ */
+
-+#define PSB_ALIGN_TO(_val, _align) \
-+ (((_val) + ((_align) - 1)) & ~((_align) - 1))
-+#define PSB_WVDC32(_val, _offs) \
-+ iowrite32(_val, dev_priv->vdc_reg + (_offs))
-+#define PSB_RVDC32(_offs) \
-+ ioread32(dev_priv->vdc_reg + (_offs))
-+#define PSB_WSGX32(_val, _offs) \
-+ iowrite32(_val, dev_priv->sgx_reg + (_offs))
-+#define PSB_RSGX32(_offs) \
-+ ioread32(dev_priv->sgx_reg + (_offs))
-+#define PSB_WMSVDX32(_val, _offs) \
-+ iowrite32(_val, dev_priv->msvdx_reg + (_offs))
-+#define PSB_RMSVDX32(_offs) \
-+ ioread32(dev_priv->msvdx_reg + (_offs))
++extern unsigned long drm_bo_vm_fault(struct vm_area_struct *vma,
++ struct vm_fault *vmf);
+
-+#define PSB_ALPL(_val, _base) \
-+ (((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT))
-+#define PSB_ALPLM(_val, _base) \
-+ ((((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT)) & (_base ## _MASK))
++/*
++ * This wrapper is a bit ugly and is here because we need access to a mutex
++ * that we can lock both around nopfn and around unmap_mapping_range + move.
++ * Normally, this would've been done using the bo mutex, but unfortunately
++ * we cannot lock it around drm_bo_do_validate(), since that would imply
++ * recursive locking.
++ */
+
-+#define PSB_D_RENDER (1 << 16)
++static int psbfb_fault(struct vm_area_struct *vma,
++ struct vm_fault *vmf)
++{
++ struct psbfb_vm_info *vi = (struct psbfb_vm_info *)vma->vm_private_data;
++ struct vm_area_struct tmp_vma;
++ int ret;
+
-+#define PSB_D_GENERAL (1 << 0)
-+#define PSB_D_INIT (1 << 1)
-+#define PSB_D_IRQ (1 << 2)
-+#define PSB_D_FW (1 << 3)
-+#define PSB_D_PERF (1 << 4)
-+#define PSB_D_TMP (1 << 5)
-+#define PSB_D_RELOC (1 << 6)
++ mutex_lock(&vi->vm_mutex);
++ tmp_vma = *vma;
++ tmp_vma.vm_private_data = vi->bo;
++ ret = drm_bo_vm_fault(&tmp_vma, vmf);
++ mutex_unlock(&vi->vm_mutex);
++ return ret;
++}
+
-+extern int drm_psb_debug;
-+extern int drm_psb_no_fb;
-+extern int drm_psb_disable_vsync;
++static void psbfb_vm_open(struct vm_area_struct *vma)
++{
++ struct psbfb_vm_info *vi = (struct psbfb_vm_info *)vma->vm_private_data;
+
-+#define PSB_DEBUG_FW(_fmt, _arg...) \
-+ PSB_DEBUG(PSB_D_FW, _fmt, ##_arg)
-+#define PSB_DEBUG_GENERAL(_fmt, _arg...) \
-+ PSB_DEBUG(PSB_D_GENERAL, _fmt, ##_arg)
-+#define PSB_DEBUG_INIT(_fmt, _arg...) \
-+ PSB_DEBUG(PSB_D_INIT, _fmt, ##_arg)
-+#define PSB_DEBUG_IRQ(_fmt, _arg...) \
-+ PSB_DEBUG(PSB_D_IRQ, _fmt, ##_arg)
-+#define PSB_DEBUG_RENDER(_fmt, _arg...) \
-+ PSB_DEBUG(PSB_D_RENDER, _fmt, ##_arg)
-+#define PSB_DEBUG_PERF(_fmt, _arg...) \
-+ PSB_DEBUG(PSB_D_PERF, _fmt, ##_arg)
-+#define PSB_DEBUG_TMP(_fmt, _arg...) \
-+ PSB_DEBUG(PSB_D_TMP, _fmt, ##_arg)
-+#define PSB_DEBUG_RELOC(_fmt, _arg...) \
-+ PSB_DEBUG(PSB_D_RELOC, _fmt, ##_arg)
-+
-+#if DRM_DEBUG_CODE
-+#define PSB_DEBUG(_flag, _fmt, _arg...) \
-+ do { \
-+ if (unlikely((_flag) & drm_psb_debug)) \
-+ printk(KERN_DEBUG \
-+ "[psb:0x%02x:%s] " _fmt , _flag, \
-+ __FUNCTION__ , ##_arg); \
-+ } while (0)
-+#else
-+#define PSB_DEBUG(_fmt, _arg...) do { } while (0)
-+#endif
++ atomic_inc(&vi->refcount);
++}
+
-+#endif
-Index: linux-2.6.28/drivers/gpu/drm/psb/psb_fb.c
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/psb/psb_fb.c 2009-02-12 09:14:41.000000000 +0000
-@@ -0,0 +1,1349 @@
-+/**************************************************************************
-+ * Copyright (c) 2007, Intel Corporation.
-+ * All Rights Reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms and conditions of the GNU General Public License,
-+ * version 2, as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
-+ *
-+ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
-+ * develop this driver.
-+ *
-+ **************************************************************************/
++static void psbfb_vm_close(struct vm_area_struct *vma)
++{
++ psbfb_vm_info_deref((struct psbfb_vm_info **)&vma->vm_private_data);
++}
+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/errno.h>
-+#include <linux/string.h>
-+#include <linux/mm.h>
-+#include <linux/tty.h>
-+#include <linux/slab.h>
-+#include <linux/delay.h>
-+#include <linux/fb.h>
-+#include <linux/init.h>
-+#include <linux/console.h>
++static struct vm_operations_struct psbfb_vm_ops = {
++ .fault = psbfb_fault,
++ .open = psbfb_vm_open,
++ .close = psbfb_vm_close,
++};
+
-+#include "drmP.h"
-+#include "drm.h"
-+#include "drm_crtc.h"
-+#include "psb_drv.h"
++static int psbfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
++{
++ struct psbfb_par *par = info->par;
++ struct drm_framebuffer *fb = par->crtc->fb;
++ struct drm_buffer_object *bo = fb->bo;
++ unsigned long size = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
++ unsigned long offset = vma->vm_pgoff;
+
-+#define SII_1392_WA
-+#ifdef SII_1392_WA
-+extern int SII_1392;
-+#endif
++ if (vma->vm_pgoff != 0)
++ return -EINVAL;
++ if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
++ return -EINVAL;
++ if (offset + size > bo->num_pages)
++ return -EINVAL;
+
-+struct psbfb_vm_info {
-+ struct drm_buffer_object *bo;
-+ struct address_space *f_mapping;
-+ struct mutex vm_mutex;
-+ atomic_t refcount;
-+};
++ mutex_lock(&par->vi->vm_mutex);
++ if (!par->vi->f_mapping)
++ par->vi->f_mapping = vma->vm_file->f_mapping;
++ mutex_unlock(&par->vi->vm_mutex);
+
-+struct psbfb_par {
-+ struct drm_device *dev;
-+ struct drm_crtc *crtc;
-+ struct drm_connector *output;
-+ struct psbfb_vm_info *vi;
-+ int dpms_state;
-+};
++ vma->vm_private_data = psbfb_vm_info_ref(par->vi);
+
-+static void psbfb_vm_info_deref(struct psbfb_vm_info **vi)
-+{
-+ struct psbfb_vm_info *tmp = *vi;
-+ *vi = NULL;
-+ if (atomic_dec_and_test(&tmp->refcount)) {
-+ drm_bo_usage_deref_unlocked(&tmp->bo);
-+ drm_free(tmp, sizeof(*tmp), DRM_MEM_MAPS);
-+ }
-+}
++ vma->vm_ops = &psbfb_vm_ops;
++ vma->vm_flags |= VM_PFNMAP;
+
-+static struct psbfb_vm_info *psbfb_vm_info_ref(struct psbfb_vm_info *vi)
-+{
-+ atomic_inc(&vi->refcount);
-+ return vi;
++ return 0;
+}
+
-+static struct psbfb_vm_info *psbfb_vm_info_create(void)
++int psbfb_sync(struct fb_info *info)
+{
-+ struct psbfb_vm_info *vi;
++ struct psbfb_par *par = info->par;
++ struct drm_psb_private *dev_priv = par->dev->dev_private;
+
-+ vi = drm_calloc(1, sizeof(*vi), DRM_MEM_MAPS);
-+ if (!vi)
-+ return NULL;
++ psb_2d_lock(dev_priv);
++ psb_idle_2d(par->dev);
++ psb_2d_unlock(dev_priv);
+
-+ mutex_init(&vi->vm_mutex);
-+ atomic_set(&vi->refcount, 1);
-+ return vi;
++ return 0;
+}
+
-+#define CMAP_TOHW(_val, _width) ((((_val) << (_width)) + 0x7FFF - (_val)) >> 16)
++static struct fb_ops psbfb_ops = {
++ .owner = THIS_MODULE,
++ .fb_check_var = psbfb_check_var,
++ .fb_set_par = psbfb_set_par,
++ .fb_setcolreg = psbfb_setcolreg,
++ .fb_fillrect = psbfb_fillrect,
++ .fb_copyarea = psbfb_copyarea,
++ .fb_imageblit = psbfb_imageblit,
++ .fb_mmap = psbfb_mmap,
++ .fb_sync = psbfb_sync,
++ .fb_blank = psbfb_blank,
++};
+
-+static int psbfb_setcolreg(unsigned regno, unsigned red, unsigned green,
-+ unsigned blue, unsigned transp, struct fb_info *info)
++static void psb_user_framebuffer_destroy(struct drm_framebuffer *fb)
+{
-+ struct psbfb_par *par = info->par;
-+ struct drm_crtc *crtc = par->crtc;
-+ uint32_t v;
++ drm_framebuffer_cleanup(fb);
++ kfree(fb);
++}
+
-+ if (!crtc->fb)
-+ return -ENOMEM;
++static const struct drm_framebuffer_funcs psb_fb_funcs = {
++ .destroy = psb_user_framebuffer_destroy,
++};
+
-+ if (regno > 255)
-+ return 1;
++int psbfb_probe(struct drm_device *dev, struct drm_crtc *crtc)
++{
++ struct fb_info *info;
++ struct psbfb_par *par;
++ struct device *device = &dev->pdev->dev;
++ struct drm_framebuffer *fb;
++ struct drm_display_mode *mode = crtc->desired_mode;
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
++ struct drm_buffer_object *fbo = NULL;
++ int ret;
++ int is_iomem;
+
-+ if (crtc->funcs->gamma_set)
-+ crtc->funcs->gamma_set(crtc, red, green, blue, regno);
++ if (drm_psb_no_fb) {
++ /* need to do this as the DRM will disable the output */
++ crtc->enabled = 1;
++ return 0;
++ }
+
-+ red = CMAP_TOHW(red, info->var.red.length);
-+ blue = CMAP_TOHW(blue, info->var.blue.length);
-+ green = CMAP_TOHW(green, info->var.green.length);
-+ transp = CMAP_TOHW(transp, info->var.transp.length);
++ fb = kzalloc(sizeof(struct drm_framebuffer), GFP_KERNEL);
++ if (!fb)
++ return -ENOMEM;
+
-+ v = (red << info->var.red.offset) |
-+ (green << info->var.green.offset) |
-+ (blue << info->var.blue.offset) |
-+ (transp << info->var.transp.offset);
+
-+ switch (crtc->fb->bits_per_pixel) {
-+ case 16:
-+ ((uint32_t *) info->pseudo_palette)[regno] = v;
-+ break;
-+ case 24:
-+ case 32:
-+ ((uint32_t *) info->pseudo_palette)[regno] = v;
-+ break;
++ ret = drm_framebuffer_init(dev, fb, &psb_fb_funcs);
++ if (!fb) {
++ DRM_ERROR("failed to allocate fb.\n");
++ return -ENOMEM;
+ }
++ crtc->fb = fb;
+
-+ return 0;
-+}
++ fb->width = mode->hdisplay;
++ fb->height = mode->vdisplay;
+
-+static int psbfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
-+{
-+ struct psbfb_par *par = info->par;
-+ struct drm_device *dev = par->dev;
-+ struct drm_framebuffer *fb = par->crtc->fb;
-+ struct drm_display_mode *drm_mode;
-+ struct drm_connector *output;
-+ int depth;
-+ int pitch;
-+ int bpp = var->bits_per_pixel;
++ fb->bits_per_pixel = 32;
++ fb->depth = 24;
++ fb->pitch =
++ ((fb->width * ((fb->bits_per_pixel + 1) / 8)) + 0x3f) & ~0x3f;
+
-+ if (!fb)
++ info = framebuffer_alloc(sizeof(struct psbfb_par), device);
++ if (!info) {
++ kfree(fb);
+ return -ENOMEM;
++ }
+
-+ if (!var->pixclock)
-+ return -EINVAL;
++ ret = drm_buffer_object_create(dev,
++ fb->pitch * fb->height,
++ drm_bo_type_kernel,
++ DRM_BO_FLAG_READ |
++ DRM_BO_FLAG_WRITE |
++ DRM_BO_FLAG_MEM_TT |
++ DRM_BO_FLAG_MEM_VRAM |
++ DRM_BO_FLAG_NO_EVICT,
++ DRM_BO_HINT_DONT_FENCE, 0, 0, &fbo);
++ if (ret || !fbo) {
++ DRM_ERROR("failed to allocate framebuffer\n");
++ goto out_err0;
++ }
+
-+ /* don't support virtuals for now */
-+ if (var->xres_virtual > var->xres)
-+ return -EINVAL;
++ fb->offset = fbo->offset - dev_priv->pg->gatt_start;
++ fb->bo = fbo;
++ DRM_DEBUG("allocated %dx%d fb: 0x%08lx, bo %p\n", fb->width,
++ fb->height, fb->offset, fbo);
+
-+ if (var->yres_virtual > var->yres)
-+ return -EINVAL;
++ fb->fbdev = info;
+
-+ switch (bpp) {
-+ case 8:
-+ depth = 8;
-+ break;
-+ case 16:
-+ depth = (var->green.length == 6) ? 16 : 15;
-+ break;
-+ case 24: /* assume this is 32bpp / depth 24 */
-+ bpp = 32;
-+ /* fallthrough */
-+ case 32:
-+ depth = (var->transp.length > 0) ? 32 : 24;
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
++ par = info->par;
+
-+ pitch = ((var->xres * ((bpp + 1) / 8)) + 0x3f) & ~0x3f;
++ par->dev = dev;
++ par->crtc = crtc;
++ par->vi = psbfb_vm_info_create();
++ if (!par->vi)
++ goto out_err1;
+
-+ /* Check that we can resize */
-+ if ((pitch * var->yres) > (fb->bo->num_pages << PAGE_SHIFT)) {
-+#if 1
-+ /* Need to resize the fb object.
-+ * But the generic fbdev code doesn't really understand
-+ * that we can do this. So disable for now.
-+ */
-+ DRM_INFO("Can't support requested size, too big!\n");
-+ return -EINVAL;
-+#else
-+ int ret;
-+ struct drm_buffer_object *fbo = NULL;
-+ struct drm_bo_kmap_obj tmp_kmap;
++ mutex_lock(&dev->struct_mutex);
++ par->vi->bo = fbo;
++ atomic_inc(&fbo->usage);
++ mutex_unlock(&dev->struct_mutex);
+
-+ /* a temporary BO to check if we could resize in setpar.
-+ * Therefore no need to set NO_EVICT.
-+ */
-+ ret = drm_buffer_object_create(dev,
-+ pitch * var->yres,
-+ drm_bo_type_kernel,
-+ DRM_BO_FLAG_READ |
-+ DRM_BO_FLAG_WRITE |
-+ DRM_BO_FLAG_MEM_TT |
-+ DRM_BO_FLAG_MEM_VRAM,
-+ DRM_BO_HINT_DONT_FENCE,
-+ 0, 0, &fbo);
-+ if (ret || !fbo)
-+ return -ENOMEM;
++ par->vi->f_mapping = NULL;
++ info->fbops = &psbfb_ops;
+
-+ ret = drm_bo_kmap(fbo, 0, fbo->num_pages, &tmp_kmap);
-+ if (ret) {
-+ drm_bo_usage_deref_unlocked(&fbo);
-+ return -EINVAL;
-+ }
++ strcpy(info->fix.id, "psbfb");
++ info->fix.type = FB_TYPE_PACKED_PIXELS;
++ info->fix.visual = FB_VISUAL_DIRECTCOLOR;
++ info->fix.type_aux = 0;
++ info->fix.xpanstep = 1;
++ info->fix.ypanstep = 1;
++ info->fix.ywrapstep = 0;
++ info->fix.accel = FB_ACCEL_NONE; /* ??? */
++ info->fix.type_aux = 0;
++ info->fix.mmio_start = 0;
++ info->fix.mmio_len = 0;
++ info->fix.line_length = fb->pitch;
++ info->fix.smem_start = dev->mode_config.fb_base + fb->offset;
++ info->fix.smem_len = info->fix.line_length * fb->height;
+
-+ drm_bo_kunmap(&tmp_kmap);
-+ /* destroy our current fbo! */
-+ drm_bo_usage_deref_unlocked(&fbo);
-+#endif
++ info->flags = FBINFO_DEFAULT |
++ FBINFO_PARTIAL_PAN_OK /*| FBINFO_MISC_ALWAYS_SETPAR */ ;
++
++ ret = drm_bo_kmap(fb->bo, 0, fb->bo->num_pages, &fb->kmap);
++ if (ret) {
++ DRM_ERROR("error mapping fb: %d\n", ret);
++ goto out_err2;
+ }
+
-+ switch (depth) {
++ info->screen_base = drm_bmo_virtual(&fb->kmap, &is_iomem);
++ memset(info->screen_base, 0x00, fb->pitch*fb->height);
++ info->screen_size = info->fix.smem_len; /* FIXME */
++ info->pseudo_palette = fb->pseudo_palette;
++ info->var.xres_virtual = fb->width;
++ info->var.yres_virtual = fb->height;
++ info->var.bits_per_pixel = fb->bits_per_pixel;
++ info->var.xoffset = 0;
++ info->var.yoffset = 0;
++ info->var.activate = FB_ACTIVATE_NOW;
++ info->var.height = -1;
++ info->var.width = -1;
++ info->var.vmode = FB_VMODE_NONINTERLACED;
++
++ info->var.xres = mode->hdisplay;
++ info->var.right_margin = mode->hsync_start - mode->hdisplay;
++ info->var.hsync_len = mode->hsync_end - mode->hsync_start;
++ info->var.left_margin = mode->htotal - mode->hsync_end;
++ info->var.yres = mode->vdisplay;
++ info->var.lower_margin = mode->vsync_start - mode->vdisplay;
++ info->var.vsync_len = mode->vsync_end - mode->vsync_start;
++ info->var.upper_margin = mode->vtotal - mode->vsync_end;
++ info->var.pixclock = 10000000 / mode->htotal * 1000 /
++ mode->vtotal * 100;
++ /* avoid overflow */
++ info->var.pixclock = info->var.pixclock * 1000 / mode->vrefresh;
++
++ info->pixmap.size = 64 * 1024;
++ info->pixmap.buf_align = 8;
++ info->pixmap.access_align = 32;
++ info->pixmap.flags = FB_PIXMAP_SYSTEM;
++ info->pixmap.scan_align = 1;
++
++ DRM_DEBUG("fb depth is %d\n", fb->depth);
++ DRM_DEBUG(" pitch is %d\n", fb->pitch);
++ switch (fb->depth) {
+ case 8:
-+ var->red.offset = 0;
-+ var->green.offset = 0;
-+ var->blue.offset = 0;
-+ var->red.length = 8;
-+ var->green.length = 8;
-+ var->blue.length = 8;
-+ var->transp.length = 0;
-+ var->transp.offset = 0;
++ info->var.red.offset = 0;
++ info->var.green.offset = 0;
++ info->var.blue.offset = 0;
++ info->var.red.length = 8; /* 8bit DAC */
++ info->var.green.length = 8;
++ info->var.blue.length = 8;
++ info->var.transp.offset = 0;
++ info->var.transp.length = 0;
+ break;
+ case 15:
-+ var->red.offset = 10;
-+ var->green.offset = 5;
-+ var->blue.offset = 0;
-+ var->red.length = 5;
-+ var->green.length = 5;
-+ var->blue.length = 5;
-+ var->transp.length = 1;
-+ var->transp.offset = 15;
++ info->var.red.offset = 10;
++ info->var.green.offset = 5;
++ info->var.blue.offset = 0;
++ info->var.red.length = info->var.green.length =
++ info->var.blue.length = 5;
++ info->var.transp.offset = 15;
++ info->var.transp.length = 1;
+ break;
+ case 16:
-+ var->red.offset = 11;
-+ var->green.offset = 5;
-+ var->blue.offset = 0;
-+ var->red.length = 5;
-+ var->green.length = 6;
-+ var->blue.length = 5;
-+ var->transp.length = 0;
-+ var->transp.offset = 0;
++ info->var.red.offset = 11;
++ info->var.green.offset = 5;
++ info->var.blue.offset = 0;
++ info->var.red.length = 5;
++ info->var.green.length = 6;
++ info->var.blue.length = 5;
++ info->var.transp.offset = 0;
+ break;
+ case 24:
-+ var->red.offset = 16;
-+ var->green.offset = 8;
-+ var->blue.offset = 0;
-+ var->red.length = 8;
-+ var->green.length = 8;
-+ var->blue.length = 8;
-+ var->transp.length = 0;
-+ var->transp.offset = 0;
++ info->var.red.offset = 16;
++ info->var.green.offset = 8;
++ info->var.blue.offset = 0;
++ info->var.red.length = info->var.green.length =
++ info->var.blue.length = 8;
++ info->var.transp.offset = 0;
++ info->var.transp.length = 0;
+ break;
+ case 32:
-+ var->red.offset = 16;
-+ var->green.offset = 8;
-+ var->blue.offset = 0;
-+ var->red.length = 8;
-+ var->green.length = 8;
-+ var->blue.length = 8;
-+ var->transp.length = 8;
-+ var->transp.offset = 24;
++ info->var.red.offset = 16;
++ info->var.green.offset = 8;
++ info->var.blue.offset = 0;
++ info->var.red.length = info->var.green.length =
++ info->var.blue.length = 8;
++ info->var.transp.offset = 24;
++ info->var.transp.length = 8;
+ break;
+ default:
-+ return -EINVAL;
++ break;
+ }
+
-+#if 0
-+ /* Here we walk the output mode list and look for modes. If we haven't
-+ * got it, then bail. Not very nice, so this is disabled.
-+ * In the set_par code, we create our mode based on the incoming
-+ * parameters. Nicer, but may not be desired by some.
-+ */
-+ list_for_each_entry(output, &dev->mode_config.connector_list, head) {
-+ if (output->crtc == par->crtc)
-+ break;
-+ }
++ if (register_framebuffer(info) < 0)
++ goto out_err3;
+
-+ list_for_each_entry(drm_mode, &output->modes, head) {
-+ if (drm_mode->hdisplay == var->xres &&
-+ drm_mode->vdisplay == var->yres && drm_mode->clock != 0)
-+ break;
-+ }
++ if (psbfb_check_var(&info->var, info) < 0)
++ goto out_err4;
+
-+ if (!drm_mode)
-+ return -EINVAL;
-+#else
-+ (void)dev; /* silence warnings */
-+ (void)output;
-+ (void)drm_mode;
-+#endif
++ psbfb_set_par(info);
++
++ DRM_INFO("fb%d: %s frame buffer device\n", info->node, info->fix.id);
+
+ return 0;
++ out_err4:
++ unregister_framebuffer(info);
++ out_err3:
++ drm_bo_kunmap(&fb->kmap);
++ out_err2:
++ psbfb_vm_info_deref(&par->vi);
++ out_err1:
++ drm_bo_usage_deref_unlocked(&fb->bo);
++ out_err0:
++ drm_framebuffer_cleanup(fb);
++ framebuffer_release(info);
++ crtc->fb = NULL;
++ return -EINVAL;
+}
+
-+static int psbfb_move_fb_bo(struct fb_info *info, struct drm_buffer_object *bo,
-+ uint64_t mem_type_flags)
++EXPORT_SYMBOL(psbfb_probe);
++
++int psbfb_remove(struct drm_device *dev, struct drm_crtc *crtc)
+{
++ struct drm_framebuffer *fb;
++ struct fb_info *info;
+ struct psbfb_par *par;
-+ loff_t holelen;
-+ int ret;
+
-+ /*
-+ * Kill all user-space mappings of this device. They will be
-+ * faulted back using nopfn when accessed.
-+ */
-+
-+ par = info->par;
-+ holelen = ((loff_t) bo->mem.num_pages) << PAGE_SHIFT;
-+ mutex_lock(&par->vi->vm_mutex);
-+ if (par->vi->f_mapping) {
-+ unmap_mapping_range(par->vi->f_mapping, 0, holelen, 1);
-+ }
++ if (drm_psb_no_fb)
++ return 0;
+
-+ ret = drm_bo_do_validate(bo,
-+ mem_type_flags,
-+ DRM_BO_MASK_MEM |
-+ DRM_BO_FLAG_NO_EVICT,
-+ DRM_BO_HINT_DONT_FENCE, 0, 1, NULL);
++ fb = crtc->fb;
++ info = fb->fbdev;
+
-+ mutex_unlock(&par->vi->vm_mutex);
-+ return ret;
++ if (info) {
++ unregister_framebuffer(info);
++ drm_bo_kunmap(&fb->kmap);
++ par = info->par;
++ if (par)
++ psbfb_vm_info_deref(&par->vi);
++ drm_bo_usage_deref_unlocked(&fb->bo);
++ drm_framebuffer_cleanup(fb);
++ framebuffer_release(info);
++ }
++ return 0;
+}
+
-+/* this will let fbcon do the mode init */
-+static int psbfb_set_par(struct fb_info *info)
-+{
-+ struct psbfb_par *par = info->par;
-+ struct drm_framebuffer *fb = par->crtc->fb;
-+ struct drm_device *dev = par->dev;
-+ struct drm_display_mode *drm_mode;
-+ struct fb_var_screeninfo *var = &info->var;
-+ struct drm_psb_private *dev_priv = dev->dev_private;
-+ struct drm_connector *output;
-+ int pitch;
-+ int depth;
-+ int bpp = var->bits_per_pixel;
++EXPORT_SYMBOL(psbfb_remove);
+
-+ if (!fb)
-+ return -ENOMEM;
+Index: linux-2.6.28/drivers/gpu/drm/psb/psb_fence.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.28/drivers/gpu/drm/psb/psb_fence.c 2009-02-12 09:14:41.000000000 +0000
+@@ -0,0 +1,285 @@
++/**************************************************************************
++ * Copyright (c) 2007, Intel Corporation.
++ * All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
++ *
++ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
++ * develop this driver.
++ *
++ **************************************************************************/
++/*
++ * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
++ */
+
-+ switch (bpp) {
-+ case 8:
-+ depth = 8;
-+ break;
-+ case 16:
-+ depth = (var->green.length == 6) ? 16 : 15;
-+ break;
-+ case 24: /* assume this is 32bpp / depth 24 */
-+ bpp = 32;
-+ /* fallthrough */
-+ case 32:
-+ depth = (var->transp.length > 0) ? 32 : 24;
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
++#include "drmP.h"
++#include "psb_drv.h"
+
-+ pitch = ((var->xres * ((bpp + 1) / 8)) + 0x3f) & ~0x3f;
++static void psb_poll_ta(struct drm_device *dev, uint32_t waiting_types)
++{
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
++ struct drm_fence_driver *driver = dev->driver->fence_driver;
++ uint32_t cur_flag = 1;
++ uint32_t flags = 0;
++ uint32_t sequence = 0;
++ uint32_t remaining = 0xFFFFFFFF;
++ uint32_t diff;
+
-+ if ((pitch * var->yres) > (fb->bo->num_pages << PAGE_SHIFT)) {
-+#if 1
-+ /* Need to resize the fb object.
-+ * But the generic fbdev code doesn't really understand
-+ * that we can do this. So disable for now.
-+ */
-+ DRM_INFO("Can't support requested size, too big!\n");
-+ return -EINVAL;
-+#else
-+ int ret;
-+ struct drm_buffer_object *fbo = NULL, *tfbo;
-+ struct drm_bo_kmap_obj tmp_kmap, tkmap;
++ struct psb_scheduler *scheduler;
++ struct psb_scheduler_seq *seq;
++ struct drm_fence_class_manager *fc =
++ &dev->fm.fence_class[PSB_ENGINE_TA];
+
-+ ret = drm_buffer_object_create(dev,
-+ pitch * var->yres,
-+ drm_bo_type_kernel,
-+ DRM_BO_FLAG_READ |
-+ DRM_BO_FLAG_WRITE |
-+ DRM_BO_FLAG_MEM_TT |
-+ DRM_BO_FLAG_MEM_VRAM |
-+ DRM_BO_FLAG_NO_EVICT,
-+ DRM_BO_HINT_DONT_FENCE,
-+ 0, 0, &fbo);
-+ if (ret || !fbo) {
-+ DRM_ERROR
-+ ("failed to allocate new resized framebuffer\n");
-+ return -ENOMEM;
-+ }
++ if (unlikely(!dev_priv))
++ return;
+
-+ ret = drm_bo_kmap(fbo, 0, fbo->num_pages, &tmp_kmap);
-+ if (ret) {
-+ DRM_ERROR("failed to kmap framebuffer.\n");
-+ drm_bo_usage_deref_unlocked(&fbo);
-+ return -EINVAL;
++ scheduler = &dev_priv->scheduler;
++ seq = scheduler->seq;
++
++ while (likely(waiting_types & remaining)) {
++ if (!(waiting_types & cur_flag))
++ goto skip;
++ if (seq->reported)
++ goto skip;
++ if (flags == 0)
++ sequence = seq->sequence;
++ else if (sequence != seq->sequence) {
++ drm_fence_handler(dev, PSB_ENGINE_TA,
++ sequence, flags, 0);
++ sequence = seq->sequence;
++ flags = 0;
+ }
++ flags |= cur_flag;
+
-+ DRM_DEBUG("allocated %dx%d fb: 0x%08lx, bo %p\n", fb->width,
-+ fb->height, fb->offset, fbo);
++ /*
++ * Sequence may not have ended up on the ring yet.
++ * In that case, report it but don't mark it as
++ * reported. A subsequent poll will report it again.
++ */
+
-+ /* set new screen base */
-+ info->screen_base = tmp_kmap.virtual;
++ diff = (fc->latest_queued_sequence - sequence) &
++ driver->sequence_mask;
++ if (diff < driver->wrap_diff)
++ seq->reported = 1;
+
-+ tkmap = fb->kmap;
-+ fb->kmap = tmp_kmap;
-+ drm_bo_kunmap(&tkmap);
++ skip:
++ cur_flag <<= 1;
++ remaining <<= 1;
++ seq++;
++ }
+
-+ tfbo = fb->bo;
-+ fb->bo = fbo;
-+ drm_bo_usage_deref_unlocked(&tfbo);
-+#endif
++ if (flags) {
++ drm_fence_handler(dev, PSB_ENGINE_TA, sequence, flags, 0);
+ }
++}
+
-+ fb->offset = fb->bo->offset - dev_priv->pg->gatt_start;
-+ fb->width = var->xres;
-+ fb->height = var->yres;
-+ fb->bits_per_pixel = bpp;
-+ fb->pitch = pitch;
-+ fb->depth = depth;
++static void psb_poll_other(struct drm_device *dev, uint32_t fence_class,
++ uint32_t waiting_types)
++{
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
++ struct drm_fence_manager *fm = &dev->fm;
++ struct drm_fence_class_manager *fc = &fm->fence_class[fence_class];
++ uint32_t sequence;
+
-+ info->fix.line_length = fb->pitch;
-+ info->fix.visual =
-+ (fb->depth == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
++ if (unlikely(!dev_priv))
++ return;
+
-+ /* some fbdev's apps don't want these to change */
-+ info->fix.smem_start = dev->mode_config.fb_base + fb->offset;
++ if (waiting_types) {
++ if (fence_class == PSB_ENGINE_VIDEO)
++ sequence = dev_priv->msvdx_current_sequence;
++ else
++ sequence = dev_priv->comm[fence_class << 4];
+
-+ /* we have to align the output base address because the fb->bo
-+ may be moved in the previous drm_bo_do_validate().
-+ Otherwise the output screens may go black when exit the X
-+ window and re-enter the console */
-+ info->screen_base = fb->kmap.virtual;
++ drm_fence_handler(dev, fence_class, sequence,
++ DRM_FENCE_TYPE_EXE, 0);
+
++ switch (fence_class) {
++ case PSB_ENGINE_2D:
++ if (dev_priv->fence0_irq_on && !fc->waiting_types) {
++ psb_2D_irq_off(dev_priv);
++ dev_priv->fence0_irq_on = 0;
++ } else if (!dev_priv->fence0_irq_on
++ && fc->waiting_types) {
++ psb_2D_irq_on(dev_priv);
++ dev_priv->fence0_irq_on = 1;
++ }
++ break;
+#if 0
-+ /* relates to resize - disable */
-+ info->fix.smem_len = info->fix.line_length * var->yres;
-+ info->screen_size = info->fix.smem_len; /* ??? */
-+#endif
++ /*
++ * FIXME: MSVDX irq switching
++ */
+
-+ /* Should we walk the output's modelist or just create our own ???
-+ * For now, we create and destroy a mode based on the incoming
-+ * parameters. But there's commented out code below which scans
-+ * the output list too.
-+ */
-+#if 0
-+ list_for_each_entry(output, &dev->mode_config.connector_list, head) {
-+ if (output->crtc == par->crtc)
++ case PSB_ENGINE_VIDEO:
++ if (dev_priv->fence2_irq_on && !fc->waiting_types) {
++ psb_msvdx_irq_off(dev_priv);
++ dev_priv->fence2_irq_on = 0;
++ } else if (!dev_priv->fence2_irq_on
++ && fc->pending_exe_flush) {
++ psb_msvdx_irq_on(dev_priv);
++ dev_priv->fence2_irq_on = 1;
++ }
+ break;
-+ }
-+
-+ list_for_each_entry(drm_mode, &output->modes, head) {
-+ if (drm_mode->hdisplay == var->xres &&
-+ drm_mode->vdisplay == var->yres && drm_mode->clock != 0)
-+ break;
-+ }
-+#else
-+ (void)output; /* silence warning */
-+
-+ drm_mode = drm_mode_create(dev);
-+ drm_mode->hdisplay = var->xres;
-+ drm_mode->hsync_start = drm_mode->hdisplay + var->right_margin;
-+ drm_mode->hsync_end = drm_mode->hsync_start + var->hsync_len;
-+ drm_mode->htotal = drm_mode->hsync_end + var->left_margin;
-+ drm_mode->vdisplay = var->yres;
-+ drm_mode->vsync_start = drm_mode->vdisplay + var->lower_margin;
-+ drm_mode->vsync_end = drm_mode->vsync_start + var->vsync_len;
-+ drm_mode->vtotal = drm_mode->vsync_end + var->upper_margin;
-+ drm_mode->clock = PICOS2KHZ(var->pixclock);
-+ drm_mode->vrefresh = drm_mode_vrefresh(drm_mode);
-+ drm_mode_set_name(drm_mode);
-+ drm_mode_set_crtcinfo(drm_mode, CRTC_INTERLACE_HALVE_V);
-+#endif
-+
-+ if (!drm_crtc_helper_set_mode(par->crtc, drm_mode, 0, 0, NULL))
-+ return -EINVAL;
-+
-+ /* Have to destroy our created mode if we're not searching the mode
-+ * list for it.
-+ */
-+#if 1
-+ drm_mode_destroy(dev, drm_mode);
+#endif
-+
-+ return 0;
++ default:
++ return;
++ }
++ }
+}
+
-+extern int psb_2d_submit(struct drm_psb_private *, uint32_t *, uint32_t);;
-+
-+static int psb_accel_2d_fillrect(struct drm_psb_private *dev_priv,
-+ uint32_t dst_offset, uint32_t dst_stride,
-+ uint32_t dst_format, uint16_t dst_x,
-+ uint16_t dst_y, uint16_t size_x,
-+ uint16_t size_y, uint32_t fill)
++static void psb_fence_poll(struct drm_device *dev,
++ uint32_t fence_class, uint32_t waiting_types)
+{
-+ uint32_t buffer[10];
-+ uint32_t *buf;
-+ int ret;
-+
-+ buf = buffer;
-+
-+ *buf++ = PSB_2D_FENCE_BH;
-+
-+ *buf++ =
-+ PSB_2D_DST_SURF_BH | dst_format | (dst_stride <<
-+ PSB_2D_DST_STRIDE_SHIFT);
-+ *buf++ = dst_offset;
-+
-+ *buf++ =
-+ PSB_2D_BLIT_BH |
-+ PSB_2D_ROT_NONE |
-+ PSB_2D_COPYORDER_TL2BR |
-+ PSB_2D_DSTCK_DISABLE |
-+ PSB_2D_SRCCK_DISABLE | PSB_2D_USE_FILL | PSB_2D_ROP3_PATCOPY;
-+
-+ *buf++ = fill << PSB_2D_FILLCOLOUR_SHIFT;
-+ *buf++ =
-+ (dst_x << PSB_2D_DST_XSTART_SHIFT) | (dst_y <<
-+ PSB_2D_DST_YSTART_SHIFT);
-+ *buf++ =
-+ (size_x << PSB_2D_DST_XSIZE_SHIFT) | (size_y <<
-+ PSB_2D_DST_YSIZE_SHIFT);
-+ *buf++ = PSB_2D_FLUSH_BH;
++ switch (fence_class) {
++ case PSB_ENGINE_TA:
++ psb_poll_ta(dev, waiting_types);
++ break;
++ default:
++ psb_poll_other(dev, fence_class, waiting_types);
++ break;
++ }
++}
+
-+ psb_2d_lock(dev_priv);
-+ ret = psb_2d_submit(dev_priv, buffer, buf - buffer);
-+ psb_2d_unlock(dev_priv);
++void psb_fence_error(struct drm_device *dev,
++ uint32_t fence_class,
++ uint32_t sequence, uint32_t type, int error)
++{
++ struct drm_fence_manager *fm = &dev->fm;
++ unsigned long irq_flags;
+
-+ return ret;
++ BUG_ON(fence_class >= PSB_NUM_ENGINES);
++ write_lock_irqsave(&fm->lock, irq_flags);
++ drm_fence_handler(dev, fence_class, sequence, type, error);
++ write_unlock_irqrestore(&fm->lock, irq_flags);
+}
+
-+static void psbfb_fillrect_accel(struct fb_info *info,
-+ const struct fb_fillrect *r)
++int psb_fence_emit_sequence(struct drm_device *dev, uint32_t fence_class,
++ uint32_t flags, uint32_t * sequence,
++ uint32_t * native_type)
+{
-+ struct psbfb_par *par = info->par;
-+ struct drm_framebuffer *fb = par->crtc->fb;
-+ struct drm_psb_private *dev_priv = par->dev->dev_private;
-+ uint32_t offset;
-+ uint32_t stride;
-+ uint32_t format;
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
++ uint32_t seq = 0;
++ int ret;
+
-+ if (!fb)
-+ return;
++ if (!dev_priv)
++ return -EINVAL;
+
-+ offset = fb->offset;
-+ stride = fb->pitch;
++ if (fence_class >= PSB_NUM_ENGINES)
++ return -EINVAL;
+
-+ switch (fb->depth) {
-+ case 8:
-+ format = PSB_2D_DST_332RGB;
-+ break;
-+ case 15:
-+ format = PSB_2D_DST_555RGB;
-+ break;
-+ case 16:
-+ format = PSB_2D_DST_565RGB;
++ switch (fence_class) {
++ case PSB_ENGINE_2D:
++ spin_lock(&dev_priv->sequence_lock);
++ seq = ++dev_priv->sequence[fence_class];
++ spin_unlock(&dev_priv->sequence_lock);
++ ret = psb_blit_sequence(dev_priv, seq);
++ if (ret)
++ return ret;
+ break;
-+ case 24:
-+ case 32:
-+ /* this is wrong but since we don't do blending its okay */
-+ format = PSB_2D_DST_8888ARGB;
++ case PSB_ENGINE_VIDEO:
++ spin_lock(&dev_priv->sequence_lock);
++ seq = ++dev_priv->sequence[fence_class];
++ spin_unlock(&dev_priv->sequence_lock);
+ break;
+ default:
-+ /* software fallback */
-+ cfb_fillrect(info, r);
-+ return;
++ spin_lock(&dev_priv->sequence_lock);
++ seq = dev_priv->sequence[fence_class];
++ spin_unlock(&dev_priv->sequence_lock);
+ }
+
-+ psb_accel_2d_fillrect(dev_priv,
-+ offset, stride, format,
-+ r->dx, r->dy, r->width, r->height, r->color);
++ *sequence = seq;
++ *native_type = DRM_FENCE_TYPE_EXE;
++
++ return 0;
+}
+
-+static void psbfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
++uint32_t psb_fence_advance_sequence(struct drm_device * dev,
++ uint32_t fence_class)
+{
-+ if (info->state != FBINFO_STATE_RUNNING)
-+ return;
-+ if (info->flags & FBINFO_HWACCEL_DISABLED) {
-+ cfb_fillrect(info, rect);
-+ return;
-+ }
-+ if (in_interrupt() || in_atomic()) {
-+ /*
-+ * Catch case when we're shutting down.
-+ */
-+ cfb_fillrect(info, rect);
-+ return;
-+ }
-+ psbfb_fillrect_accel(info, rect);
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
++ uint32_t sequence;
++
++ spin_lock(&dev_priv->sequence_lock);
++ sequence = ++dev_priv->sequence[fence_class];
++ spin_unlock(&dev_priv->sequence_lock);
++
++ return sequence;
+}
+
-+uint32_t psb_accel_2d_copy_direction(int xdir, int ydir)
++void psb_fence_handler(struct drm_device *dev, uint32_t fence_class)
+{
-+ if (xdir < 0)
-+ return ((ydir <
-+ 0) ? PSB_2D_COPYORDER_BR2TL : PSB_2D_COPYORDER_TR2BL);
-+ else
-+ return ((ydir <
-+ 0) ? PSB_2D_COPYORDER_BL2TR : PSB_2D_COPYORDER_TL2BR);
++ struct drm_fence_manager *fm = &dev->fm;
++ struct drm_fence_class_manager *fc = &fm->fence_class[fence_class];
++
++#ifdef FIX_TG_16
++ if (fence_class == 0) {
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
++
++ if ((atomic_read(&dev_priv->ta_wait_2d_irq) == 1) &&
++ (PSB_RSGX32(PSB_CR_2D_SOCIF) == _PSB_C2_SOCIF_EMPTY) &&
++ ((PSB_RSGX32(PSB_CR_2D_BLIT_STATUS) &
++ _PSB_C2B_STATUS_BUSY) == 0))
++ psb_resume_ta_2d_idle(dev_priv);
++ }
++#endif
++ write_lock(&fm->lock);
++ psb_fence_poll(dev, fence_class, fc->waiting_types);
++ write_unlock(&fm->lock);
+}
+
-+/*
-+ * @srcOffset in bytes
-+ * @srcStride in bytes
-+ * @srcFormat psb 2D format defines
-+ * @dstOffset in bytes
-+ * @dstStride in bytes
-+ * @dstFormat psb 2D format defines
-+ * @srcX offset in pixels
-+ * @srcY offset in pixels
-+ * @dstX offset in pixels
-+ * @dstY offset in pixels
-+ * @sizeX of the copied area
-+ * @sizeY of the copied area
-+ */
-+static int psb_accel_2d_copy(struct drm_psb_private *dev_priv,
-+ uint32_t src_offset, uint32_t src_stride,
-+ uint32_t src_format, uint32_t dst_offset,
-+ uint32_t dst_stride, uint32_t dst_format,
-+ uint16_t src_x, uint16_t src_y, uint16_t dst_x,
-+ uint16_t dst_y, uint16_t size_x, uint16_t size_y)
++static int psb_fence_wait(struct drm_fence_object *fence,
++ int lazy, int interruptible, uint32_t mask)
+{
-+ uint32_t blit_cmd;
-+ uint32_t buffer[10];
-+ uint32_t *buf;
-+ uint32_t direction;
-+ int ret;
++ struct drm_device *dev = fence->dev;
++ struct drm_fence_class_manager *fc =
++ &dev->fm.fence_class[fence->fence_class];
++ int ret = 0;
++ unsigned long timeout = DRM_HZ *
++ ((fence->fence_class == PSB_ENGINE_TA) ? 30 : 3);
+
-+ buf = buffer;
++ drm_fence_object_flush(fence, mask);
++ if (interruptible)
++ ret = wait_event_interruptible_timeout
++ (fc->fence_queue, drm_fence_object_signaled(fence, mask),
++ timeout);
++ else
++ ret = wait_event_timeout
++ (fc->fence_queue, drm_fence_object_signaled(fence, mask),
++ timeout);
+
-+ direction = psb_accel_2d_copy_direction(src_x - dst_x, src_y - dst_y);
++ if (unlikely(ret == -ERESTARTSYS))
++ return -EAGAIN;
+
-+ if (direction == PSB_2D_COPYORDER_BR2TL ||
-+ direction == PSB_2D_COPYORDER_TR2BL) {
-+ src_x += size_x - 1;
-+ dst_x += size_x - 1;
-+ }
-+ if (direction == PSB_2D_COPYORDER_BR2TL ||
-+ direction == PSB_2D_COPYORDER_BL2TR) {
-+ src_y += size_y - 1;
-+ dst_y += size_y - 1;
-+ }
-+
-+ blit_cmd =
-+ PSB_2D_BLIT_BH |
-+ PSB_2D_ROT_NONE |
-+ PSB_2D_DSTCK_DISABLE |
-+ PSB_2D_SRCCK_DISABLE |
-+ PSB_2D_USE_PAT | PSB_2D_ROP3_SRCCOPY | direction;
-+
-+ *buf++ = PSB_2D_FENCE_BH;
-+ *buf++ =
-+ PSB_2D_DST_SURF_BH | dst_format | (dst_stride <<
-+ PSB_2D_DST_STRIDE_SHIFT);
-+ *buf++ = dst_offset;
-+ *buf++ =
-+ PSB_2D_SRC_SURF_BH | src_format | (src_stride <<
-+ PSB_2D_SRC_STRIDE_SHIFT);
-+ *buf++ = src_offset;
-+ *buf++ =
-+ PSB_2D_SRC_OFF_BH | (src_x << PSB_2D_SRCOFF_XSTART_SHIFT) | (src_y
-+ <<
-+ PSB_2D_SRCOFF_YSTART_SHIFT);
-+ *buf++ = blit_cmd;
-+ *buf++ =
-+ (dst_x << PSB_2D_DST_XSTART_SHIFT) | (dst_y <<
-+ PSB_2D_DST_YSTART_SHIFT);
-+ *buf++ =
-+ (size_x << PSB_2D_DST_XSIZE_SHIFT) | (size_y <<
-+ PSB_2D_DST_YSIZE_SHIFT);
-+ *buf++ = PSB_2D_FLUSH_BH;
++ if (unlikely(ret == 0))
++ return -EBUSY;
+
-+ psb_2d_lock(dev_priv);
-+ ret = psb_2d_submit(dev_priv, buffer, buf - buffer);
-+ psb_2d_unlock(dev_priv);
-+ return ret;
++ return 0;
+}
+
-+static void psbfb_copyarea_accel(struct fb_info *info,
-+ const struct fb_copyarea *a)
-+{
-+ struct psbfb_par *par = info->par;
-+ struct drm_framebuffer *fb = par->crtc->fb;
-+ struct drm_psb_private *dev_priv = par->dev->dev_private;
-+ uint32_t offset;
-+ uint32_t stride;
-+ uint32_t src_format;
-+ uint32_t dst_format;
-+
-+ if (!fb)
-+ return;
-+
-+ offset = fb->offset;
-+ stride = fb->pitch;
++struct drm_fence_driver psb_fence_driver = {
++ .num_classes = PSB_NUM_ENGINES,
++ .wrap_diff = (1 << 30),
++ .flush_diff = (1 << 29),
++ .sequence_mask = 0xFFFFFFFFU,
++ .has_irq = NULL,
++ .emit = psb_fence_emit_sequence,
++ .flush = NULL,
++ .poll = psb_fence_poll,
++ .needed_flush = NULL,
++ .wait = psb_fence_wait
++};
+Index: linux-2.6.28/drivers/gpu/drm/psb/psb_gtt.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.28/drivers/gpu/drm/psb/psb_gtt.c 2009-02-12 09:14:41.000000000 +0000
+@@ -0,0 +1,233 @@
++/**************************************************************************
++ * Copyright (c) 2007, Intel Corporation.
++ * All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
++ *
++ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
++ * develop this driver.
++ *
++ **************************************************************************/
++/*
++ * Authors: Thomas Hellstrom <thomas-at-tungstengraphics.com>
++ */
++#include "drmP.h"
++#include "psb_drv.h"
+
-+ if (a->width == 8 || a->height == 8) {
-+ psb_2d_lock(dev_priv);
-+ psb_idle_2d(par->dev);
-+ psb_2d_unlock(dev_priv);
-+ cfb_copyarea(info, a);
-+ return;
-+ }
++static inline uint32_t psb_gtt_mask_pte(uint32_t pfn, int type)
++{
++ uint32_t mask = PSB_PTE_VALID;
+
-+ switch (fb->depth) {
-+ case 8:
-+ src_format = PSB_2D_SRC_332RGB;
-+ dst_format = PSB_2D_DST_332RGB;
-+ break;
-+ case 15:
-+ src_format = PSB_2D_SRC_555RGB;
-+ dst_format = PSB_2D_DST_555RGB;
-+ break;
-+ case 16:
-+ src_format = PSB_2D_SRC_565RGB;
-+ dst_format = PSB_2D_DST_565RGB;
-+ break;
-+ case 24:
-+ case 32:
-+ /* this is wrong but since we don't do blending its okay */
-+ src_format = PSB_2D_SRC_8888ARGB;
-+ dst_format = PSB_2D_DST_8888ARGB;
-+ break;
-+ default:
-+ /* software fallback */
-+ cfb_copyarea(info, a);
-+ return;
-+ }
++ if (type & PSB_MMU_CACHED_MEMORY)
++ mask |= PSB_PTE_CACHED;
++ if (type & PSB_MMU_RO_MEMORY)
++ mask |= PSB_PTE_RO;
++ if (type & PSB_MMU_WO_MEMORY)
++ mask |= PSB_PTE_WO;
+
-+ psb_accel_2d_copy(dev_priv,
-+ offset, stride, src_format,
-+ offset, stride, dst_format,
-+ a->sx, a->sy, a->dx, a->dy, a->width, a->height);
++ return (pfn << PAGE_SHIFT) | mask;
+}
+
-+static void psbfb_copyarea(struct fb_info *info,
-+ const struct fb_copyarea *region)
++struct psb_gtt *psb_gtt_alloc(struct drm_device *dev)
+{
-+ if (info->state != FBINFO_STATE_RUNNING)
-+ return;
-+ if (info->flags & FBINFO_HWACCEL_DISABLED) {
-+ cfb_copyarea(info, region);
-+ return;
-+ }
-+ if (in_interrupt() || in_atomic()) {
-+ /*
-+ * Catch case when we're shutting down.
-+ */
-+ cfb_copyarea(info, region);
-+ return;
-+ }
++ struct psb_gtt *tmp = drm_calloc(1, sizeof(*tmp), DRM_MEM_DRIVER);
+
-+ psbfb_copyarea_accel(info, region);
-+}
++ if (!tmp)
++ return NULL;
+
-+void psbfb_imageblit(struct fb_info *info, const struct fb_image *image)
-+{
-+ if (info->state != FBINFO_STATE_RUNNING)
-+ return;
-+ if (info->flags & FBINFO_HWACCEL_DISABLED) {
-+ cfb_imageblit(info, image);
-+ return;
-+ }
-+ if (in_interrupt() || in_atomic()) {
-+ cfb_imageblit(info, image);
-+ return;
-+ }
++ init_rwsem(&tmp->sem);
++ tmp->dev = dev;
+
-+ cfb_imageblit(info, image);
++ return tmp;
+}
+
-+static int psbfb_blank(int blank_mode, struct fb_info *info)
++void psb_gtt_takedown(struct psb_gtt *pg, int free)
+{
-+ int dpms_mode;
-+ struct psbfb_par *par = info->par;
-+ struct drm_connector *output;
-+ struct drm_crtc_helper_funcs *crtc_funcs;
-+
-+ par->dpms_state = blank_mode;
++ struct drm_psb_private *dev_priv = pg->dev->dev_private;
+
-+ switch(blank_mode) {
-+ case FB_BLANK_UNBLANK:
-+ dpms_mode = DRM_MODE_DPMS_ON;
-+ break;
-+ case FB_BLANK_NORMAL:
-+ if (!par->crtc)
-+ return 0;
-+ crtc_funcs = par->crtc->helper_private;
++ if (!pg)
++ return;
+
-+ (*crtc_funcs->dpms)(par->crtc, DRM_MODE_DPMS_STANDBY);
-+ return 0;
-+ case FB_BLANK_HSYNC_SUSPEND:
-+ default:
-+ dpms_mode = DRM_MODE_DPMS_STANDBY;
-+ break;
-+ case FB_BLANK_VSYNC_SUSPEND:
-+ dpms_mode = DRM_MODE_DPMS_SUSPEND;
-+ break;
-+ case FB_BLANK_POWERDOWN:
-+ dpms_mode = DRM_MODE_DPMS_OFF;
-+ break;
++ if (pg->gtt_map) {
++ iounmap(pg->gtt_map);
++ pg->gtt_map = NULL;
+ }
-+
-+ if (!par->crtc)
-+ return 0;
-+
-+ crtc_funcs = par->crtc->helper_private;
-+
-+ list_for_each_entry(output, &par->dev->mode_config.connector_list, head) {
-+ if (output->encoder->crtc == par->crtc)
-+ (*output->funcs->dpms)(output, dpms_mode);
++ if (pg->initialized) {
++ pci_write_config_word(pg->dev->pdev, PSB_GMCH_CTRL,
++ pg->gmch_ctrl);
++ PSB_WVDC32(pg->pge_ctl, PSB_PGETBL_CTL);
++ (void)PSB_RVDC32(PSB_PGETBL_CTL);
+ }
-+
-+ return 0;
++ if (free)
++ drm_free(pg, sizeof(*pg), DRM_MEM_DRIVER);
+}
+
-+
-+static int psbfb_kms_off(struct drm_device *dev, int suspend)
++int psb_gtt_init(struct psb_gtt *pg, int resume)
+{
-+ struct drm_framebuffer *fb = 0;
-+ struct drm_buffer_object *bo = 0;
++ struct drm_device *dev = pg->dev;
+ struct drm_psb_private *dev_priv = dev->dev_private;
++ unsigned gtt_pages;
++ unsigned long stolen_size;
++ unsigned i, num_pages;
++ unsigned pfn_base;
++
+ int ret = 0;
++ uint32_t pte;
+
-+ DRM_DEBUG("psbfb_kms_off_ioctl\n");
++ pci_read_config_word(dev->pdev, PSB_GMCH_CTRL, &pg->gmch_ctrl);
++ pci_write_config_word(dev->pdev, PSB_GMCH_CTRL,
++ pg->gmch_ctrl | _PSB_GMCH_ENABLED);
+
-+ mutex_lock(&dev->mode_config.mutex);
-+ list_for_each_entry(fb, &dev->mode_config.fb_list, head) {
-+ struct fb_info *info = fb->fbdev;
-+ struct psbfb_par *par = info->par;
-+ int save_dpms_state;
-+
-+ if (suspend)
-+ fb_set_suspend(info, 1);
-+ else
-+ info->state &= ~FBINFO_STATE_RUNNING;
-+
-+ info->screen_base = NULL;
-+
-+ bo = fb->bo;
++ pg->pge_ctl = PSB_RVDC32(PSB_PGETBL_CTL);
++ PSB_WVDC32(pg->pge_ctl | _PSB_PGETBL_ENABLED, PSB_PGETBL_CTL);
++ (void)PSB_RVDC32(PSB_PGETBL_CTL);
+
-+ if (!bo)
-+ continue;
++ pg->initialized = 1;
+
-+ drm_bo_kunmap(&fb->kmap);
++ pg->gtt_phys_start = pg->pge_ctl & PAGE_MASK;
++ pg->gatt_start = pci_resource_start(dev->pdev, PSB_GATT_RESOURCE);
++ pg->gtt_start = pci_resource_start(dev->pdev, PSB_GTT_RESOURCE);
++ gtt_pages = pci_resource_len(dev->pdev, PSB_GTT_RESOURCE) >> PAGE_SHIFT;
++ pg->gatt_pages = pci_resource_len(dev->pdev, PSB_GATT_RESOURCE)
++ >> PAGE_SHIFT;
++ pci_read_config_dword(dev->pdev, PSB_BSM, &pg->stolen_base);
++ stolen_size = pg->gtt_phys_start - pg->stolen_base - PAGE_SIZE;
+
-+ /*
-+ * We don't take the 2D lock here as we assume that the
-+ * 2D engine will eventually idle anyway.
-+ */
++ PSB_DEBUG_INIT("GTT phys start: 0x%08x.\n", pg->gtt_phys_start);
++ PSB_DEBUG_INIT("GTT start: 0x%08x.\n", pg->gtt_start);
++ PSB_DEBUG_INIT("GATT start: 0x%08x.\n", pg->gatt_start);
++ PSB_DEBUG_INIT("GTT pages: %u\n", gtt_pages);
++ PSB_DEBUG_INIT("Stolen size: %lu kiB\n", stolen_size / 1024);
+
-+ if (!suspend) {
-+ uint32_t dummy2 = 0;
-+ (void) psb_fence_emit_sequence(dev, PSB_ENGINE_2D, 0,
-+ &dummy2, &dummy2);
-+ psb_2d_lock(dev_priv);
-+ (void)psb_idle_2d(dev);
-+ psb_2d_unlock(dev_priv);
-+ } else
-+ psb_idle_2d(dev);
++ if (resume && (gtt_pages != pg->gtt_pages) &&
++ (stolen_size != pg->stolen_size)) {
++ DRM_ERROR("GTT resume error.\n");
++ ret = -EINVAL;
++ goto out_err;
++ }
+
-+ save_dpms_state = par->dpms_state;
-+ psbfb_blank(FB_BLANK_NORMAL, info);
-+ par->dpms_state = save_dpms_state;
++ pg->gtt_pages = gtt_pages;
++ pg->stolen_size = stolen_size;
++ pg->gtt_map =
++ ioremap_nocache(pg->gtt_phys_start, gtt_pages << PAGE_SHIFT);
++ if (!pg->gtt_map) {
++ DRM_ERROR("Failure to map gtt.\n");
++ ret = -ENOMEM;
++ goto out_err;
++ }
+
-+ ret = psbfb_move_fb_bo(info, bo, DRM_BO_FLAG_MEM_LOCAL);
++ /*
++ * insert stolen pages.
++ */
+
-+ if (ret)
-+ goto out_err;
++ pfn_base = pg->stolen_base >> PAGE_SHIFT;
++ num_pages = stolen_size >> PAGE_SHIFT;
++ PSB_DEBUG_INIT("Set up %d stolen pages starting at 0x%08x\n",
++ num_pages, pfn_base);
++ for (i = 0; i < num_pages; ++i) {
++ pte = psb_gtt_mask_pte(pfn_base + i, 0);
++ iowrite32(pte, pg->gtt_map + i);
+ }
-+ out_err:
-+ mutex_unlock(&dev->mode_config.mutex);
+
-+ return ret;
-+}
++ /*
++ * Init rest of gtt.
++ */
+
-+int psbfb_kms_off_ioctl(struct drm_device *dev, void *data,
-+ struct drm_file *file_priv)
-+{
-+ int ret;
++ pfn_base = page_to_pfn(dev_priv->scratch_page);
++ pte = psb_gtt_mask_pte(pfn_base, 0);
++ PSB_DEBUG_INIT("Initializing the rest of a total "
++ "of %d gtt pages.\n", pg->gatt_pages);
+
-+ acquire_console_sem();
-+ ret = psbfb_kms_off(dev, 0);
-+ release_console_sem();
++ for (; i < pg->gatt_pages; ++i)
++ iowrite32(pte, pg->gtt_map + i);
++ (void)ioread32(pg->gtt_map + i - 1);
++
++ return 0;
+
++ out_err:
++ psb_gtt_takedown(pg, 0);
+ return ret;
+}
+
-+static int psbfb_kms_on(struct drm_device *dev, int resume)
++int psb_gtt_insert_pages(struct psb_gtt *pg, struct page **pages,
++ unsigned offset_pages, unsigned num_pages,
++ unsigned desired_tile_stride, unsigned hw_tile_stride,
++ int type)
+{
-+ struct drm_framebuffer *fb = 0;
-+ struct drm_buffer_object *bo = 0;
-+ struct drm_psb_private *dev_priv = dev->dev_private;
-+ int ret = 0;
-+ int dummy;
-+
-+ DRM_DEBUG("psbfb_kms_on_ioctl\n");
-+
-+ if (!resume) {
-+ uint32_t dummy2 = 0;
-+ (void) psb_fence_emit_sequence(dev, PSB_ENGINE_2D, 0,
-+ &dummy2, &dummy2);
-+ psb_2d_lock(dev_priv);
-+ (void)psb_idle_2d(dev);
-+ psb_2d_unlock(dev_priv);
-+ } else
-+ psb_idle_2d(dev);
-+
-+ mutex_lock(&dev->mode_config.mutex);
-+ list_for_each_entry(fb, &dev->mode_config.fb_list, head) {
-+ struct fb_info *info = fb->fbdev;
-+ struct psbfb_par *par = info->par;
-+
-+ bo = fb->bo;
-+ if (!bo)
-+ continue;
-+
-+ ret = psbfb_move_fb_bo(info, bo,
-+ DRM_BO_FLAG_MEM_TT |
-+ DRM_BO_FLAG_MEM_VRAM |
-+ DRM_BO_FLAG_NO_EVICT);
-+ if (ret)
-+ goto out_err;
-+
-+ ret = drm_bo_kmap(bo, 0, bo->num_pages, &fb->kmap);
-+ if (ret)
-+ goto out_err;
-+
-+ info->screen_base = drm_bmo_virtual(&fb->kmap, &dummy);
-+ fb->offset = bo->offset - dev_priv->pg->gatt_start;
-+
-+ if (ret)
-+ goto out_err;
++ unsigned rows = 1;
++ unsigned add;
++ unsigned row_add;
++ unsigned i;
++ unsigned j;
++ uint32_t *cur_page = NULL;
++ uint32_t pte;
+
-+ if (resume)
-+ fb_set_suspend(info, 0);
-+ else
-+ info->state |= FBINFO_STATE_RUNNING;
++ if (hw_tile_stride)
++ rows = num_pages / desired_tile_stride;
++ else
++ desired_tile_stride = num_pages;
+
-+ /*
-+ * Re-run modesetting here, since the VDS scanout offset may
-+ * have changed.
-+ */
++ add = desired_tile_stride;
++ row_add = hw_tile_stride;
+
-+ if (par->crtc->enabled) {
-+ psbfb_set_par(info);
-+ psbfb_blank(par->dpms_state, info);
++ down_read(&pg->sem);
++ for (i = 0; i < rows; ++i) {
++ cur_page = pg->gtt_map + offset_pages;
++ for (j = 0; j < desired_tile_stride; ++j) {
++ pte = psb_gtt_mask_pte(page_to_pfn(*pages++), type);
++ iowrite32(pte, cur_page++);
+ }
++ offset_pages += add;
+ }
-+ out_err:
-+ mutex_unlock(&dev->mode_config.mutex);
++ (void)ioread32(cur_page - 1);
++ up_read(&pg->sem);
+
-+ return ret;
++ return 0;
+}
+
-+int psbfb_kms_on_ioctl(struct drm_device *dev, void *data,
-+ struct drm_file *file_priv)
++int psb_gtt_remove_pages(struct psb_gtt *pg, unsigned offset_pages,
++ unsigned num_pages, unsigned desired_tile_stride,
++ unsigned hw_tile_stride)
+{
-+ int ret;
++ struct drm_psb_private *dev_priv = pg->dev->dev_private;
++ unsigned rows = 1;
++ unsigned add;
++ unsigned row_add;
++ unsigned i;
++ unsigned j;
++ uint32_t *cur_page = NULL;
++ unsigned pfn_base = page_to_pfn(dev_priv->scratch_page);
++ uint32_t pte = psb_gtt_mask_pte(pfn_base, 0);
+
-+ acquire_console_sem();
-+ ret = psbfb_kms_on(dev, 0);
-+ release_console_sem();
-+#ifdef SII_1392_WA
-+ if((SII_1392 != 1) || (drm_psb_no_fb==0))
-+ drm_helper_disable_unused_functions(dev);
-+#else
-+ drm_helper_disable_unused_functions(dev);
-+#endif
-+ return ret;
-+}
++ if (hw_tile_stride)
++ rows = num_pages / desired_tile_stride;
++ else
++ desired_tile_stride = num_pages;
+
-+void psbfb_suspend(struct drm_device *dev)
-+{
-+ acquire_console_sem();
-+ psbfb_kms_off(dev, 1);
-+ release_console_sem();
-+}
++ add = desired_tile_stride;
++ row_add = hw_tile_stride;
+
-+void psbfb_resume(struct drm_device *dev)
-+{
-+ acquire_console_sem();
-+ psbfb_kms_on(dev, 1);
-+ release_console_sem();
-+#ifdef SII_1392_WA
-+ if((SII_1392 != 1) || (drm_psb_no_fb==0))
-+ drm_helper_disable_unused_functions(dev);
-+#else
-+ drm_helper_disable_unused_functions(dev);
-+#endif
-+}
++ down_read(&pg->sem);
++ for (i = 0; i < rows; ++i) {
++ cur_page = pg->gtt_map + offset_pages;
++ for (j = 0; j < desired_tile_stride; ++j) {
++ iowrite32(pte, cur_page++);
++ }
++ offset_pages += add;
++ }
++ (void)ioread32(cur_page - 1);
++ up_read(&pg->sem);
+
++ return 0;
++}
+Index: linux-2.6.28/drivers/gpu/drm/psb/psb_i2c.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.28/drivers/gpu/drm/psb/psb_i2c.c 2009-02-12 10:12:29.000000000 +0000
+@@ -0,0 +1,179 @@
+/*
-+ * FIXME: Before kernel inclusion, migrate nopfn to fault.
-+ * Also, these should be the default vm ops for buffer object type fbs.
-+ */
++ * Copyright © 2006-2007 Intel Corporation
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the next
++ * paragraph) shall be included in all copies or substantial portions of the
++ * Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
++ * DEALINGS IN THE SOFTWARE.
++ *
++ * Authors:
++ * Eric Anholt <eric@anholt.net>
++ */
++/*
++ * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
++ * Jesse Barnes <jesse.barnes@intel.com>
++ */
+
-+extern unsigned long drm_bo_vm_fault(struct vm_area_struct *vma,
-+ struct vm_fault *vmf);
++#include <linux/i2c.h>
++#include <linux/i2c-id.h>
++#include <linux/i2c-algo-bit.h>
++#include "drmP.h"
++#include "drm.h"
++#include "../i915/intel_drv.h"
++#include "psb_drv.h"
+
+/*
-+ * This wrapper is a bit ugly and is here because we need access to a mutex
-+ * that we can lock both around nopfn and around unmap_mapping_range + move.
-+ * Normally, this would've been done using the bo mutex, but unfortunately
-+ * we cannot lock it around drm_bo_do_validate(), since that would imply
-+ * recursive locking.
++ * Intel GPIO access functions
+ */
+
-+static int psbfb_fault(struct vm_area_struct *vma,
-+ struct vm_fault *vmf)
-+{
-+ struct psbfb_vm_info *vi = (struct psbfb_vm_info *)vma->vm_private_data;
-+ struct vm_area_struct tmp_vma;
-+ int ret;
-+
-+ mutex_lock(&vi->vm_mutex);
-+ tmp_vma = *vma;
-+ tmp_vma.vm_private_data = vi->bo;
-+ ret = drm_bo_vm_fault(&tmp_vma, vmf);
-+ mutex_unlock(&vi->vm_mutex);
-+ return ret;
-+}
++#define I2C_RISEFALL_TIME 20
+
-+static void psbfb_vm_open(struct vm_area_struct *vma)
++static int get_clock(void *data)
+{
-+ struct psbfb_vm_info *vi = (struct psbfb_vm_info *)vma->vm_private_data;
++ struct intel_i2c_chan *chan = data;
++ struct drm_psb_private *dev_priv = chan->drm_dev->dev_private;
++ uint32_t val;
+
-+ atomic_inc(&vi->refcount);
++ val = PSB_RVDC32(chan->reg);
++ return ((val & GPIO_CLOCK_VAL_IN) != 0);
+}
+
-+static void psbfb_vm_close(struct vm_area_struct *vma)
++static int get_data(void *data)
+{
-+ psbfb_vm_info_deref((struct psbfb_vm_info **)&vma->vm_private_data);
-+}
++ struct intel_i2c_chan *chan = data;
++ struct drm_psb_private *dev_priv = chan->drm_dev->dev_private;
++ uint32_t val;
+
-+static struct vm_operations_struct psbfb_vm_ops = {
-+ .fault = psbfb_fault,
-+ .open = psbfb_vm_open,
-+ .close = psbfb_vm_close,
-+};
++ val = PSB_RVDC32(chan->reg);
++ return ((val & GPIO_DATA_VAL_IN) != 0);
++}
+
-+static int psbfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
++static void set_clock(void *data, int state_high)
+{
-+ struct psbfb_par *par = info->par;
-+ struct drm_framebuffer *fb = par->crtc->fb;
-+ struct drm_buffer_object *bo = fb->bo;
-+ unsigned long size = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
-+ unsigned long offset = vma->vm_pgoff;
-+
-+ if (vma->vm_pgoff != 0)
-+ return -EINVAL;
-+ if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
-+ return -EINVAL;
-+ if (offset + size > bo->num_pages)
-+ return -EINVAL;
-+
-+ mutex_lock(&par->vi->vm_mutex);
-+ if (!par->vi->f_mapping)
-+ par->vi->f_mapping = vma->vm_file->f_mapping;
-+ mutex_unlock(&par->vi->vm_mutex);
-+
-+ vma->vm_private_data = psbfb_vm_info_ref(par->vi);
++ struct intel_i2c_chan *chan = data;
++ struct drm_psb_private *dev_priv = chan->drm_dev->dev_private;
++ uint32_t reserved = 0, clock_bits;
+
-+ vma->vm_ops = &psbfb_vm_ops;
-+ vma->vm_flags |= VM_PFNMAP;
++ /* On most chips, these bits must be preserved in software. */
++ reserved = PSB_RVDC32(chan->reg) & (GPIO_DATA_PULLUP_DISABLE |
++ GPIO_CLOCK_PULLUP_DISABLE);
+
-+ return 0;
++ if (state_high)
++ clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
++ else
++ clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
++ GPIO_CLOCK_VAL_MASK;
++ PSB_WVDC32(reserved | clock_bits, chan->reg);
++ udelay(I2C_RISEFALL_TIME); /* wait for the line to change state */
+}
+
-+int psbfb_sync(struct fb_info *info)
++static void set_data(void *data, int state_high)
+{
-+ struct psbfb_par *par = info->par;
-+ struct drm_psb_private *dev_priv = par->dev->dev_private;
-+
-+ psb_2d_lock(dev_priv);
-+ psb_idle_2d(par->dev);
-+ psb_2d_unlock(dev_priv);
++ struct intel_i2c_chan *chan = data;
++ struct drm_psb_private *dev_priv = chan->drm_dev->dev_private;
++ uint32_t reserved = 0, data_bits;
+
-+ return 0;
-+}
++ /* On most chips, these bits must be preserved in software. */
++ reserved = PSB_RVDC32(chan->reg) & (GPIO_DATA_PULLUP_DISABLE |
++ GPIO_CLOCK_PULLUP_DISABLE);
+
-+static struct fb_ops psbfb_ops = {
-+ .owner = THIS_MODULE,
-+ .fb_check_var = psbfb_check_var,
-+ .fb_set_par = psbfb_set_par,
-+ .fb_setcolreg = psbfb_setcolreg,
-+ .fb_fillrect = psbfb_fillrect,
-+ .fb_copyarea = psbfb_copyarea,
-+ .fb_imageblit = psbfb_imageblit,
-+ .fb_mmap = psbfb_mmap,
-+ .fb_sync = psbfb_sync,
-+ .fb_blank = psbfb_blank,
-+};
++ if (state_high)
++ data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
++ else
++ data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
++ GPIO_DATA_VAL_MASK;
+
-+static void psb_user_framebuffer_destroy(struct drm_framebuffer *fb)
-+{
-+ drm_framebuffer_cleanup(fb);
-+ kfree(fb);
++ PSB_WVDC32(data_bits, chan->reg);
++ udelay(I2C_RISEFALL_TIME); /* wait for the line to change state */
+}
+
-+static const struct drm_framebuffer_funcs psb_fb_funcs = {
-+ .destroy = psb_user_framebuffer_destroy,
-+};
-+
-+int psbfb_probe(struct drm_device *dev, struct drm_crtc *crtc)
++/**
++ * intel_i2c_create - instantiate an Intel i2c bus using the specified GPIO reg
++ * @dev: DRM device
++ * @output: driver specific output device
++ * @reg: GPIO reg to use
++ * @name: name for this bus
++ *
++ * Creates and registers a new i2c bus with the Linux i2c layer, for use
++ * in output probing and control (e.g. DDC or SDVO control functions).
++ *
++ * Possible values for @reg include:
++ * %GPIOA
++ * %GPIOB
++ * %GPIOC
++ * %GPIOD
++ * %GPIOE
++ * %GPIOF
++ * %GPIOG
++ * %GPIOH
++ * see PRM for details on how these different busses are used.
++ */
++struct intel_i2c_chan *intel_i2c_create(struct drm_device *dev,
++ const uint32_t reg, const char *name)
+{
-+ struct fb_info *info;
-+ struct psbfb_par *par;
-+ struct device *device = &dev->pdev->dev;
-+ struct drm_framebuffer *fb;
-+ struct drm_display_mode *mode = crtc->desired_mode;
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
-+ struct drm_buffer_object *fbo = NULL;
-+ int ret;
-+ int is_iomem;
++ struct intel_i2c_chan *chan;
+
-+ if (drm_psb_no_fb) {
-+ /* need to do this as the DRM will disable the output */
-+ crtc->enabled = 1;
-+ return 0;
-+ }
++ chan = kzalloc(sizeof(struct intel_i2c_chan), GFP_KERNEL);
++ if (!chan)
++ goto out_free;
+
-+ fb = kzalloc(sizeof(struct drm_framebuffer), GFP_KERNEL);
-+ if (!fb)
-+ return -ENOMEM;
++ chan->drm_dev = dev;
++ chan->reg = reg;
++ snprintf(chan->adapter.name, I2C_NAME_SIZE, "intel drm %s", name);
++ chan->adapter.owner = THIS_MODULE;
++ chan->adapter.id = I2C_HW_B_INTELFB;
++ chan->adapter.algo_data = &chan->algo;
++ chan->adapter.dev.parent = &dev->pdev->dev;
++ chan->algo.setsda = set_data;
++ chan->algo.setscl = set_clock;
++ chan->algo.getsda = get_data;
++ chan->algo.getscl = get_clock;
++ chan->algo.udelay = 20;
++ chan->algo.timeout = usecs_to_jiffies(2200);
++ chan->algo.data = chan;
+
++ i2c_set_adapdata(&chan->adapter, chan);
+
-+ ret = drm_framebuffer_init(dev, fb, &psb_fb_funcs);
-+ if (!fb) {
-+ DRM_ERROR("failed to allocate fb.\n");
-+ return -ENOMEM;
-+ }
-+ crtc->fb = fb;
++ if (i2c_bit_add_bus(&chan->adapter))
++ goto out_free;
+
-+ fb->width = mode->hdisplay;
-+ fb->height = mode->vdisplay;
++ /* JJJ: raise SCL and SDA? */
++ set_data(chan, 1);
++ set_clock(chan, 1);
++ udelay(20);
+
-+ fb->bits_per_pixel = 32;
-+ fb->depth = 24;
-+ fb->pitch =
-+ ((fb->width * ((fb->bits_per_pixel + 1) / 8)) + 0x3f) & ~0x3f;
++ return chan;
+
-+ info = framebuffer_alloc(sizeof(struct psbfb_par), device);
-+ if (!info) {
-+ kfree(fb);
-+ return -ENOMEM;
-+ }
++ out_free:
++ kfree(chan);
++ return NULL;
++}
+
-+ ret = drm_buffer_object_create(dev,
-+ fb->pitch * fb->height,
-+ drm_bo_type_kernel,
-+ DRM_BO_FLAG_READ |
-+ DRM_BO_FLAG_WRITE |
-+ DRM_BO_FLAG_MEM_TT |
-+ DRM_BO_FLAG_MEM_VRAM |
-+ DRM_BO_FLAG_NO_EVICT,
-+ DRM_BO_HINT_DONT_FENCE, 0, 0, &fbo);
-+ if (ret || !fbo) {
-+ DRM_ERROR("failed to allocate framebuffer\n");
-+ goto out_err0;
-+ }
-+
-+ fb->offset = fbo->offset - dev_priv->pg->gatt_start;
-+ fb->bo = fbo;
-+ DRM_DEBUG("allocated %dx%d fb: 0x%08lx, bo %p\n", fb->width,
-+ fb->height, fb->offset, fbo);
-+
-+ fb->fbdev = info;
-+
-+ par = info->par;
-+
-+ par->dev = dev;
-+ par->crtc = crtc;
-+ par->vi = psbfb_vm_info_create();
-+ if (!par->vi)
-+ goto out_err1;
-+
-+ mutex_lock(&dev->struct_mutex);
-+ par->vi->bo = fbo;
-+ atomic_inc(&fbo->usage);
-+ mutex_unlock(&dev->struct_mutex);
-+
-+ par->vi->f_mapping = NULL;
-+ info->fbops = &psbfb_ops;
-+
-+ strcpy(info->fix.id, "psbfb");
-+ info->fix.type = FB_TYPE_PACKED_PIXELS;
-+ info->fix.visual = FB_VISUAL_DIRECTCOLOR;
-+ info->fix.type_aux = 0;
-+ info->fix.xpanstep = 1;
-+ info->fix.ypanstep = 1;
-+ info->fix.ywrapstep = 0;
-+ info->fix.accel = FB_ACCEL_NONE; /* ??? */
-+ info->fix.type_aux = 0;
-+ info->fix.mmio_start = 0;
-+ info->fix.mmio_len = 0;
-+ info->fix.line_length = fb->pitch;
-+ info->fix.smem_start = dev->mode_config.fb_base + fb->offset;
-+ info->fix.smem_len = info->fix.line_length * fb->height;
-+
-+ info->flags = FBINFO_DEFAULT |
-+ FBINFO_PARTIAL_PAN_OK /*| FBINFO_MISC_ALWAYS_SETPAR */ ;
-+
-+ ret = drm_bo_kmap(fb->bo, 0, fb->bo->num_pages, &fb->kmap);
-+ if (ret) {
-+ DRM_ERROR("error mapping fb: %d\n", ret);
-+ goto out_err2;
-+ }
-+
-+ info->screen_base = drm_bmo_virtual(&fb->kmap, &is_iomem);
-+ memset(info->screen_base, 0x00, fb->pitch*fb->height);
-+ info->screen_size = info->fix.smem_len; /* FIXME */
-+ info->pseudo_palette = fb->pseudo_palette;
-+ info->var.xres_virtual = fb->width;
-+ info->var.yres_virtual = fb->height;
-+ info->var.bits_per_pixel = fb->bits_per_pixel;
-+ info->var.xoffset = 0;
-+ info->var.yoffset = 0;
-+ info->var.activate = FB_ACTIVATE_NOW;
-+ info->var.height = -1;
-+ info->var.width = -1;
-+ info->var.vmode = FB_VMODE_NONINTERLACED;
-+
-+ info->var.xres = mode->hdisplay;
-+ info->var.right_margin = mode->hsync_start - mode->hdisplay;
-+ info->var.hsync_len = mode->hsync_end - mode->hsync_start;
-+ info->var.left_margin = mode->htotal - mode->hsync_end;
-+ info->var.yres = mode->vdisplay;
-+ info->var.lower_margin = mode->vsync_start - mode->vdisplay;
-+ info->var.vsync_len = mode->vsync_end - mode->vsync_start;
-+ info->var.upper_margin = mode->vtotal - mode->vsync_end;
-+ info->var.pixclock = 10000000 / mode->htotal * 1000 /
-+ mode->vtotal * 100;
-+ /* avoid overflow */
-+ info->var.pixclock = info->var.pixclock * 1000 / mode->vrefresh;
-+
-+ info->pixmap.size = 64 * 1024;
-+ info->pixmap.buf_align = 8;
-+ info->pixmap.access_align = 32;
-+ info->pixmap.flags = FB_PIXMAP_SYSTEM;
-+ info->pixmap.scan_align = 1;
-+
-+ DRM_DEBUG("fb depth is %d\n", fb->depth);
-+ DRM_DEBUG(" pitch is %d\n", fb->pitch);
-+ switch (fb->depth) {
-+ case 8:
-+ info->var.red.offset = 0;
-+ info->var.green.offset = 0;
-+ info->var.blue.offset = 0;
-+ info->var.red.length = 8; /* 8bit DAC */
-+ info->var.green.length = 8;
-+ info->var.blue.length = 8;
-+ info->var.transp.offset = 0;
-+ info->var.transp.length = 0;
-+ break;
-+ case 15:
-+ info->var.red.offset = 10;
-+ info->var.green.offset = 5;
-+ info->var.blue.offset = 0;
-+ info->var.red.length = info->var.green.length =
-+ info->var.blue.length = 5;
-+ info->var.transp.offset = 15;
-+ info->var.transp.length = 1;
-+ break;
-+ case 16:
-+ info->var.red.offset = 11;
-+ info->var.green.offset = 5;
-+ info->var.blue.offset = 0;
-+ info->var.red.length = 5;
-+ info->var.green.length = 6;
-+ info->var.blue.length = 5;
-+ info->var.transp.offset = 0;
-+ break;
-+ case 24:
-+ info->var.red.offset = 16;
-+ info->var.green.offset = 8;
-+ info->var.blue.offset = 0;
-+ info->var.red.length = info->var.green.length =
-+ info->var.blue.length = 8;
-+ info->var.transp.offset = 0;
-+ info->var.transp.length = 0;
-+ break;
-+ case 32:
-+ info->var.red.offset = 16;
-+ info->var.green.offset = 8;
-+ info->var.blue.offset = 0;
-+ info->var.red.length = info->var.green.length =
-+ info->var.blue.length = 8;
-+ info->var.transp.offset = 24;
-+ info->var.transp.length = 8;
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ if (register_framebuffer(info) < 0)
-+ goto out_err3;
-+
-+ if (psbfb_check_var(&info->var, info) < 0)
-+ goto out_err4;
-+
-+ psbfb_set_par(info);
-+
-+ DRM_INFO("fb%d: %s frame buffer device\n", info->node, info->fix.id);
-+
-+ return 0;
-+ out_err4:
-+ unregister_framebuffer(info);
-+ out_err3:
-+ drm_bo_kunmap(&fb->kmap);
-+ out_err2:
-+ psbfb_vm_info_deref(&par->vi);
-+ out_err1:
-+ drm_bo_usage_deref_unlocked(&fb->bo);
-+ out_err0:
-+ drm_framebuffer_cleanup(fb);
-+ framebuffer_release(info);
-+ crtc->fb = NULL;
-+ return -EINVAL;
-+}
-+
-+EXPORT_SYMBOL(psbfb_probe);
-+
-+int psbfb_remove(struct drm_device *dev, struct drm_crtc *crtc)
++/**
++ * intel_i2c_destroy - unregister and free i2c bus resources
++ * @output: channel to free
++ *
++ * Unregister the adapter from the i2c layer, then free the structure.
++ */
++void intel_i2c_destroy(struct intel_i2c_chan *chan)
+{
-+ struct drm_framebuffer *fb;
-+ struct fb_info *info;
-+ struct psbfb_par *par;
-+
-+ if (drm_psb_no_fb)
-+ return 0;
-+
-+ fb = crtc->fb;
-+ info = fb->fbdev;
++ if (!chan)
++ return;
+
-+ if (info) {
-+ unregister_framebuffer(info);
-+ drm_bo_kunmap(&fb->kmap);
-+ par = info->par;
-+ if (par)
-+ psbfb_vm_info_deref(&par->vi);
-+ drm_bo_usage_deref_unlocked(&fb->bo);
-+ drm_framebuffer_cleanup(fb);
-+ framebuffer_release(info);
-+ }
-+ return 0;
++ i2c_del_adapter(&chan->adapter);
++ kfree(chan);
+}
-+
-+EXPORT_SYMBOL(psbfb_remove);
-+
-Index: linux-2.6.28/drivers/gpu/drm/psb/psb_fence.c
+Index: linux-2.6.28/drivers/gpu/drm/psb/psb_irq.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/psb/psb_fence.c 2009-02-12 09:14:41.000000000 +0000
-@@ -0,0 +1,285 @@
++++ linux-2.6.28/drivers/gpu/drm/psb/psb_irq.c 2009-02-12 09:14:41.000000000 +0000
+@@ -0,0 +1,382 @@
+/**************************************************************************
+ * Copyright (c) 2007, Intel Corporation.
+ * All Rights Reserved.
+ *
+ **************************************************************************/
+/*
-+ * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
+ */
+
+#include "drmP.h"
+#include "psb_drv.h"
++#include "psb_reg.h"
++#include "psb_msvdx.h"
+
-+static void psb_poll_ta(struct drm_device *dev, uint32_t waiting_types)
++/*
++ * Video display controller interrupt.
++ */
++
++static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat)
+{
+ struct drm_psb_private *dev_priv =
+ (struct drm_psb_private *)dev->dev_private;
-+ struct drm_fence_driver *driver = dev->driver->fence_driver;
-+ uint32_t cur_flag = 1;
-+ uint32_t flags = 0;
-+ uint32_t sequence = 0;
-+ uint32_t remaining = 0xFFFFFFFF;
-+ uint32_t diff;
++ uint32_t pipe_stats;
++ int wake = 0;
+
-+ struct psb_scheduler *scheduler;
-+ struct psb_scheduler_seq *seq;
-+ struct drm_fence_class_manager *fc =
-+ &dev->fm.fence_class[PSB_ENGINE_TA];
++ if (!drm_psb_disable_vsync && (vdc_stat & _PSB_VSYNC_PIPEA_FLAG)) {
++ pipe_stats = PSB_RVDC32(PSB_PIPEASTAT);
++ atomic_inc(&dev->vbl_received);
++ wake = 1;
++ PSB_WVDC32(pipe_stats | _PSB_VBLANK_INTERRUPT_ENABLE |
++ _PSB_VBLANK_CLEAR, PSB_PIPEASTAT);
++ }
+
-+ if (unlikely(!dev_priv))
-+ return;
++ if (!drm_psb_disable_vsync && (vdc_stat & _PSB_VSYNC_PIPEB_FLAG)) {
++ pipe_stats = PSB_RVDC32(PSB_PIPEBSTAT);
++ atomic_inc(&dev->vbl_received2);
++ wake = 1;
++ PSB_WVDC32(pipe_stats | _PSB_VBLANK_INTERRUPT_ENABLE |
++ _PSB_VBLANK_CLEAR, PSB_PIPEBSTAT);
++ }
+
-+ scheduler = &dev_priv->scheduler;
-+ seq = scheduler->seq;
++ PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R);
++ (void)PSB_RVDC32(PSB_INT_IDENTITY_R);
++ DRM_READMEMORYBARRIER();
+
-+ while (likely(waiting_types & remaining)) {
-+ if (!(waiting_types & cur_flag))
-+ goto skip;
-+ if (seq->reported)
-+ goto skip;
-+ if (flags == 0)
-+ sequence = seq->sequence;
-+ else if (sequence != seq->sequence) {
-+ drm_fence_handler(dev, PSB_ENGINE_TA,
-+ sequence, flags, 0);
-+ sequence = seq->sequence;
-+ flags = 0;
-+ }
-+ flags |= cur_flag;
++ if (wake) {
++ DRM_WAKEUP(&dev->vbl_queue);
++ drm_vbl_send_signals(dev);
++ }
++}
+
-+ /*
-+ * Sequence may not have ended up on the ring yet.
-+ * In that case, report it but don't mark it as
-+ * reported. A subsequent poll will report it again.
-+ */
++/*
++ * SGX interrupt source 1.
++ */
+
-+ diff = (fc->latest_queued_sequence - sequence) &
-+ driver->sequence_mask;
-+ if (diff < driver->wrap_diff)
-+ seq->reported = 1;
++static void psb_sgx_interrupt(struct drm_device *dev, uint32_t sgx_stat,
++ uint32_t sgx_stat2)
++{
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
+
-+ skip:
-+ cur_flag <<= 1;
-+ remaining <<= 1;
-+ seq++;
++ if (sgx_stat & _PSB_CE_TWOD_COMPLETE) {
++ DRM_WAKEUP(&dev_priv->event_2d_queue);
++ psb_fence_handler(dev, 0);
+ }
+
-+ if (flags) {
-+ drm_fence_handler(dev, PSB_ENGINE_TA, sequence, flags, 0);
-+ }
++ if (unlikely(sgx_stat2 & _PSB_CE2_BIF_REQUESTER_FAULT))
++ psb_print_pagefault(dev_priv);
++
++ psb_scheduler_handler(dev_priv, sgx_stat);
+}
+
-+static void psb_poll_other(struct drm_device *dev, uint32_t fence_class,
-+ uint32_t waiting_types)
++/*
++ * MSVDX interrupt.
++ */
++static void psb_msvdx_interrupt(struct drm_device *dev, uint32_t msvdx_stat)
+{
+ struct drm_psb_private *dev_priv =
+ (struct drm_psb_private *)dev->dev_private;
-+ struct drm_fence_manager *fm = &dev->fm;
-+ struct drm_fence_class_manager *fc = &fm->fence_class[fence_class];
-+ uint32_t sequence;
+
-+ if (unlikely(!dev_priv))
-+ return;
++ if (msvdx_stat & MSVDX_INTERRUPT_STATUS_CR_MMU_FAULT_IRQ_MASK) {
++ /*Ideally we should we should never get to this */
++ PSB_DEBUG_GENERAL
++ ("******MSVDX: msvdx_stat: 0x%x fence2_irq_on=%d ***** (MMU FAULT)\n",
++ msvdx_stat, dev_priv->fence2_irq_on);
+
-+ if (waiting_types) {
-+ if (fence_class == PSB_ENGINE_VIDEO)
-+ sequence = dev_priv->msvdx_current_sequence;
-+ else
-+ sequence = dev_priv->comm[fence_class << 4];
++ /* Pause MMU */
++ PSB_WMSVDX32(MSVDX_MMU_CONTROL0_CR_MMU_PAUSE_MASK,
++ MSVDX_MMU_CONTROL0);
++ DRM_WRITEMEMORYBARRIER();
+
-+ drm_fence_handler(dev, fence_class, sequence,
-+ DRM_FENCE_TYPE_EXE, 0);
++ /* Clear this interupt bit only */
++ PSB_WMSVDX32(MSVDX_INTERRUPT_STATUS_CR_MMU_FAULT_IRQ_MASK,
++ MSVDX_INTERRUPT_CLEAR);
++ PSB_RMSVDX32(MSVDX_INTERRUPT_CLEAR);
++ DRM_READMEMORYBARRIER();
+
-+ switch (fence_class) {
-+ case PSB_ENGINE_2D:
-+ if (dev_priv->fence0_irq_on && !fc->waiting_types) {
-+ psb_2D_irq_off(dev_priv);
-+ dev_priv->fence0_irq_on = 0;
-+ } else if (!dev_priv->fence0_irq_on
-+ && fc->waiting_types) {
-+ psb_2D_irq_on(dev_priv);
-+ dev_priv->fence0_irq_on = 1;
-+ }
-+ break;
-+#if 0
-+ /*
-+ * FIXME: MSVDX irq switching
-+ */
++ dev_priv->msvdx_needs_reset = 1;
++ } else if (msvdx_stat & MSVDX_INTERRUPT_STATUS_CR_MTX_IRQ_MASK) {
++ PSB_DEBUG_GENERAL
++ ("******MSVDX: msvdx_stat: 0x%x fence2_irq_on=%d ***** (MTX)\n",
++ msvdx_stat, dev_priv->fence2_irq_on);
+
-+ case PSB_ENGINE_VIDEO:
-+ if (dev_priv->fence2_irq_on && !fc->waiting_types) {
-+ psb_msvdx_irq_off(dev_priv);
-+ dev_priv->fence2_irq_on = 0;
-+ } else if (!dev_priv->fence2_irq_on
-+ && fc->pending_exe_flush) {
-+ psb_msvdx_irq_on(dev_priv);
-+ dev_priv->fence2_irq_on = 1;
-+ }
-+ break;
-+#endif
-+ default:
-+ return;
-+ }
-+ }
-+}
++ /* Clear all interupt bits */
++ PSB_WMSVDX32(0xffff, MSVDX_INTERRUPT_CLEAR);
++ PSB_RMSVDX32(MSVDX_INTERRUPT_CLEAR);
++ DRM_READMEMORYBARRIER();
+
-+static void psb_fence_poll(struct drm_device *dev,
-+ uint32_t fence_class, uint32_t waiting_types)
-+{
-+ switch (fence_class) {
-+ case PSB_ENGINE_TA:
-+ psb_poll_ta(dev, waiting_types);
-+ break;
-+ default:
-+ psb_poll_other(dev, fence_class, waiting_types);
-+ break;
++ psb_msvdx_mtx_interrupt(dev);
+ }
+}
+
-+void psb_fence_error(struct drm_device *dev,
-+ uint32_t fence_class,
-+ uint32_t sequence, uint32_t type, int error)
-+{
-+ struct drm_fence_manager *fm = &dev->fm;
-+ unsigned long irq_flags;
-+
-+ BUG_ON(fence_class >= PSB_NUM_ENGINES);
-+ write_lock_irqsave(&fm->lock, irq_flags);
-+ drm_fence_handler(dev, fence_class, sequence, type, error);
-+ write_unlock_irqrestore(&fm->lock, irq_flags);
-+}
-+
-+int psb_fence_emit_sequence(struct drm_device *dev, uint32_t fence_class,
-+ uint32_t flags, uint32_t * sequence,
-+ uint32_t * native_type)
++irqreturn_t psb_irq_handler(DRM_IRQ_ARGS)
+{
++ struct drm_device *dev = (struct drm_device *)arg;
+ struct drm_psb_private *dev_priv =
+ (struct drm_psb_private *)dev->dev_private;
-+ uint32_t seq = 0;
-+ int ret;
+
-+ if (!dev_priv)
-+ return -EINVAL;
++ uint32_t vdc_stat;
++ uint32_t sgx_stat;
++ uint32_t sgx_stat2;
++ uint32_t msvdx_stat;
++ int handled = 0;
+
-+ if (fence_class >= PSB_NUM_ENGINES)
-+ return -EINVAL;
++ spin_lock(&dev_priv->irqmask_lock);
+
-+ switch (fence_class) {
-+ case PSB_ENGINE_2D:
-+ spin_lock(&dev_priv->sequence_lock);
-+ seq = ++dev_priv->sequence[fence_class];
-+ spin_unlock(&dev_priv->sequence_lock);
-+ ret = psb_blit_sequence(dev_priv, seq);
-+ if (ret)
-+ return ret;
-+ break;
-+ case PSB_ENGINE_VIDEO:
-+ spin_lock(&dev_priv->sequence_lock);
-+ seq = ++dev_priv->sequence[fence_class];
-+ spin_unlock(&dev_priv->sequence_lock);
-+ break;
-+ default:
-+ spin_lock(&dev_priv->sequence_lock);
-+ seq = dev_priv->sequence[fence_class];
-+ spin_unlock(&dev_priv->sequence_lock);
-+ }
++ vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R);
++ sgx_stat = PSB_RSGX32(PSB_CR_EVENT_STATUS);
++ sgx_stat2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
++ msvdx_stat = PSB_RMSVDX32(MSVDX_INTERRUPT_STATUS);
+
-+ *sequence = seq;
-+ *native_type = DRM_FENCE_TYPE_EXE;
++ sgx_stat2 &= dev_priv->sgx2_irq_mask;
++ sgx_stat &= dev_priv->sgx_irq_mask;
++ PSB_WSGX32(sgx_stat2, PSB_CR_EVENT_HOST_CLEAR2);
++ PSB_WSGX32(sgx_stat, PSB_CR_EVENT_HOST_CLEAR);
++ (void)PSB_RSGX32(PSB_CR_EVENT_HOST_CLEAR);
+
-+ return 0;
-+}
++ vdc_stat &= dev_priv->vdc_irq_mask;
++ spin_unlock(&dev_priv->irqmask_lock);
+
-+uint32_t psb_fence_advance_sequence(struct drm_device * dev,
-+ uint32_t fence_class)
-+{
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
-+ uint32_t sequence;
++ if (msvdx_stat) {
++ psb_msvdx_interrupt(dev, msvdx_stat);
++ handled = 1;
++ }
+
-+ spin_lock(&dev_priv->sequence_lock);
-+ sequence = ++dev_priv->sequence[fence_class];
-+ spin_unlock(&dev_priv->sequence_lock);
++ if (vdc_stat) {
++ /* MSVDX IRQ status is part of vdc_irq_mask */
++ psb_vdc_interrupt(dev, vdc_stat);
++ handled = 1;
++ }
+
-+ return sequence;
++ if (sgx_stat || sgx_stat2) {
++ psb_sgx_interrupt(dev, sgx_stat, sgx_stat2);
++ handled = 1;
++ }
++
++ if (!handled) {
++ return IRQ_NONE;
++ }
++
++ return IRQ_HANDLED;
+}
+
-+void psb_fence_handler(struct drm_device *dev, uint32_t fence_class)
++void psb_msvdx_irq_preinstall(struct drm_psb_private *dev_priv)
+{
-+ struct drm_fence_manager *fm = &dev->fm;
-+ struct drm_fence_class_manager *fc = &fm->fence_class[fence_class];
-+
-+#ifdef FIX_TG_16
-+ if (fence_class == 0) {
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
++ unsigned long mtx_int = 0;
++ dev_priv->vdc_irq_mask |= _PSB_IRQ_MSVDX_FLAG;
+
-+ if ((atomic_read(&dev_priv->ta_wait_2d_irq) == 1) &&
-+ (PSB_RSGX32(PSB_CR_2D_SOCIF) == _PSB_C2_SOCIF_EMPTY) &&
-+ ((PSB_RSGX32(PSB_CR_2D_BLIT_STATUS) &
-+ _PSB_C2B_STATUS_BUSY) == 0))
-+ psb_resume_ta_2d_idle(dev_priv);
-+ }
-+#endif
-+ write_lock(&fm->lock);
-+ psb_fence_poll(dev, fence_class, fc->waiting_types);
-+ write_unlock(&fm->lock);
++ /*Clear MTX interrupt */
++ REGIO_WRITE_FIELD_LITE(mtx_int, MSVDX_INTERRUPT_STATUS, CR_MTX_IRQ, 1);
++ PSB_WMSVDX32(mtx_int, MSVDX_INTERRUPT_CLEAR);
+}
+
-+static int psb_fence_wait(struct drm_fence_object *fence,
-+ int lazy, int interruptible, uint32_t mask)
++void psb_irq_preinstall(struct drm_device *dev)
+{
-+ struct drm_device *dev = fence->dev;
-+ struct drm_fence_class_manager *fc =
-+ &dev->fm.fence_class[fence->fence_class];
-+ int ret = 0;
-+ unsigned long timeout = DRM_HZ *
-+ ((fence->fence_class == PSB_ENGINE_TA) ? 30 : 3);
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
++ spin_lock(&dev_priv->irqmask_lock);
++ PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
++ PSB_WVDC32(0x00000000, PSB_INT_MASK_R);
++ PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
++ PSB_WSGX32(0x00000000, PSB_CR_EVENT_HOST_ENABLE);
++ (void)PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE);
+
-+ drm_fence_object_flush(fence, mask);
-+ if (interruptible)
-+ ret = wait_event_interruptible_timeout
-+ (fc->fence_queue, drm_fence_object_signaled(fence, mask),
-+ timeout);
-+ else
-+ ret = wait_event_timeout
-+ (fc->fence_queue, drm_fence_object_signaled(fence, mask),
-+ timeout);
++ dev_priv->sgx_irq_mask = _PSB_CE_PIXELBE_END_RENDER |
++ _PSB_CE_DPM_3D_MEM_FREE |
++ _PSB_CE_TA_FINISHED |
++ _PSB_CE_DPM_REACHED_MEM_THRESH |
++ _PSB_CE_DPM_OUT_OF_MEMORY_GBL |
++ _PSB_CE_DPM_OUT_OF_MEMORY_MT |
++ _PSB_CE_TA_TERMINATE | _PSB_CE_SW_EVENT;
+
-+ if (unlikely(ret == -ERESTARTSYS))
-+ return -EAGAIN;
++ dev_priv->sgx2_irq_mask = _PSB_CE2_BIF_REQUESTER_FAULT;
+
-+ if (unlikely(ret == 0))
-+ return -EBUSY;
++ dev_priv->vdc_irq_mask = _PSB_IRQ_SGX_FLAG | _PSB_IRQ_MSVDX_FLAG;
++
++ if (!drm_psb_disable_vsync)
++ dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG |
++ _PSB_VSYNC_PIPEB_FLAG;
++
++ /*Clear MTX interrupt */
++ {
++ unsigned long mtx_int = 0;
++ REGIO_WRITE_FIELD_LITE(mtx_int, MSVDX_INTERRUPT_STATUS,
++ CR_MTX_IRQ, 1);
++ PSB_WMSVDX32(mtx_int, MSVDX_INTERRUPT_CLEAR);
++ }
++ spin_unlock(&dev_priv->irqmask_lock);
++}
++
++void psb_msvdx_irq_postinstall(struct drm_psb_private *dev_priv)
++{
++ /* Enable Mtx Interupt to host */
++ unsigned long enables = 0;
++ PSB_DEBUG_GENERAL("Setting up MSVDX IRQs.....\n");
++ REGIO_WRITE_FIELD_LITE(enables, MSVDX_INTERRUPT_STATUS, CR_MTX_IRQ, 1);
++ PSB_WMSVDX32(enables, MSVDX_HOST_INTERRUPT_ENABLE);
++}
++
++int psb_irq_postinstall(struct drm_device *dev)
++{
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
++ unsigned long irqflags;
+
++ spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
++ PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
++ PSB_WSGX32(dev_priv->sgx2_irq_mask, PSB_CR_EVENT_HOST_ENABLE2);
++ PSB_WSGX32(dev_priv->sgx_irq_mask, PSB_CR_EVENT_HOST_ENABLE);
++ (void)PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE);
++ /****MSVDX IRQ Setup...*****/
++ /* Enable Mtx Interupt to host */
++ {
++ unsigned long enables = 0;
++ PSB_DEBUG_GENERAL("Setting up MSVDX IRQs.....\n");
++ REGIO_WRITE_FIELD_LITE(enables, MSVDX_INTERRUPT_STATUS,
++ CR_MTX_IRQ, 1);
++ PSB_WMSVDX32(enables, MSVDX_HOST_INTERRUPT_ENABLE);
++ }
++ dev_priv->irq_enabled = 1;
++ spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
+ return 0;
+}
+
-+struct drm_fence_driver psb_fence_driver = {
-+ .num_classes = PSB_NUM_ENGINES,
-+ .wrap_diff = (1 << 30),
-+ .flush_diff = (1 << 29),
-+ .sequence_mask = 0xFFFFFFFFU,
-+ .has_irq = NULL,
-+ .emit = psb_fence_emit_sequence,
-+ .flush = NULL,
-+ .poll = psb_fence_poll,
-+ .needed_flush = NULL,
-+ .wait = psb_fence_wait
-+};
-Index: linux-2.6.28/drivers/gpu/drm/psb/psb_gtt.c
++void psb_irq_uninstall(struct drm_device *dev)
++{
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
++ unsigned long irqflags;
++
++ spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
++
++ dev_priv->sgx_irq_mask = 0x00000000;
++ dev_priv->sgx2_irq_mask = 0x00000000;
++ dev_priv->vdc_irq_mask = 0x00000000;
++
++ PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
++ PSB_WVDC32(0xFFFFFFFF, PSB_INT_MASK_R);
++ PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
++ PSB_WSGX32(dev_priv->sgx_irq_mask, PSB_CR_EVENT_HOST_ENABLE);
++ PSB_WSGX32(dev_priv->sgx2_irq_mask, PSB_CR_EVENT_HOST_ENABLE2);
++ wmb();
++ PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R);
++ PSB_WSGX32(PSB_RSGX32(PSB_CR_EVENT_STATUS), PSB_CR_EVENT_HOST_CLEAR);
++ PSB_WSGX32(PSB_RSGX32(PSB_CR_EVENT_STATUS2), PSB_CR_EVENT_HOST_CLEAR2);
++
++ /****MSVDX IRQ Setup...*****/
++ /* Clear interrupt enabled flag */
++ PSB_WMSVDX32(0, MSVDX_HOST_INTERRUPT_ENABLE);
++
++ dev_priv->irq_enabled = 0;
++ spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
++
++}
++
++void psb_2D_irq_off(struct drm_psb_private *dev_priv)
++{
++ unsigned long irqflags;
++ uint32_t old_mask;
++ uint32_t cleared_mask;
++
++ spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
++ --dev_priv->irqen_count_2d;
++ if (dev_priv->irq_enabled && dev_priv->irqen_count_2d == 0) {
++
++ old_mask = dev_priv->sgx_irq_mask;
++ dev_priv->sgx_irq_mask &= ~_PSB_CE_TWOD_COMPLETE;
++ PSB_WSGX32(dev_priv->sgx_irq_mask, PSB_CR_EVENT_HOST_ENABLE);
++ (void)PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE);
++
++ cleared_mask = (old_mask ^ dev_priv->sgx_irq_mask) & old_mask;
++ PSB_WSGX32(cleared_mask, PSB_CR_EVENT_HOST_CLEAR);
++ (void)PSB_RSGX32(PSB_CR_EVENT_HOST_CLEAR);
++ }
++ spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
++}
++
++void psb_2D_irq_on(struct drm_psb_private *dev_priv)
++{
++ unsigned long irqflags;
++
++ spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
++ if (dev_priv->irq_enabled && dev_priv->irqen_count_2d == 0) {
++ dev_priv->sgx_irq_mask |= _PSB_CE_TWOD_COMPLETE;
++ PSB_WSGX32(dev_priv->sgx_irq_mask, PSB_CR_EVENT_HOST_ENABLE);
++ (void)PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE);
++ }
++ ++dev_priv->irqen_count_2d;
++ spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
++}
++
++static int psb_vblank_do_wait(struct drm_device *dev, unsigned int *sequence,
++ atomic_t * counter)
++{
++ unsigned int cur_vblank;
++ int ret = 0;
++
++ DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
++ (((cur_vblank = atomic_read(counter))
++ - *sequence) <= (1 << 23)));
++
++ *sequence = cur_vblank;
++
++ return ret;
++}
++
++int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence)
++{
++ int ret;
++
++ ret = psb_vblank_do_wait(dev, sequence, &dev->vbl_received);
++ return ret;
++}
++
++int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence)
++{
++ int ret;
++
++ ret = psb_vblank_do_wait(dev, sequence, &dev->vbl_received2);
++ return ret;
++}
++
++void psb_msvdx_irq_off(struct drm_psb_private *dev_priv)
++{
++ unsigned long irqflags;
++
++ spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
++ if (dev_priv->irq_enabled) {
++ dev_priv->vdc_irq_mask &= ~_PSB_IRQ_MSVDX_FLAG;
++ PSB_WSGX32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
++ (void)PSB_RSGX32(PSB_INT_ENABLE_R);
++ }
++ spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
++}
++
++void psb_msvdx_irq_on(struct drm_psb_private *dev_priv)
++{
++ unsigned long irqflags;
++
++ spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
++ if (dev_priv->irq_enabled) {
++ dev_priv->vdc_irq_mask |= _PSB_IRQ_MSVDX_FLAG;
++ PSB_WSGX32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
++ (void)PSB_RSGX32(PSB_INT_ENABLE_R);
++ }
++ spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
++}
+Index: linux-2.6.28/drivers/gpu/drm/psb/psb_mmu.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/psb/psb_gtt.c 2009-02-12 09:14:41.000000000 +0000
-@@ -0,0 +1,233 @@
++++ linux-2.6.28/drivers/gpu/drm/psb/psb_mmu.c 2009-02-12 09:14:42.000000000 +0000
+@@ -0,0 +1,1037 @@
+/**************************************************************************
+ * Copyright (c) 2007, Intel Corporation.
+ * All Rights Reserved.
+ * develop this driver.
+ *
+ **************************************************************************/
-+/*
-+ * Authors: Thomas Hellstrom <thomas-at-tungstengraphics.com>
-+ */
+#include "drmP.h"
+#include "psb_drv.h"
++#include "psb_reg.h"
+
-+static inline uint32_t psb_gtt_mask_pte(uint32_t pfn, int type)
-+{
-+ uint32_t mask = PSB_PTE_VALID;
-+
-+ if (type & PSB_MMU_CACHED_MEMORY)
-+ mask |= PSB_PTE_CACHED;
-+ if (type & PSB_MMU_RO_MEMORY)
-+ mask |= PSB_PTE_RO;
-+ if (type & PSB_MMU_WO_MEMORY)
-+ mask |= PSB_PTE_WO;
-+
-+ return (pfn << PAGE_SHIFT) | mask;
-+}
++/*
++ * Code for the SGX MMU:
++ */
+
-+struct psb_gtt *psb_gtt_alloc(struct drm_device *dev)
-+{
-+ struct psb_gtt *tmp = drm_calloc(1, sizeof(*tmp), DRM_MEM_DRIVER);
++/*
++ * clflush on one processor only:
++ * clflush should apparently flush the cache line on all processors in an
++ * SMP system.
++ */
+
-+ if (!tmp)
-+ return NULL;
++/*
++ * kmap atomic:
++ * The usage of the slots must be completely encapsulated within a spinlock, and
++ * no other functions that may be using the locks for other purposed may be
++ * called from within the locked region.
++ * Since the slots are per processor, this will guarantee that we are the only
++ * user.
++ */
+
-+ init_rwsem(&tmp->sem);
-+ tmp->dev = dev;
++/*
++ * TODO: Inserting ptes from an interrupt handler:
++ * This may be desirable for some SGX functionality where the GPU can fault in
++ * needed pages. For that, we need to make an atomic insert_pages function, that
++ * may fail.
++ * If it fails, the caller need to insert the page using a workqueue function,
++ * but on average it should be fast.
++ */
+
-+ return tmp;
-+}
++struct psb_mmu_driver {
++ /* protects driver- and pd structures. Always take in read mode
++ * before taking the page table spinlock.
++ */
++ struct rw_semaphore sem;
+
-+void psb_gtt_takedown(struct psb_gtt *pg, int free)
-+{
-+ struct drm_psb_private *dev_priv = pg->dev->dev_private;
++ /* protects page tables, directory tables and pt tables.
++ * and pt structures.
++ */
++ spinlock_t lock;
+
-+ if (!pg)
-+ return;
++ atomic_t needs_tlbflush;
++ atomic_t *msvdx_mmu_invaldc;
++ uint8_t __iomem *register_map;
++ struct psb_mmu_pd *default_pd;
++ uint32_t bif_ctrl;
++ int has_clflush;
++ int clflush_add;
++ unsigned long clflush_mask;
++};
+
-+ if (pg->gtt_map) {
-+ iounmap(pg->gtt_map);
-+ pg->gtt_map = NULL;
-+ }
-+ if (pg->initialized) {
-+ pci_write_config_word(pg->dev->pdev, PSB_GMCH_CTRL,
-+ pg->gmch_ctrl);
-+ PSB_WVDC32(pg->pge_ctl, PSB_PGETBL_CTL);
-+ (void)PSB_RVDC32(PSB_PGETBL_CTL);
-+ }
-+ if (free)
-+ drm_free(pg, sizeof(*pg), DRM_MEM_DRIVER);
++struct psb_mmu_pd;
++
++struct psb_mmu_pt {
++ struct psb_mmu_pd *pd;
++ uint32_t index;
++ uint32_t count;
++ struct page *p;
++ uint32_t *v;
++};
++
++struct psb_mmu_pd {
++ struct psb_mmu_driver *driver;
++ int hw_context;
++ struct psb_mmu_pt **tables;
++ struct page *p;
++ struct page *dummy_pt;
++ struct page *dummy_page;
++ uint32_t pd_mask;
++ uint32_t invalid_pde;
++ uint32_t invalid_pte;
++};
++
++static inline uint32_t psb_mmu_pt_index(uint32_t offset)
++{
++ return (offset >> PSB_PTE_SHIFT) & 0x3FF;
++}
++static inline uint32_t psb_mmu_pd_index(uint32_t offset)
++{
++ return (offset >> PSB_PDE_SHIFT);
+}
+
-+int psb_gtt_init(struct psb_gtt *pg, int resume)
++#if defined(CONFIG_X86)
++static inline void psb_clflush(void *addr)
+{
-+ struct drm_device *dev = pg->dev;
-+ struct drm_psb_private *dev_priv = dev->dev_private;
-+ unsigned gtt_pages;
-+ unsigned long stolen_size;
-+ unsigned i, num_pages;
-+ unsigned pfn_base;
++ __asm__ __volatile__("clflush (%0)\n"::"r"(addr):"memory");
++}
+
-+ int ret = 0;
-+ uint32_t pte;
++static inline void psb_mmu_clflush(struct psb_mmu_driver *driver, void *addr)
++{
++ if (!driver->has_clflush)
++ return;
+
-+ pci_read_config_word(dev->pdev, PSB_GMCH_CTRL, &pg->gmch_ctrl);
-+ pci_write_config_word(dev->pdev, PSB_GMCH_CTRL,
-+ pg->gmch_ctrl | _PSB_GMCH_ENABLED);
++ mb();
++ psb_clflush(addr);
++ mb();
++}
++#else
+
-+ pg->pge_ctl = PSB_RVDC32(PSB_PGETBL_CTL);
-+ PSB_WVDC32(pg->pge_ctl | _PSB_PGETBL_ENABLED, PSB_PGETBL_CTL);
-+ (void)PSB_RVDC32(PSB_PGETBL_CTL);
++static inline void psb_mmu_clflush(struct psb_mmu_driver *driver, void *addr)
++{;
++}
+
-+ pg->initialized = 1;
++#endif
+
-+ pg->gtt_phys_start = pg->pge_ctl & PAGE_MASK;
-+ pg->gatt_start = pci_resource_start(dev->pdev, PSB_GATT_RESOURCE);
-+ pg->gtt_start = pci_resource_start(dev->pdev, PSB_GTT_RESOURCE);
-+ gtt_pages = pci_resource_len(dev->pdev, PSB_GTT_RESOURCE) >> PAGE_SHIFT;
-+ pg->gatt_pages = pci_resource_len(dev->pdev, PSB_GATT_RESOURCE)
-+ >> PAGE_SHIFT;
-+ pci_read_config_dword(dev->pdev, PSB_BSM, &pg->stolen_base);
-+ stolen_size = pg->gtt_phys_start - pg->stolen_base - PAGE_SIZE;
++static inline void psb_iowrite32(const struct psb_mmu_driver *d,
++ uint32_t val, uint32_t offset)
++{
++ iowrite32(val, d->register_map + offset);
++}
+
-+ PSB_DEBUG_INIT("GTT phys start: 0x%08x.\n", pg->gtt_phys_start);
-+ PSB_DEBUG_INIT("GTT start: 0x%08x.\n", pg->gtt_start);
-+ PSB_DEBUG_INIT("GATT start: 0x%08x.\n", pg->gatt_start);
-+ PSB_DEBUG_INIT("GTT pages: %u\n", gtt_pages);
-+ PSB_DEBUG_INIT("Stolen size: %lu kiB\n", stolen_size / 1024);
++static inline uint32_t psb_ioread32(const struct psb_mmu_driver *d,
++ uint32_t offset)
++{
++ return ioread32(d->register_map + offset);
++}
+
-+ if (resume && (gtt_pages != pg->gtt_pages) &&
-+ (stolen_size != pg->stolen_size)) {
-+ DRM_ERROR("GTT resume error.\n");
-+ ret = -EINVAL;
-+ goto out_err;
++static void psb_mmu_flush_pd_locked(struct psb_mmu_driver *driver, int force)
++{
++ if (atomic_read(&driver->needs_tlbflush) || force) {
++ uint32_t val = psb_ioread32(driver, PSB_CR_BIF_CTRL);
++ psb_iowrite32(driver, val | _PSB_CB_CTRL_INVALDC,
++ PSB_CR_BIF_CTRL);
++ wmb();
++ psb_iowrite32(driver, val & ~_PSB_CB_CTRL_INVALDC,
++ PSB_CR_BIF_CTRL);
++ (void)psb_ioread32(driver, PSB_CR_BIF_CTRL);
++ if (driver->msvdx_mmu_invaldc)
++ atomic_set(driver->msvdx_mmu_invaldc, 1);
+ }
++ atomic_set(&driver->needs_tlbflush, 0);
++}
+
-+ pg->gtt_pages = gtt_pages;
-+ pg->stolen_size = stolen_size;
-+ pg->gtt_map =
-+ ioremap_nocache(pg->gtt_phys_start, gtt_pages << PAGE_SHIFT);
-+ if (!pg->gtt_map) {
-+ DRM_ERROR("Failure to map gtt.\n");
-+ ret = -ENOMEM;
-+ goto out_err;
-+ }
++static void psb_mmu_flush_pd(struct psb_mmu_driver *driver, int force)
++{
++ down_write(&driver->sem);
++ psb_mmu_flush_pd_locked(driver, force);
++ up_write(&driver->sem);
++}
+
-+ /*
-+ * insert stolen pages.
-+ */
++void psb_mmu_flush(struct psb_mmu_driver *driver)
++{
++ uint32_t val;
+
-+ pfn_base = pg->stolen_base >> PAGE_SHIFT;
-+ num_pages = stolen_size >> PAGE_SHIFT;
-+ PSB_DEBUG_INIT("Set up %d stolen pages starting at 0x%08x\n",
-+ num_pages, pfn_base);
-+ for (i = 0; i < num_pages; ++i) {
-+ pte = psb_gtt_mask_pte(pfn_base + i, 0);
-+ iowrite32(pte, pg->gtt_map + i);
-+ }
++ down_write(&driver->sem);
++ val = psb_ioread32(driver, PSB_CR_BIF_CTRL);
++ if (atomic_read(&driver->needs_tlbflush))
++ psb_iowrite32(driver, val | _PSB_CB_CTRL_INVALDC,
++ PSB_CR_BIF_CTRL);
++ else
++ psb_iowrite32(driver, val | _PSB_CB_CTRL_FLUSH,
++ PSB_CR_BIF_CTRL);
++ wmb();
++ psb_iowrite32(driver,
++ val & ~(_PSB_CB_CTRL_FLUSH | _PSB_CB_CTRL_INVALDC),
++ PSB_CR_BIF_CTRL);
++ (void)psb_ioread32(driver, PSB_CR_BIF_CTRL);
++ atomic_set(&driver->needs_tlbflush, 0);
++ if (driver->msvdx_mmu_invaldc)
++ atomic_set(driver->msvdx_mmu_invaldc, 1);
++ up_write(&driver->sem);
++}
+
-+ /*
-+ * Init rest of gtt.
-+ */
++void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context)
++{
++ uint32_t offset = (hw_context == 0) ? PSB_CR_BIF_DIR_LIST_BASE0 :
++ PSB_CR_BIF_DIR_LIST_BASE1 + hw_context * 4;
+
-+ pfn_base = page_to_pfn(dev_priv->scratch_page);
-+ pte = psb_gtt_mask_pte(pfn_base, 0);
-+ PSB_DEBUG_INIT("Initializing the rest of a total "
-+ "of %d gtt pages.\n", pg->gatt_pages);
++ drm_ttm_cache_flush();
++ down_write(&pd->driver->sem);
++ psb_iowrite32(pd->driver, (page_to_pfn(pd->p) << PAGE_SHIFT), offset);
++ wmb();
++ psb_mmu_flush_pd_locked(pd->driver, 1);
++ pd->hw_context = hw_context;
++ up_write(&pd->driver->sem);
+
-+ for (; i < pg->gatt_pages; ++i)
-+ iowrite32(pte, pg->gtt_map + i);
-+ (void)ioread32(pg->gtt_map + i - 1);
++}
+
-+ return 0;
++static inline unsigned long psb_pd_addr_end(unsigned long addr,
++ unsigned long end)
++{
+
-+ out_err:
-+ psb_gtt_takedown(pg, 0);
-+ return ret;
++ addr = (addr + PSB_PDE_MASK + 1) & ~PSB_PDE_MASK;
++ return (addr < end) ? addr : end;
+}
+
-+int psb_gtt_insert_pages(struct psb_gtt *pg, struct page **pages,
-+ unsigned offset_pages, unsigned num_pages,
-+ unsigned desired_tile_stride, unsigned hw_tile_stride,
-+ int type)
++static inline uint32_t psb_mmu_mask_pte(uint32_t pfn, int type)
+{
-+ unsigned rows = 1;
-+ unsigned add;
-+ unsigned row_add;
-+ unsigned i;
-+ unsigned j;
-+ uint32_t *cur_page = NULL;
-+ uint32_t pte;
++ uint32_t mask = PSB_PTE_VALID;
+
-+ if (hw_tile_stride)
-+ rows = num_pages / desired_tile_stride;
-+ else
-+ desired_tile_stride = num_pages;
++ if (type & PSB_MMU_CACHED_MEMORY)
++ mask |= PSB_PTE_CACHED;
++ if (type & PSB_MMU_RO_MEMORY)
++ mask |= PSB_PTE_RO;
++ if (type & PSB_MMU_WO_MEMORY)
++ mask |= PSB_PTE_WO;
+
-+ add = desired_tile_stride;
-+ row_add = hw_tile_stride;
++ return (pfn << PAGE_SHIFT) | mask;
++}
+
-+ down_read(&pg->sem);
-+ for (i = 0; i < rows; ++i) {
-+ cur_page = pg->gtt_map + offset_pages;
-+ for (j = 0; j < desired_tile_stride; ++j) {
-+ pte = psb_gtt_mask_pte(page_to_pfn(*pages++), type);
-+ iowrite32(pte, cur_page++);
-+ }
-+ offset_pages += add;
-+ }
-+ (void)ioread32(cur_page - 1);
-+ up_read(&pg->sem);
-+
-+ return 0;
-+}
-+
-+int psb_gtt_remove_pages(struct psb_gtt *pg, unsigned offset_pages,
-+ unsigned num_pages, unsigned desired_tile_stride,
-+ unsigned hw_tile_stride)
++struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
++ int trap_pagefaults, int invalid_type)
+{
-+ struct drm_psb_private *dev_priv = pg->dev->dev_private;
-+ unsigned rows = 1;
-+ unsigned add;
-+ unsigned row_add;
-+ unsigned i;
-+ unsigned j;
-+ uint32_t *cur_page = NULL;
-+ unsigned pfn_base = page_to_pfn(dev_priv->scratch_page);
-+ uint32_t pte = psb_gtt_mask_pte(pfn_base, 0);
++ struct psb_mmu_pd *pd = kmalloc(sizeof(*pd), GFP_KERNEL);
++ uint32_t *v;
++ int i;
+
-+ if (hw_tile_stride)
-+ rows = num_pages / desired_tile_stride;
-+ else
-+ desired_tile_stride = num_pages;
++ if (!pd)
++ return NULL;
+
-+ add = desired_tile_stride;
-+ row_add = hw_tile_stride;
++ pd->p = alloc_page(GFP_DMA32);
++ if (!pd->p)
++ goto out_err1;
++ pd->dummy_pt = alloc_page(GFP_DMA32);
++ if (!pd->dummy_pt)
++ goto out_err2;
++ pd->dummy_page = alloc_page(GFP_DMA32);
++ if (!pd->dummy_page)
++ goto out_err3;
+
-+ down_read(&pg->sem);
-+ for (i = 0; i < rows; ++i) {
-+ cur_page = pg->gtt_map + offset_pages;
-+ for (j = 0; j < desired_tile_stride; ++j) {
-+ iowrite32(pte, cur_page++);
-+ }
-+ offset_pages += add;
++ if (!trap_pagefaults) {
++ pd->invalid_pde = psb_mmu_mask_pte(page_to_pfn(pd->dummy_pt),
++ invalid_type |
++ PSB_MMU_CACHED_MEMORY);
++ pd->invalid_pte = psb_mmu_mask_pte(page_to_pfn(pd->dummy_page),
++ invalid_type |
++ PSB_MMU_CACHED_MEMORY);
++ } else {
++ pd->invalid_pde = 0;
++ pd->invalid_pte = 0;
+ }
-+ (void)ioread32(cur_page - 1);
-+ up_read(&pg->sem);
+
-+ return 0;
-+}
-Index: linux-2.6.28/drivers/gpu/drm/psb/psb_i2c.c
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/psb/psb_i2c.c 2009-02-12 09:14:41.000000000 +0000
-@@ -0,0 +1,179 @@
-+/*
-+ * Copyright © 2006-2007 Intel Corporation
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice (including the next
-+ * paragraph) shall be included in all copies or substantial portions of the
-+ * Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-+ * DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors:
-+ * Eric Anholt <eric@anholt.net>
-+ */
-+/*
-+ * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
-+ * Jesse Barnes <jesse.barnes@intel.com>
-+ */
++ v = kmap(pd->dummy_pt);
++ for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i) {
++ v[i] = pd->invalid_pte;
++ }
++ kunmap(pd->dummy_pt);
+
-+#include <linux/i2c.h>
-+#include <linux/i2c-id.h>
-+#include <linux/i2c-algo-bit.h>
-+#include "drmP.h"
-+#include "drm.h"
-+#include "intel_drv.h"
-+#include "psb_drv.h"
++ v = kmap(pd->p);
++ for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i) {
++ v[i] = pd->invalid_pde;
++ }
++ kunmap(pd->p);
+
-+/*
-+ * Intel GPIO access functions
-+ */
++ clear_page(kmap(pd->dummy_page));
++ kunmap(pd->dummy_page);
+
-+#define I2C_RISEFALL_TIME 20
++ pd->tables = vmalloc_user(sizeof(struct psb_mmu_pt *) * 1024);
++ if (!pd->tables)
++ goto out_err4;
+
-+static int get_clock(void *data)
-+{
-+ struct intel_i2c_chan *chan = data;
-+ struct drm_psb_private *dev_priv = chan->drm_dev->dev_private;
-+ uint32_t val;
++ pd->hw_context = -1;
++ pd->pd_mask = PSB_PTE_VALID;
++ pd->driver = driver;
+
-+ val = PSB_RVDC32(chan->reg);
-+ return ((val & GPIO_CLOCK_VAL_IN) != 0);
++ return pd;
++
++ out_err4:
++ __free_page(pd->dummy_page);
++ out_err3:
++ __free_page(pd->dummy_pt);
++ out_err2:
++ __free_page(pd->p);
++ out_err1:
++ kfree(pd);
++ return NULL;
+}
+
-+static int get_data(void *data)
++void psb_mmu_free_pt(struct psb_mmu_pt *pt)
+{
-+ struct intel_i2c_chan *chan = data;
-+ struct drm_psb_private *dev_priv = chan->drm_dev->dev_private;
-+ uint32_t val;
-+
-+ val = PSB_RVDC32(chan->reg);
-+ return ((val & GPIO_DATA_VAL_IN) != 0);
++ __free_page(pt->p);
++ kfree(pt);
+}
+
-+static void set_clock(void *data, int state_high)
++void psb_mmu_free_pagedir(struct psb_mmu_pd *pd)
+{
-+ struct intel_i2c_chan *chan = data;
-+ struct drm_psb_private *dev_priv = chan->drm_dev->dev_private;
-+ uint32_t reserved = 0, clock_bits;
++ struct psb_mmu_driver *driver = pd->driver;
++ struct psb_mmu_pt *pt;
++ int i;
+
-+ /* On most chips, these bits must be preserved in software. */
-+ reserved = PSB_RVDC32(chan->reg) & (GPIO_DATA_PULLUP_DISABLE |
-+ GPIO_CLOCK_PULLUP_DISABLE);
++ down_write(&driver->sem);
++ if (pd->hw_context != -1) {
++ psb_iowrite32(driver, 0,
++ PSB_CR_BIF_DIR_LIST_BASE0 + pd->hw_context * 4);
++ psb_mmu_flush_pd_locked(driver, 1);
++ }
+
-+ if (state_high)
-+ clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
-+ else
-+ clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
-+ GPIO_CLOCK_VAL_MASK;
-+ PSB_WVDC32(reserved | clock_bits, chan->reg);
-+ udelay(I2C_RISEFALL_TIME); /* wait for the line to change state */
++ /* Should take the spinlock here, but we don't need to do that
++ since we have the semaphore in write mode. */
++
++ for (i = 0; i < 1024; ++i) {
++ pt = pd->tables[i];
++ if (pt)
++ psb_mmu_free_pt(pt);
++ }
++
++ vfree(pd->tables);
++ __free_page(pd->dummy_page);
++ __free_page(pd->dummy_pt);
++ __free_page(pd->p);
++ kfree(pd);
++ up_write(&driver->sem);
+}
+
-+static void set_data(void *data, int state_high)
++static struct psb_mmu_pt *psb_mmu_alloc_pt(struct psb_mmu_pd *pd)
+{
-+ struct intel_i2c_chan *chan = data;
-+ struct drm_psb_private *dev_priv = chan->drm_dev->dev_private;
-+ uint32_t reserved = 0, data_bits;
++ struct psb_mmu_pt *pt = kmalloc(sizeof(*pt), GFP_KERNEL);
++ void *v;
++ uint32_t clflush_add = pd->driver->clflush_add >> PAGE_SHIFT;
++ uint32_t clflush_count = PAGE_SIZE / clflush_add;
++ spinlock_t *lock = &pd->driver->lock;
++ uint8_t *clf;
++ uint32_t *ptes;
++ int i;
+
-+ /* On most chips, these bits must be preserved in software. */
-+ reserved = PSB_RVDC32(chan->reg) & (GPIO_DATA_PULLUP_DISABLE |
-+ GPIO_CLOCK_PULLUP_DISABLE);
++ if (!pt)
++ return NULL;
+
-+ if (state_high)
-+ data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
-+ else
-+ data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
-+ GPIO_DATA_VAL_MASK;
++ pt->p = alloc_page(GFP_DMA32);
++ if (!pt->p) {
++ kfree(pt);
++ return NULL;
++ }
+
-+ PSB_WVDC32(data_bits, chan->reg);
-+ udelay(I2C_RISEFALL_TIME); /* wait for the line to change state */
++ spin_lock(lock);
++
++ v = kmap_atomic(pt->p, KM_USER0);
++ clf = (uint8_t *) v;
++ ptes = (uint32_t *) v;
++ for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i) {
++ *ptes++ = pd->invalid_pte;
++ }
++
++#if defined(CONFIG_X86)
++ if (pd->driver->has_clflush && pd->hw_context != -1) {
++ mb();
++ for (i = 0; i < clflush_count; ++i) {
++ psb_clflush(clf);
++ clf += clflush_add;
++ }
++ mb();
++ }
++#endif
++ kunmap_atomic(v, KM_USER0);
++ spin_unlock(lock);
++
++ pt->count = 0;
++ pt->pd = pd;
++ pt->index = 0;
++
++ return pt;
+}
+
-+/**
-+ * intel_i2c_create - instantiate an Intel i2c bus using the specified GPIO reg
-+ * @dev: DRM device
-+ * @output: driver specific output device
-+ * @reg: GPIO reg to use
-+ * @name: name for this bus
-+ *
-+ * Creates and registers a new i2c bus with the Linux i2c layer, for use
-+ * in output probing and control (e.g. DDC or SDVO control functions).
-+ *
-+ * Possible values for @reg include:
-+ * %GPIOA
-+ * %GPIOB
-+ * %GPIOC
-+ * %GPIOD
-+ * %GPIOE
-+ * %GPIOF
-+ * %GPIOG
-+ * %GPIOH
-+ * see PRM for details on how these different busses are used.
-+ */
-+struct intel_i2c_chan *intel_i2c_create(struct drm_device *dev,
-+ const uint32_t reg, const char *name)
++struct psb_mmu_pt *psb_mmu_pt_alloc_map_lock(struct psb_mmu_pd *pd,
++ unsigned long addr)
+{
-+ struct intel_i2c_chan *chan;
-+
-+ chan = kzalloc(sizeof(struct intel_i2c_chan), GFP_KERNEL);
-+ if (!chan)
-+ goto out_free;
-+
-+ chan->drm_dev = dev;
-+ chan->reg = reg;
-+ snprintf(chan->adapter.name, I2C_NAME_SIZE, "intel drm %s", name);
-+ chan->adapter.owner = THIS_MODULE;
-+ chan->adapter.id = I2C_HW_B_INTELFB;
-+ chan->adapter.algo_data = &chan->algo;
-+ chan->adapter.dev.parent = &dev->pdev->dev;
-+ chan->algo.setsda = set_data;
-+ chan->algo.setscl = set_clock;
-+ chan->algo.getsda = get_data;
-+ chan->algo.getscl = get_clock;
-+ chan->algo.udelay = 20;
-+ chan->algo.timeout = usecs_to_jiffies(2200);
-+ chan->algo.data = chan;
-+
-+ i2c_set_adapdata(&chan->adapter, chan);
++ uint32_t index = psb_mmu_pd_index(addr);
++ struct psb_mmu_pt *pt;
++ volatile uint32_t *v;
++ spinlock_t *lock = &pd->driver->lock;
+
-+ if (i2c_bit_add_bus(&chan->adapter))
-+ goto out_free;
++ spin_lock(lock);
++ pt = pd->tables[index];
++ while (!pt) {
++ spin_unlock(lock);
++ pt = psb_mmu_alloc_pt(pd);
++ if (!pt)
++ return NULL;
++ spin_lock(lock);
+
-+ /* JJJ: raise SCL and SDA? */
-+ set_data(chan, 1);
-+ set_clock(chan, 1);
-+ udelay(20);
++ if (pd->tables[index]) {
++ spin_unlock(lock);
++ psb_mmu_free_pt(pt);
++ spin_lock(lock);
++ pt = pd->tables[index];
++ continue;
++ }
+
-+ return chan;
++ v = kmap_atomic(pd->p, KM_USER0);
++ pd->tables[index] = pt;
++ v[index] = (page_to_pfn(pt->p) << 12) | pd->pd_mask;
++ pt->index = index;
++ kunmap_atomic((void *)v, KM_USER0);
+
-+ out_free:
-+ kfree(chan);
-+ return NULL;
++ if (pd->hw_context != -1) {
++ psb_mmu_clflush(pd->driver, (void *)&v[index]);
++ atomic_set(&pd->driver->needs_tlbflush, 1);
++ }
++ }
++ pt->v = kmap_atomic(pt->p, KM_USER0);
++ return pt;
+}
+
-+/**
-+ * intel_i2c_destroy - unregister and free i2c bus resources
-+ * @output: channel to free
-+ *
-+ * Unregister the adapter from the i2c layer, then free the structure.
-+ */
-+void intel_i2c_destroy(struct intel_i2c_chan *chan)
++static struct psb_mmu_pt *psb_mmu_pt_map_lock(struct psb_mmu_pd *pd,
++ unsigned long addr)
+{
-+ if (!chan)
-+ return;
++ uint32_t index = psb_mmu_pd_index(addr);
++ struct psb_mmu_pt *pt;
++ spinlock_t *lock = &pd->driver->lock;
+
-+ i2c_del_adapter(&chan->adapter);
-+ kfree(chan);
++ spin_lock(lock);
++ pt = pd->tables[index];
++ if (!pt) {
++ spin_unlock(lock);
++ return NULL;
++ }
++ pt->v = kmap_atomic(pt->p, KM_USER0);
++ return pt;
+}
-Index: linux-2.6.28/drivers/gpu/drm/psb/psb_irq.c
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/psb/psb_irq.c 2009-02-12 09:14:41.000000000 +0000
-@@ -0,0 +1,382 @@
-+/**************************************************************************
-+ * Copyright (c) 2007, Intel Corporation.
-+ * All Rights Reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms and conditions of the GNU General Public License,
-+ * version 2, as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
-+ *
-+ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
-+ * develop this driver.
-+ *
-+ **************************************************************************/
-+/*
-+ */
-+
-+#include "drmP.h"
-+#include "psb_drv.h"
-+#include "psb_reg.h"
-+#include "psb_msvdx.h"
-+
-+/*
-+ * Video display controller interrupt.
-+ */
+
-+static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat)
++static void psb_mmu_pt_unmap_unlock(struct psb_mmu_pt *pt)
+{
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
-+ uint32_t pipe_stats;
-+ int wake = 0;
++ struct psb_mmu_pd *pd = pt->pd;
++ volatile uint32_t *v;
+
-+ if (!drm_psb_disable_vsync && (vdc_stat & _PSB_VSYNC_PIPEA_FLAG)) {
-+ pipe_stats = PSB_RVDC32(PSB_PIPEASTAT);
-+ atomic_inc(&dev->vbl_received);
-+ wake = 1;
-+ PSB_WVDC32(pipe_stats | _PSB_VBLANK_INTERRUPT_ENABLE |
-+ _PSB_VBLANK_CLEAR, PSB_PIPEASTAT);
-+ }
++ kunmap_atomic(pt->v, KM_USER0);
++ if (pt->count == 0) {
++ v = kmap_atomic(pd->p, KM_USER0);
++ v[pt->index] = pd->invalid_pde;
++ pd->tables[pt->index] = NULL;
+
-+ if (!drm_psb_disable_vsync && (vdc_stat & _PSB_VSYNC_PIPEB_FLAG)) {
-+ pipe_stats = PSB_RVDC32(PSB_PIPEBSTAT);
-+ atomic_inc(&dev->vbl_received2);
-+ wake = 1;
-+ PSB_WVDC32(pipe_stats | _PSB_VBLANK_INTERRUPT_ENABLE |
-+ _PSB_VBLANK_CLEAR, PSB_PIPEBSTAT);
++ if (pd->hw_context != -1) {
++ psb_mmu_clflush(pd->driver, (void *)&v[pt->index]);
++ atomic_set(&pd->driver->needs_tlbflush, 1);
++ }
++ kunmap_atomic(pt->v, KM_USER0);
++ spin_unlock(&pd->driver->lock);
++ psb_mmu_free_pt(pt);
++ return;
+ }
++ spin_unlock(&pd->driver->lock);
++}
+
-+ PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R);
-+ (void)PSB_RVDC32(PSB_INT_IDENTITY_R);
-+ DRM_READMEMORYBARRIER();
-+
-+ if (wake) {
-+ DRM_WAKEUP(&dev->vbl_queue);
-+ drm_vbl_send_signals(dev);
-+ }
++static inline void psb_mmu_set_pte(struct psb_mmu_pt *pt, unsigned long addr,
++ uint32_t pte)
++{
++ pt->v[psb_mmu_pt_index(addr)] = pte;
+}
+
-+/*
-+ * SGX interrupt source 1.
-+ */
++static inline void psb_mmu_invalidate_pte(struct psb_mmu_pt *pt,
++ unsigned long addr)
++{
++ pt->v[psb_mmu_pt_index(addr)] = pt->pd->invalid_pte;
++}
+
-+static void psb_sgx_interrupt(struct drm_device *dev, uint32_t sgx_stat,
-+ uint32_t sgx_stat2)
++#if 0
++static uint32_t psb_mmu_check_pte_locked(struct psb_mmu_pd *pd,
++ uint32_t mmu_offset)
+{
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
++ uint32_t *v;
++ uint32_t pfn;
+
-+ if (sgx_stat & _PSB_CE_TWOD_COMPLETE) {
-+ DRM_WAKEUP(&dev_priv->event_2d_queue);
-+ psb_fence_handler(dev, 0);
++ v = kmap_atomic(pd->p, KM_USER0);
++ if (!v) {
++ printk(KERN_INFO "Could not kmap pde page.\n");
++ return 0;
+ }
-+
-+ if (unlikely(sgx_stat2 & _PSB_CE2_BIF_REQUESTER_FAULT))
-+ psb_print_pagefault(dev_priv);
-+
-+ psb_scheduler_handler(dev_priv, sgx_stat);
++ pfn = v[psb_mmu_pd_index(mmu_offset)];
++ // printk(KERN_INFO "pde is 0x%08x\n",pfn);
++ kunmap_atomic(v, KM_USER0);
++ if (((pfn & 0x0F) != PSB_PTE_VALID)) {
++ printk(KERN_INFO "Strange pde at 0x%08x: 0x%08x.\n",
++ mmu_offset, pfn);
++ }
++ v = ioremap(pfn & 0xFFFFF000, 4096);
++ if (!v) {
++ printk(KERN_INFO "Could not kmap pte page.\n");
++ return 0;
++ }
++ pfn = v[psb_mmu_pt_index(mmu_offset)];
++ // printk(KERN_INFO "pte is 0x%08x\n",pfn);
++ iounmap(v);
++ if (((pfn & 0x0F) != PSB_PTE_VALID)) {
++ printk(KERN_INFO "Strange pte at 0x%08x: 0x%08x.\n",
++ mmu_offset, pfn);
++ }
++ return pfn >> PAGE_SHIFT;
+}
+
-+/*
-+ * MSVDX interrupt.
-+ */
-+static void psb_msvdx_interrupt(struct drm_device *dev, uint32_t msvdx_stat)
++static void psb_mmu_check_mirrored_gtt(struct psb_mmu_pd *pd,
++ uint32_t mmu_offset, uint32_t gtt_pages)
+{
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
++ uint32_t start;
++ uint32_t next;
+
-+ if (msvdx_stat & MSVDX_INTERRUPT_STATUS_CR_MMU_FAULT_IRQ_MASK) {
-+ /*Ideally we should we should never get to this */
-+ PSB_DEBUG_GENERAL
-+ ("******MSVDX: msvdx_stat: 0x%x fence2_irq_on=%d ***** (MMU FAULT)\n",
-+ msvdx_stat, dev_priv->fence2_irq_on);
-+
-+ /* Pause MMU */
-+ PSB_WMSVDX32(MSVDX_MMU_CONTROL0_CR_MMU_PAUSE_MASK,
-+ MSVDX_MMU_CONTROL0);
-+ DRM_WRITEMEMORYBARRIER();
-+
-+ /* Clear this interupt bit only */
-+ PSB_WMSVDX32(MSVDX_INTERRUPT_STATUS_CR_MMU_FAULT_IRQ_MASK,
-+ MSVDX_INTERRUPT_CLEAR);
-+ PSB_RMSVDX32(MSVDX_INTERRUPT_CLEAR);
-+ DRM_READMEMORYBARRIER();
-+
-+ dev_priv->msvdx_needs_reset = 1;
-+ } else if (msvdx_stat & MSVDX_INTERRUPT_STATUS_CR_MTX_IRQ_MASK) {
-+ PSB_DEBUG_GENERAL
-+ ("******MSVDX: msvdx_stat: 0x%x fence2_irq_on=%d ***** (MTX)\n",
-+ msvdx_stat, dev_priv->fence2_irq_on);
-+
-+ /* Clear all interupt bits */
-+ PSB_WMSVDX32(0xffff, MSVDX_INTERRUPT_CLEAR);
-+ PSB_RMSVDX32(MSVDX_INTERRUPT_CLEAR);
-+ DRM_READMEMORYBARRIER();
-+
-+ psb_msvdx_mtx_interrupt(dev);
++ printk(KERN_INFO "Checking mirrored gtt 0x%08x %d\n",
++ mmu_offset, gtt_pages);
++ down_read(&pd->driver->sem);
++ start = psb_mmu_check_pte_locked(pd, mmu_offset);
++ mmu_offset += PAGE_SIZE;
++ gtt_pages -= 1;
++ while (gtt_pages--) {
++ next = psb_mmu_check_pte_locked(pd, mmu_offset);
++ if (next != start + 1) {
++ printk(KERN_INFO "Ptes out of order: 0x%08x, 0x%08x.\n",
++ start, next);
++ }
++ start = next;
++ mmu_offset += PAGE_SIZE;
+ }
++ up_read(&pd->driver->sem);
+}
+
-+irqreturn_t psb_irq_handler(DRM_IRQ_ARGS)
-+{
-+ struct drm_device *dev = (struct drm_device *)arg;
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
-+
-+ uint32_t vdc_stat;
-+ uint32_t sgx_stat;
-+ uint32_t sgx_stat2;
-+ uint32_t msvdx_stat;
-+ int handled = 0;
-+
-+ spin_lock(&dev_priv->irqmask_lock);
-+
-+ vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R);
-+ sgx_stat = PSB_RSGX32(PSB_CR_EVENT_STATUS);
-+ sgx_stat2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
-+ msvdx_stat = PSB_RMSVDX32(MSVDX_INTERRUPT_STATUS);
++#endif
+
-+ sgx_stat2 &= dev_priv->sgx2_irq_mask;
-+ sgx_stat &= dev_priv->sgx_irq_mask;
-+ PSB_WSGX32(sgx_stat2, PSB_CR_EVENT_HOST_CLEAR2);
-+ PSB_WSGX32(sgx_stat, PSB_CR_EVENT_HOST_CLEAR);
-+ (void)PSB_RSGX32(PSB_CR_EVENT_HOST_CLEAR);
++void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd,
++ uint32_t mmu_offset, uint32_t gtt_start,
++ uint32_t gtt_pages)
++{
++ uint32_t *v;
++ uint32_t start = psb_mmu_pd_index(mmu_offset);
++ struct psb_mmu_driver *driver = pd->driver;
+
-+ vdc_stat &= dev_priv->vdc_irq_mask;
-+ spin_unlock(&dev_priv->irqmask_lock);
++ down_read(&driver->sem);
++ spin_lock(&driver->lock);
+
-+ if (msvdx_stat) {
-+ psb_msvdx_interrupt(dev, msvdx_stat);
-+ handled = 1;
-+ }
++ v = kmap_atomic(pd->p, KM_USER0);
++ v += start;
+
-+ if (vdc_stat) {
-+ /* MSVDX IRQ status is part of vdc_irq_mask */
-+ psb_vdc_interrupt(dev, vdc_stat);
-+ handled = 1;
++ while (gtt_pages--) {
++ *v++ = gtt_start | pd->pd_mask;
++ gtt_start += PAGE_SIZE;
+ }
+
-+ if (sgx_stat || sgx_stat2) {
-+ psb_sgx_interrupt(dev, sgx_stat, sgx_stat2);
-+ handled = 1;
-+ }
++ drm_ttm_cache_flush();
++ kunmap_atomic(v, KM_USER0);
++ spin_unlock(&driver->lock);
+
-+ if (!handled) {
-+ return IRQ_NONE;
-+ }
++ if (pd->hw_context != -1)
++ atomic_set(&pd->driver->needs_tlbflush, 1);
+
-+ return IRQ_HANDLED;
++ up_read(&pd->driver->sem);
++ psb_mmu_flush_pd(pd->driver, 0);
+}
+
-+void psb_msvdx_irq_preinstall(struct drm_psb_private *dev_priv)
++struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver *driver)
+{
-+ unsigned long mtx_int = 0;
-+ dev_priv->vdc_irq_mask |= _PSB_IRQ_MSVDX_FLAG;
++ struct psb_mmu_pd *pd;
+
-+ /*Clear MTX interrupt */
-+ REGIO_WRITE_FIELD_LITE(mtx_int, MSVDX_INTERRUPT_STATUS, CR_MTX_IRQ, 1);
-+ PSB_WMSVDX32(mtx_int, MSVDX_INTERRUPT_CLEAR);
++ down_read(&driver->sem);
++ pd = driver->default_pd;
++ up_read(&driver->sem);
++
++ return pd;
+}
+
-+void psb_irq_preinstall(struct drm_device *dev)
++/* Returns the physical address of the PD shared by sgx/msvdx */
++uint32_t psb_get_default_pd_addr(struct psb_mmu_driver * driver)
+{
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
-+ spin_lock(&dev_priv->irqmask_lock);
-+ PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
-+ PSB_WVDC32(0x00000000, PSB_INT_MASK_R);
-+ PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
-+ PSB_WSGX32(0x00000000, PSB_CR_EVENT_HOST_ENABLE);
-+ (void)PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE);
-+
-+ dev_priv->sgx_irq_mask = _PSB_CE_PIXELBE_END_RENDER |
-+ _PSB_CE_DPM_3D_MEM_FREE |
-+ _PSB_CE_TA_FINISHED |
-+ _PSB_CE_DPM_REACHED_MEM_THRESH |
-+ _PSB_CE_DPM_OUT_OF_MEMORY_GBL |
-+ _PSB_CE_DPM_OUT_OF_MEMORY_MT |
-+ _PSB_CE_TA_TERMINATE | _PSB_CE_SW_EVENT;
-+
-+ dev_priv->sgx2_irq_mask = _PSB_CE2_BIF_REQUESTER_FAULT;
-+
-+ dev_priv->vdc_irq_mask = _PSB_IRQ_SGX_FLAG | _PSB_IRQ_MSVDX_FLAG;
-+
-+ if (!drm_psb_disable_vsync)
-+ dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG |
-+ _PSB_VSYNC_PIPEB_FLAG;
++ struct psb_mmu_pd *pd;
+
-+ /*Clear MTX interrupt */
-+ {
-+ unsigned long mtx_int = 0;
-+ REGIO_WRITE_FIELD_LITE(mtx_int, MSVDX_INTERRUPT_STATUS,
-+ CR_MTX_IRQ, 1);
-+ PSB_WMSVDX32(mtx_int, MSVDX_INTERRUPT_CLEAR);
-+ }
-+ spin_unlock(&dev_priv->irqmask_lock);
++ pd = psb_mmu_get_default_pd(driver);
++ return ((page_to_pfn(pd->p) << PAGE_SHIFT));
+}
+
-+void psb_msvdx_irq_postinstall(struct drm_psb_private *dev_priv)
++void psb_mmu_driver_takedown(struct psb_mmu_driver *driver)
+{
-+ /* Enable Mtx Interupt to host */
-+ unsigned long enables = 0;
-+ PSB_DEBUG_GENERAL("Setting up MSVDX IRQs.....\n");
-+ REGIO_WRITE_FIELD_LITE(enables, MSVDX_INTERRUPT_STATUS, CR_MTX_IRQ, 1);
-+ PSB_WMSVDX32(enables, MSVDX_HOST_INTERRUPT_ENABLE);
++ psb_iowrite32(driver, driver->bif_ctrl, PSB_CR_BIF_CTRL);
++ psb_mmu_free_pagedir(driver->default_pd);
++ kfree(driver);
+}
+
-+int psb_irq_postinstall(struct drm_device *dev)
++struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
++ int trap_pagefaults,
++ int invalid_type,
++ atomic_t *msvdx_mmu_invaldc)
+{
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
-+ unsigned long irqflags;
++ struct psb_mmu_driver *driver;
+
-+ spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
-+ PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
-+ PSB_WSGX32(dev_priv->sgx2_irq_mask, PSB_CR_EVENT_HOST_ENABLE2);
-+ PSB_WSGX32(dev_priv->sgx_irq_mask, PSB_CR_EVENT_HOST_ENABLE);
-+ (void)PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE);
-+ /****MSVDX IRQ Setup...*****/
-+ /* Enable Mtx Interupt to host */
-+ {
-+ unsigned long enables = 0;
-+ PSB_DEBUG_GENERAL("Setting up MSVDX IRQs.....\n");
-+ REGIO_WRITE_FIELD_LITE(enables, MSVDX_INTERRUPT_STATUS,
-+ CR_MTX_IRQ, 1);
-+ PSB_WMSVDX32(enables, MSVDX_HOST_INTERRUPT_ENABLE);
-+ }
-+ dev_priv->irq_enabled = 1;
-+ spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
-+ return 0;
-+}
++ driver = (struct psb_mmu_driver *)kmalloc(sizeof(*driver), GFP_KERNEL);
+
-+void psb_irq_uninstall(struct drm_device *dev)
-+{
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
-+ unsigned long irqflags;
++ if (!driver)
++ return NULL;
+
-+ spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
++ driver->default_pd = psb_mmu_alloc_pd(driver, trap_pagefaults,
++ invalid_type);
++ if (!driver->default_pd)
++ goto out_err1;
+
-+ dev_priv->sgx_irq_mask = 0x00000000;
-+ dev_priv->sgx2_irq_mask = 0x00000000;
-+ dev_priv->vdc_irq_mask = 0x00000000;
++ spin_lock_init(&driver->lock);
++ init_rwsem(&driver->sem);
++ down_write(&driver->sem);
++ driver->register_map = registers;
++ atomic_set(&driver->needs_tlbflush, 1);
++ driver->msvdx_mmu_invaldc = msvdx_mmu_invaldc;
+
-+ PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
-+ PSB_WVDC32(0xFFFFFFFF, PSB_INT_MASK_R);
-+ PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
-+ PSB_WSGX32(dev_priv->sgx_irq_mask, PSB_CR_EVENT_HOST_ENABLE);
-+ PSB_WSGX32(dev_priv->sgx2_irq_mask, PSB_CR_EVENT_HOST_ENABLE2);
-+ wmb();
-+ PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R);
-+ PSB_WSGX32(PSB_RSGX32(PSB_CR_EVENT_STATUS), PSB_CR_EVENT_HOST_CLEAR);
-+ PSB_WSGX32(PSB_RSGX32(PSB_CR_EVENT_STATUS2), PSB_CR_EVENT_HOST_CLEAR2);
++ driver->bif_ctrl = psb_ioread32(driver, PSB_CR_BIF_CTRL);
++ psb_iowrite32(driver, driver->bif_ctrl | _PSB_CB_CTRL_CLEAR_FAULT,
++ PSB_CR_BIF_CTRL);
++ psb_iowrite32(driver, driver->bif_ctrl & ~_PSB_CB_CTRL_CLEAR_FAULT,
++ PSB_CR_BIF_CTRL);
+
-+ /****MSVDX IRQ Setup...*****/
-+ /* Clear interrupt enabled flag */
-+ PSB_WMSVDX32(0, MSVDX_HOST_INTERRUPT_ENABLE);
++ driver->has_clflush = 0;
+
-+ dev_priv->irq_enabled = 0;
-+ spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
++#if defined(CONFIG_X86)
++ if (boot_cpu_has(X86_FEATURE_CLFLSH)) {
++ uint32_t tfms, misc, cap0, cap4, clflush_size;
+
-+}
++ /*
++ * clflush size is determined at kernel setup for x86_64 but not for
++ * i386. We have to do it here.
++ */
+
-+void psb_2D_irq_off(struct drm_psb_private *dev_priv)
-+{
-+ unsigned long irqflags;
-+ uint32_t old_mask;
-+ uint32_t cleared_mask;
++ cpuid(0x00000001, &tfms, &misc, &cap0, &cap4);
++ clflush_size = ((misc >> 8) & 0xff) * 8;
++ driver->has_clflush = 1;
++ driver->clflush_add =
++ PAGE_SIZE * clflush_size / sizeof(uint32_t);
++ driver->clflush_mask = driver->clflush_add - 1;
++ driver->clflush_mask = ~driver->clflush_mask;
++ }
++#endif
+
-+ spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
-+ --dev_priv->irqen_count_2d;
-+ if (dev_priv->irq_enabled && dev_priv->irqen_count_2d == 0) {
-+
-+ old_mask = dev_priv->sgx_irq_mask;
-+ dev_priv->sgx_irq_mask &= ~_PSB_CE_TWOD_COMPLETE;
-+ PSB_WSGX32(dev_priv->sgx_irq_mask, PSB_CR_EVENT_HOST_ENABLE);
-+ (void)PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE);
++ up_write(&driver->sem);
++ return driver;
+
-+ cleared_mask = (old_mask ^ dev_priv->sgx_irq_mask) & old_mask;
-+ PSB_WSGX32(cleared_mask, PSB_CR_EVENT_HOST_CLEAR);
-+ (void)PSB_RSGX32(PSB_CR_EVENT_HOST_CLEAR);
-+ }
-+ spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
++ out_err1:
++ kfree(driver);
++ return NULL;
+}
+
-+void psb_2D_irq_on(struct drm_psb_private *dev_priv)
++#if defined(CONFIG_X86)
++static void psb_mmu_flush_ptes(struct psb_mmu_pd *pd, unsigned long address,
++ uint32_t num_pages, uint32_t desired_tile_stride,
++ uint32_t hw_tile_stride)
+{
-+ unsigned long irqflags;
++ struct psb_mmu_pt *pt;
++ uint32_t rows = 1;
++ uint32_t i;
++ unsigned long addr;
++ unsigned long end;
++ unsigned long next;
++ unsigned long add;
++ unsigned long row_add;
++ unsigned long clflush_add = pd->driver->clflush_add;
++ unsigned long clflush_mask = pd->driver->clflush_mask;
+
-+ spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
-+ if (dev_priv->irq_enabled && dev_priv->irqen_count_2d == 0) {
-+ dev_priv->sgx_irq_mask |= _PSB_CE_TWOD_COMPLETE;
-+ PSB_WSGX32(dev_priv->sgx_irq_mask, PSB_CR_EVENT_HOST_ENABLE);
-+ (void)PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE);
++ if (!pd->driver->has_clflush) {
++ drm_ttm_cache_flush();
++ return;
+ }
-+ ++dev_priv->irqen_count_2d;
-+ spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
-+}
+
-+static int psb_vblank_do_wait(struct drm_device *dev, unsigned int *sequence,
-+ atomic_t * counter)
-+{
-+ unsigned int cur_vblank;
-+ int ret = 0;
++ if (hw_tile_stride)
++ rows = num_pages / desired_tile_stride;
++ else
++ desired_tile_stride = num_pages;
+
-+ DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
-+ (((cur_vblank = atomic_read(counter))
-+ - *sequence) <= (1 << 23)));
++ add = desired_tile_stride << PAGE_SHIFT;
++ row_add = hw_tile_stride << PAGE_SHIFT;
++ mb();
++ for (i = 0; i < rows; ++i) {
+
-+ *sequence = cur_vblank;
++ addr = address;
++ end = addr + add;
+
-+ return ret;
-+}
++ do {
++ next = psb_pd_addr_end(addr, end);
++ pt = psb_mmu_pt_map_lock(pd, addr);
++ if (!pt)
++ continue;
++ do {
++ psb_clflush(&pt->v[psb_mmu_pt_index(addr)]);
++ } while (addr += clflush_add,
++ (addr & clflush_mask) < next);
+
-+int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence)
++ psb_mmu_pt_unmap_unlock(pt);
++ } while (addr = next, next != end);
++ address += row_add;
++ }
++ mb();
++}
++#else
++static void psb_mmu_flush_ptes(struct psb_mmu_pd *pd, unsigned long address,
++ uint32_t num_pages, uint32_t desired_tile_stride,
++ uint32_t hw_tile_stride)
+{
-+ int ret;
-+
-+ ret = psb_vblank_do_wait(dev, sequence, &dev->vbl_received);
-+ return ret;
++ drm_ttm_cache_flush();
+}
++#endif
+
-+int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence)
++void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
++ unsigned long address, uint32_t num_pages)
+{
-+ int ret;
++ struct psb_mmu_pt *pt;
++ unsigned long addr;
++ unsigned long end;
++ unsigned long next;
++ unsigned long f_address = address;
+
-+ ret = psb_vblank_do_wait(dev, sequence, &dev->vbl_received2);
-+ return ret;
-+}
++ down_read(&pd->driver->sem);
+
-+void psb_msvdx_irq_off(struct drm_psb_private *dev_priv)
-+{
-+ unsigned long irqflags;
++ addr = address;
++ end = addr + (num_pages << PAGE_SHIFT);
+
-+ spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
-+ if (dev_priv->irq_enabled) {
-+ dev_priv->vdc_irq_mask &= ~_PSB_IRQ_MSVDX_FLAG;
-+ PSB_WSGX32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
-+ (void)PSB_RSGX32(PSB_INT_ENABLE_R);
-+ }
-+ spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
-+}
++ do {
++ next = psb_pd_addr_end(addr, end);
++ pt = psb_mmu_pt_alloc_map_lock(pd, addr);
++ if (!pt)
++ goto out;
++ do {
++ psb_mmu_invalidate_pte(pt, addr);
++ --pt->count;
++ } while (addr += PAGE_SIZE, addr < next);
++ psb_mmu_pt_unmap_unlock(pt);
+
-+void psb_msvdx_irq_on(struct drm_psb_private *dev_priv)
-+{
-+ unsigned long irqflags;
++ } while (addr = next, next != end);
+
-+ spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
-+ if (dev_priv->irq_enabled) {
-+ dev_priv->vdc_irq_mask |= _PSB_IRQ_MSVDX_FLAG;
-+ PSB_WSGX32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
-+ (void)PSB_RSGX32(PSB_INT_ENABLE_R);
-+ }
-+ spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
-+}
-Index: linux-2.6.28/drivers/gpu/drm/psb/psb_mmu.c
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/psb/psb_mmu.c 2009-02-12 09:14:42.000000000 +0000
-@@ -0,0 +1,1037 @@
-+/**************************************************************************
-+ * Copyright (c) 2007, Intel Corporation.
-+ * All Rights Reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms and conditions of the GNU General Public License,
-+ * version 2, as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
-+ *
-+ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
-+ * develop this driver.
-+ *
-+ **************************************************************************/
-+#include "drmP.h"
-+#include "psb_drv.h"
-+#include "psb_reg.h"
++ out:
++ if (pd->hw_context != -1)
++ psb_mmu_flush_ptes(pd, f_address, num_pages, 1, 1);
+
-+/*
-+ * Code for the SGX MMU:
-+ */
++ up_read(&pd->driver->sem);
+
-+/*
-+ * clflush on one processor only:
-+ * clflush should apparently flush the cache line on all processors in an
-+ * SMP system.
-+ */
++ if (pd->hw_context != -1)
++ psb_mmu_flush(pd->driver);
+
-+/*
-+ * kmap atomic:
-+ * The usage of the slots must be completely encapsulated within a spinlock, and
-+ * no other functions that may be using the locks for other purposed may be
-+ * called from within the locked region.
-+ * Since the slots are per processor, this will guarantee that we are the only
-+ * user.
-+ */
++ return;
++}
+
-+/*
-+ * TODO: Inserting ptes from an interrupt handler:
-+ * This may be desirable for some SGX functionality where the GPU can fault in
-+ * needed pages. For that, we need to make an atomic insert_pages function, that
-+ * may fail.
-+ * If it fails, the caller need to insert the page using a workqueue function,
-+ * but on average it should be fast.
-+ */
++void psb_mmu_remove_pages(struct psb_mmu_pd *pd, unsigned long address,
++ uint32_t num_pages, uint32_t desired_tile_stride,
++ uint32_t hw_tile_stride)
++{
++ struct psb_mmu_pt *pt;
++ uint32_t rows = 1;
++ uint32_t i;
++ unsigned long addr;
++ unsigned long end;
++ unsigned long next;
++ unsigned long add;
++ unsigned long row_add;
++ unsigned long f_address = address;
+
-+struct psb_mmu_driver {
-+ /* protects driver- and pd structures. Always take in read mode
-+ * before taking the page table spinlock.
-+ */
-+ struct rw_semaphore sem;
++ if (hw_tile_stride)
++ rows = num_pages / desired_tile_stride;
++ else
++ desired_tile_stride = num_pages;
+
-+ /* protects page tables, directory tables and pt tables.
-+ * and pt structures.
-+ */
-+ spinlock_t lock;
++ add = desired_tile_stride << PAGE_SHIFT;
++ row_add = hw_tile_stride << PAGE_SHIFT;
+
-+ atomic_t needs_tlbflush;
-+ atomic_t *msvdx_mmu_invaldc;
-+ uint8_t __iomem *register_map;
-+ struct psb_mmu_pd *default_pd;
-+ uint32_t bif_ctrl;
-+ int has_clflush;
-+ int clflush_add;
-+ unsigned long clflush_mask;
-+};
++ down_read(&pd->driver->sem);
+
-+struct psb_mmu_pd;
++ /* Make sure we only need to flush this processor's cache */
+
-+struct psb_mmu_pt {
-+ struct psb_mmu_pd *pd;
-+ uint32_t index;
-+ uint32_t count;
-+ struct page *p;
-+ uint32_t *v;
-+};
++ for (i = 0; i < rows; ++i) {
+
-+struct psb_mmu_pd {
-+ struct psb_mmu_driver *driver;
-+ int hw_context;
-+ struct psb_mmu_pt **tables;
-+ struct page *p;
-+ struct page *dummy_pt;
-+ struct page *dummy_page;
-+ uint32_t pd_mask;
-+ uint32_t invalid_pde;
-+ uint32_t invalid_pte;
-+};
++ addr = address;
++ end = addr + add;
+
-+static inline uint32_t psb_mmu_pt_index(uint32_t offset)
-+{
-+ return (offset >> PSB_PTE_SHIFT) & 0x3FF;
-+}
-+static inline uint32_t psb_mmu_pd_index(uint32_t offset)
-+{
-+ return (offset >> PSB_PDE_SHIFT);
-+}
++ do {
++ next = psb_pd_addr_end(addr, end);
++ pt = psb_mmu_pt_map_lock(pd, addr);
++ if (!pt)
++ continue;
++ do {
++ psb_mmu_invalidate_pte(pt, addr);
++ --pt->count;
+
-+#if defined(CONFIG_X86)
-+static inline void psb_clflush(void *addr)
-+{
-+ __asm__ __volatile__("clflush (%0)\n"::"r"(addr):"memory");
-+}
++ } while (addr += PAGE_SIZE, addr < next);
++ psb_mmu_pt_unmap_unlock(pt);
+
-+static inline void psb_mmu_clflush(struct psb_mmu_driver *driver, void *addr)
-+{
-+ if (!driver->has_clflush)
-+ return;
++ } while (addr = next, next != end);
++ address += row_add;
++ }
++ if (pd->hw_context != -1)
++ psb_mmu_flush_ptes(pd, f_address, num_pages,
++ desired_tile_stride, hw_tile_stride);
+
-+ mb();
-+ psb_clflush(addr);
-+ mb();
-+}
-+#else
++ up_read(&pd->driver->sem);
+
-+static inline void psb_mmu_clflush(struct psb_mmu_driver *driver, void *addr)
-+{;
++ if (pd->hw_context != -1)
++ psb_mmu_flush(pd->driver);
+}
+
-+#endif
-+
-+static inline void psb_iowrite32(const struct psb_mmu_driver *d,
-+ uint32_t val, uint32_t offset)
++int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd, uint32_t start_pfn,
++ unsigned long address, uint32_t num_pages,
++ int type)
+{
-+ iowrite32(val, d->register_map + offset);
-+}
++ struct psb_mmu_pt *pt;
++ uint32_t pte;
++ unsigned long addr;
++ unsigned long end;
++ unsigned long next;
++ unsigned long f_address = address;
++ int ret = -ENOMEM;
+
-+static inline uint32_t psb_ioread32(const struct psb_mmu_driver *d,
-+ uint32_t offset)
-+{
-+ return ioread32(d->register_map + offset);
-+}
++ down_read(&pd->driver->sem);
+
-+static void psb_mmu_flush_pd_locked(struct psb_mmu_driver *driver, int force)
-+{
-+ if (atomic_read(&driver->needs_tlbflush) || force) {
-+ uint32_t val = psb_ioread32(driver, PSB_CR_BIF_CTRL);
-+ psb_iowrite32(driver, val | _PSB_CB_CTRL_INVALDC,
-+ PSB_CR_BIF_CTRL);
-+ wmb();
-+ psb_iowrite32(driver, val & ~_PSB_CB_CTRL_INVALDC,
-+ PSB_CR_BIF_CTRL);
-+ (void)psb_ioread32(driver, PSB_CR_BIF_CTRL);
-+ if (driver->msvdx_mmu_invaldc)
-+ atomic_set(driver->msvdx_mmu_invaldc, 1);
-+ }
-+ atomic_set(&driver->needs_tlbflush, 0);
-+}
++ addr = address;
++ end = addr + (num_pages << PAGE_SHIFT);
+
-+static void psb_mmu_flush_pd(struct psb_mmu_driver *driver, int force)
-+{
-+ down_write(&driver->sem);
-+ psb_mmu_flush_pd_locked(driver, force);
-+ up_write(&driver->sem);
-+}
++ do {
++ next = psb_pd_addr_end(addr, end);
++ pt = psb_mmu_pt_alloc_map_lock(pd, addr);
++ if (!pt) {
++ ret = -ENOMEM;
++ goto out;
++ }
++ do {
++ pte = psb_mmu_mask_pte(start_pfn++, type);
++ psb_mmu_set_pte(pt, addr, pte);
++ pt->count++;
++ } while (addr += PAGE_SIZE, addr < next);
++ psb_mmu_pt_unmap_unlock(pt);
+
-+void psb_mmu_flush(struct psb_mmu_driver *driver)
-+{
-+ uint32_t val;
++ } while (addr = next, next != end);
++ ret = 0;
+
-+ down_write(&driver->sem);
-+ val = psb_ioread32(driver, PSB_CR_BIF_CTRL);
-+ if (atomic_read(&driver->needs_tlbflush))
-+ psb_iowrite32(driver, val | _PSB_CB_CTRL_INVALDC,
-+ PSB_CR_BIF_CTRL);
-+ else
-+ psb_iowrite32(driver, val | _PSB_CB_CTRL_FLUSH,
-+ PSB_CR_BIF_CTRL);
-+ wmb();
-+ psb_iowrite32(driver,
-+ val & ~(_PSB_CB_CTRL_FLUSH | _PSB_CB_CTRL_INVALDC),
-+ PSB_CR_BIF_CTRL);
-+ (void)psb_ioread32(driver, PSB_CR_BIF_CTRL);
-+ atomic_set(&driver->needs_tlbflush, 0);
-+ if (driver->msvdx_mmu_invaldc)
-+ atomic_set(driver->msvdx_mmu_invaldc, 1);
-+ up_write(&driver->sem);
-+}
++ out:
++ if (pd->hw_context != -1)
++ psb_mmu_flush_ptes(pd, f_address, num_pages, 1, 1);
+
-+void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context)
-+{
-+ uint32_t offset = (hw_context == 0) ? PSB_CR_BIF_DIR_LIST_BASE0 :
-+ PSB_CR_BIF_DIR_LIST_BASE1 + hw_context * 4;
++ up_read(&pd->driver->sem);
+
-+ drm_ttm_cache_flush();
-+ down_write(&pd->driver->sem);
-+ psb_iowrite32(pd->driver, (page_to_pfn(pd->p) << PAGE_SHIFT), offset);
-+ wmb();
-+ psb_mmu_flush_pd_locked(pd->driver, 1);
-+ pd->hw_context = hw_context;
-+ up_write(&pd->driver->sem);
++ if (pd->hw_context != -1)
++ psb_mmu_flush(pd->driver);
+
++ return 0;
+}
+
-+static inline unsigned long psb_pd_addr_end(unsigned long addr,
-+ unsigned long end)
++int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
++ unsigned long address, uint32_t num_pages,
++ uint32_t desired_tile_stride, uint32_t hw_tile_stride,
++ int type)
+{
++ struct psb_mmu_pt *pt;
++ uint32_t rows = 1;
++ uint32_t i;
++ uint32_t pte;
++ unsigned long addr;
++ unsigned long end;
++ unsigned long next;
++ unsigned long add;
++ unsigned long row_add;
++ unsigned long f_address = address;
++ int ret = -ENOMEM;
+
-+ addr = (addr + PSB_PDE_MASK + 1) & ~PSB_PDE_MASK;
-+ return (addr < end) ? addr : end;
-+}
++ if (hw_tile_stride) {
++ if (num_pages % desired_tile_stride != 0)
++ return -EINVAL;
++ rows = num_pages / desired_tile_stride;
++ } else {
++ desired_tile_stride = num_pages;
++ }
+
-+static inline uint32_t psb_mmu_mask_pte(uint32_t pfn, int type)
-+{
-+ uint32_t mask = PSB_PTE_VALID;
++ add = desired_tile_stride << PAGE_SHIFT;
++ row_add = hw_tile_stride << PAGE_SHIFT;
+
-+ if (type & PSB_MMU_CACHED_MEMORY)
-+ mask |= PSB_PTE_CACHED;
-+ if (type & PSB_MMU_RO_MEMORY)
-+ mask |= PSB_PTE_RO;
-+ if (type & PSB_MMU_WO_MEMORY)
-+ mask |= PSB_PTE_WO;
++ down_read(&pd->driver->sem);
+
-+ return (pfn << PAGE_SHIFT) | mask;
-+}
++ for (i = 0; i < rows; ++i) {
+
-+struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
-+ int trap_pagefaults, int invalid_type)
-+{
-+ struct psb_mmu_pd *pd = kmalloc(sizeof(*pd), GFP_KERNEL);
-+ uint32_t *v;
-+ int i;
++ addr = address;
++ end = addr + add;
+
-+ if (!pd)
-+ return NULL;
++ do {
++ next = psb_pd_addr_end(addr, end);
++ pt = psb_mmu_pt_alloc_map_lock(pd, addr);
++ if (!pt)
++ goto out;
++ do {
++ pte = psb_mmu_mask_pte(page_to_pfn(*pages++),
++ type);
++ psb_mmu_set_pte(pt, addr, pte);
++ pt->count++;
++ } while (addr += PAGE_SIZE, addr < next);
++ psb_mmu_pt_unmap_unlock(pt);
+
-+ pd->p = alloc_page(GFP_DMA32);
-+ if (!pd->p)
-+ goto out_err1;
-+ pd->dummy_pt = alloc_page(GFP_DMA32);
-+ if (!pd->dummy_pt)
-+ goto out_err2;
-+ pd->dummy_page = alloc_page(GFP_DMA32);
-+ if (!pd->dummy_page)
-+ goto out_err3;
++ } while (addr = next, next != end);
+
-+ if (!trap_pagefaults) {
-+ pd->invalid_pde = psb_mmu_mask_pte(page_to_pfn(pd->dummy_pt),
-+ invalid_type |
-+ PSB_MMU_CACHED_MEMORY);
-+ pd->invalid_pte = psb_mmu_mask_pte(page_to_pfn(pd->dummy_page),
-+ invalid_type |
-+ PSB_MMU_CACHED_MEMORY);
-+ } else {
-+ pd->invalid_pde = 0;
-+ pd->invalid_pte = 0;
++ address += row_add;
+ }
++ ret = 0;
++ out:
++ if (pd->hw_context != -1)
++ psb_mmu_flush_ptes(pd, f_address, num_pages,
++ desired_tile_stride, hw_tile_stride);
+
-+ v = kmap(pd->dummy_pt);
-+ for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i) {
-+ v[i] = pd->invalid_pte;
-+ }
-+ kunmap(pd->dummy_pt);
++ up_read(&pd->driver->sem);
+
-+ v = kmap(pd->p);
-+ for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i) {
-+ v[i] = pd->invalid_pde;
-+ }
-+ kunmap(pd->p);
++ if (pd->hw_context != -1)
++ psb_mmu_flush(pd->driver);
+
-+ clear_page(kmap(pd->dummy_page));
-+ kunmap(pd->dummy_page);
++ return 0;
++}
+
-+ pd->tables = vmalloc_user(sizeof(struct psb_mmu_pt *) * 1024);
-+ if (!pd->tables)
-+ goto out_err4;
-+
-+ pd->hw_context = -1;
-+ pd->pd_mask = PSB_PTE_VALID;
-+ pd->driver = driver;
-+
-+ return pd;
-+
-+ out_err4:
-+ __free_page(pd->dummy_page);
-+ out_err3:
-+ __free_page(pd->dummy_pt);
-+ out_err2:
-+ __free_page(pd->p);
-+ out_err1:
-+ kfree(pd);
-+ return NULL;
++void psb_mmu_enable_requestor(struct psb_mmu_driver *driver, uint32_t mask)
++{
++ mask &= _PSB_MMU_ER_MASK;
++ psb_iowrite32(driver, psb_ioread32(driver, PSB_CR_BIF_CTRL) & ~mask,
++ PSB_CR_BIF_CTRL);
++ (void)psb_ioread32(driver, PSB_CR_BIF_CTRL);
+}
+
-+void psb_mmu_free_pt(struct psb_mmu_pt *pt)
++void psb_mmu_disable_requestor(struct psb_mmu_driver *driver, uint32_t mask)
+{
-+ __free_page(pt->p);
-+ kfree(pt);
++ mask &= _PSB_MMU_ER_MASK;
++ psb_iowrite32(driver, psb_ioread32(driver, PSB_CR_BIF_CTRL) | mask,
++ PSB_CR_BIF_CTRL);
++ (void)psb_ioread32(driver, PSB_CR_BIF_CTRL);
+}
+
-+void psb_mmu_free_pagedir(struct psb_mmu_pd *pd)
++int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
++ unsigned long *pfn)
+{
-+ struct psb_mmu_driver *driver = pd->driver;
++ int ret;
+ struct psb_mmu_pt *pt;
-+ int i;
++ uint32_t tmp;
++ spinlock_t *lock = &pd->driver->lock;
+
-+ down_write(&driver->sem);
-+ if (pd->hw_context != -1) {
-+ psb_iowrite32(driver, 0,
-+ PSB_CR_BIF_DIR_LIST_BASE0 + pd->hw_context * 4);
-+ psb_mmu_flush_pd_locked(driver, 1);
-+ }
++ down_read(&pd->driver->sem);
++ pt = psb_mmu_pt_map_lock(pd, virtual);
++ if (!pt) {
++ uint32_t *v;
+
-+ /* Should take the spinlock here, but we don't need to do that
-+ since we have the semaphore in write mode. */
++ spin_lock(lock);
++ v = kmap_atomic(pd->p, KM_USER0);
++ tmp = v[psb_mmu_pd_index(virtual)];
++ kunmap_atomic(v, KM_USER0);
++ spin_unlock(lock);
+
-+ for (i = 0; i < 1024; ++i) {
-+ pt = pd->tables[i];
-+ if (pt)
-+ psb_mmu_free_pt(pt);
++ if (tmp != pd->invalid_pde || !(tmp & PSB_PTE_VALID) ||
++ !(pd->invalid_pte & PSB_PTE_VALID)) {
++ ret = -EINVAL;
++ goto out;
++ }
++ ret = 0;
++ *pfn = pd->invalid_pte >> PAGE_SHIFT;
++ goto out;
+ }
-+
-+ vfree(pd->tables);
-+ __free_page(pd->dummy_page);
-+ __free_page(pd->dummy_pt);
-+ __free_page(pd->p);
-+ kfree(pd);
-+ up_write(&driver->sem);
++ tmp = pt->v[psb_mmu_pt_index(virtual)];
++ if (!(tmp & PSB_PTE_VALID)) {
++ ret = -EINVAL;
++ } else {
++ ret = 0;
++ *pfn = tmp >> PAGE_SHIFT;
++ }
++ psb_mmu_pt_unmap_unlock(pt);
++ out:
++ up_read(&pd->driver->sem);
++ return ret;
+}
+
-+static struct psb_mmu_pt *psb_mmu_alloc_pt(struct psb_mmu_pd *pd)
++void psb_mmu_test(struct psb_mmu_driver *driver, uint32_t offset)
+{
-+ struct psb_mmu_pt *pt = kmalloc(sizeof(*pt), GFP_KERNEL);
-+ void *v;
-+ uint32_t clflush_add = pd->driver->clflush_add >> PAGE_SHIFT;
-+ uint32_t clflush_count = PAGE_SIZE / clflush_add;
-+ spinlock_t *lock = &pd->driver->lock;
-+ uint8_t *clf;
-+ uint32_t *ptes;
-+ int i;
-+
-+ if (!pt)
-+ return NULL;
++ struct page *p;
++ unsigned long pfn;
++ int ret = 0;
++ struct psb_mmu_pd *pd;
++ uint32_t *v;
++ uint32_t *vmmu;
+
-+ pt->p = alloc_page(GFP_DMA32);
-+ if (!pt->p) {
-+ kfree(pt);
-+ return NULL;
++ pd = driver->default_pd;
++ if (!pd) {
++ printk(KERN_WARNING "Could not get default pd\n");
+ }
+
-+ spin_lock(lock);
-+
-+ v = kmap_atomic(pt->p, KM_USER0);
-+ clf = (uint8_t *) v;
-+ ptes = (uint32_t *) v;
-+ for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i) {
-+ *ptes++ = pd->invalid_pte;
-+ }
++ p = alloc_page(GFP_DMA32);
+
-+#if defined(CONFIG_X86)
-+ if (pd->driver->has_clflush && pd->hw_context != -1) {
-+ mb();
-+ for (i = 0; i < clflush_count; ++i) {
-+ psb_clflush(clf);
-+ clf += clflush_add;
-+ }
-+ mb();
++ if (!p) {
++ printk(KERN_WARNING "Failed allocating page\n");
++ return;
+ }
-+#endif
-+ kunmap_atomic(v, KM_USER0);
-+ spin_unlock(lock);
-+
-+ pt->count = 0;
-+ pt->pd = pd;
-+ pt->index = 0;
-+
-+ return pt;
-+}
-+
-+struct psb_mmu_pt *psb_mmu_pt_alloc_map_lock(struct psb_mmu_pd *pd,
-+ unsigned long addr)
-+{
-+ uint32_t index = psb_mmu_pd_index(addr);
-+ struct psb_mmu_pt *pt;
-+ volatile uint32_t *v;
-+ spinlock_t *lock = &pd->driver->lock;
-+
-+ spin_lock(lock);
-+ pt = pd->tables[index];
-+ while (!pt) {
-+ spin_unlock(lock);
-+ pt = psb_mmu_alloc_pt(pd);
-+ if (!pt)
-+ return NULL;
-+ spin_lock(lock);
+
-+ if (pd->tables[index]) {
-+ spin_unlock(lock);
-+ psb_mmu_free_pt(pt);
-+ spin_lock(lock);
-+ pt = pd->tables[index];
-+ continue;
-+ }
++ v = kmap(p);
++ memset(v, 0x67, PAGE_SIZE);
+
-+ v = kmap_atomic(pd->p, KM_USER0);
-+ pd->tables[index] = pt;
-+ v[index] = (page_to_pfn(pt->p) << 12) | pd->pd_mask;
-+ pt->index = index;
-+ kunmap_atomic((void *)v, KM_USER0);
++ pfn = (offset >> PAGE_SHIFT);
+
-+ if (pd->hw_context != -1) {
-+ psb_mmu_clflush(pd->driver, (void *)&v[index]);
-+ atomic_set(&pd->driver->needs_tlbflush, 1);
-+ }
++ ret = psb_mmu_insert_pages(pd, &p, pfn << PAGE_SHIFT, 1, 0, 0,
++ PSB_MMU_CACHED_MEMORY);
++ if (ret) {
++ printk(KERN_WARNING "Failed inserting mmu page\n");
++ goto out_err1;
+ }
-+ pt->v = kmap_atomic(pt->p, KM_USER0);
-+ return pt;
-+}
+
-+static struct psb_mmu_pt *psb_mmu_pt_map_lock(struct psb_mmu_pd *pd,
-+ unsigned long addr)
-+{
-+ uint32_t index = psb_mmu_pd_index(addr);
-+ struct psb_mmu_pt *pt;
-+ spinlock_t *lock = &pd->driver->lock;
++ /* Ioremap the page through the GART aperture */
+
-+ spin_lock(lock);
-+ pt = pd->tables[index];
-+ if (!pt) {
-+ spin_unlock(lock);
-+ return NULL;
++ vmmu = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE);
++ if (!vmmu) {
++ printk(KERN_WARNING "Failed ioremapping page\n");
++ goto out_err2;
+ }
-+ pt->v = kmap_atomic(pt->p, KM_USER0);
-+ return pt;
-+}
-+
-+static void psb_mmu_pt_unmap_unlock(struct psb_mmu_pt *pt)
-+{
-+ struct psb_mmu_pd *pd = pt->pd;
-+ volatile uint32_t *v;
+
-+ kunmap_atomic(pt->v, KM_USER0);
-+ if (pt->count == 0) {
-+ v = kmap_atomic(pd->p, KM_USER0);
-+ v[pt->index] = pd->invalid_pde;
-+ pd->tables[pt->index] = NULL;
++ /* Read from the page with mmu disabled. */
++ printk(KERN_INFO "Page first dword is 0x%08x\n", ioread32(vmmu));
+
-+ if (pd->hw_context != -1) {
-+ psb_mmu_clflush(pd->driver, (void *)&v[pt->index]);
-+ atomic_set(&pd->driver->needs_tlbflush, 1);
-+ }
-+ kunmap_atomic(pt->v, KM_USER0);
-+ spin_unlock(&pd->driver->lock);
-+ psb_mmu_free_pt(pt);
-+ return;
-+ }
-+ spin_unlock(&pd->driver->lock);
-+}
++ /* Enable the mmu for host accesses and read again. */
++ psb_mmu_enable_requestor(driver, _PSB_MMU_ER_HOST);
+
-+static inline void psb_mmu_set_pte(struct psb_mmu_pt *pt, unsigned long addr,
-+ uint32_t pte)
-+{
-+ pt->v[psb_mmu_pt_index(addr)] = pte;
-+}
++ printk(KERN_INFO "MMU Page first dword is (0x67676767) 0x%08x\n",
++ ioread32(vmmu));
++ *v = 0x15243705;
++ printk(KERN_INFO "MMU Page new dword is (0x15243705) 0x%08x\n",
++ ioread32(vmmu));
++ iowrite32(0x16243355, vmmu);
++ (void)ioread32(vmmu);
++ printk(KERN_INFO "Page new dword is (0x16243355) 0x%08x\n", *v);
+
-+static inline void psb_mmu_invalidate_pte(struct psb_mmu_pt *pt,
-+ unsigned long addr)
-+{
-+ pt->v[psb_mmu_pt_index(addr)] = pt->pd->invalid_pte;
-+}
++ printk(KERN_INFO "Int stat is 0x%08x\n",
++ psb_ioread32(driver, PSB_CR_BIF_INT_STAT));
++ printk(KERN_INFO "Fault is 0x%08x\n",
++ psb_ioread32(driver, PSB_CR_BIF_FAULT));
+
-+#if 0
-+static uint32_t psb_mmu_check_pte_locked(struct psb_mmu_pd *pd,
-+ uint32_t mmu_offset)
-+{
-+ uint32_t *v;
-+ uint32_t pfn;
-+
-+ v = kmap_atomic(pd->p, KM_USER0);
-+ if (!v) {
-+ printk(KERN_INFO "Could not kmap pde page.\n");
-+ return 0;
-+ }
-+ pfn = v[psb_mmu_pd_index(mmu_offset)];
-+ // printk(KERN_INFO "pde is 0x%08x\n",pfn);
-+ kunmap_atomic(v, KM_USER0);
-+ if (((pfn & 0x0F) != PSB_PTE_VALID)) {
-+ printk(KERN_INFO "Strange pde at 0x%08x: 0x%08x.\n",
-+ mmu_offset, pfn);
-+ }
-+ v = ioremap(pfn & 0xFFFFF000, 4096);
-+ if (!v) {
-+ printk(KERN_INFO "Could not kmap pte page.\n");
-+ return 0;
-+ }
-+ pfn = v[psb_mmu_pt_index(mmu_offset)];
-+ // printk(KERN_INFO "pte is 0x%08x\n",pfn);
-+ iounmap(v);
-+ if (((pfn & 0x0F) != PSB_PTE_VALID)) {
-+ printk(KERN_INFO "Strange pte at 0x%08x: 0x%08x.\n",
-+ mmu_offset, pfn);
-+ }
-+ return pfn >> PAGE_SHIFT;
-+}
-+
-+static void psb_mmu_check_mirrored_gtt(struct psb_mmu_pd *pd,
-+ uint32_t mmu_offset, uint32_t gtt_pages)
-+{
-+ uint32_t start;
-+ uint32_t next;
-+
-+ printk(KERN_INFO "Checking mirrored gtt 0x%08x %d\n",
-+ mmu_offset, gtt_pages);
-+ down_read(&pd->driver->sem);
-+ start = psb_mmu_check_pte_locked(pd, mmu_offset);
-+ mmu_offset += PAGE_SIZE;
-+ gtt_pages -= 1;
-+ while (gtt_pages--) {
-+ next = psb_mmu_check_pte_locked(pd, mmu_offset);
-+ if (next != start + 1) {
-+ printk(KERN_INFO "Ptes out of order: 0x%08x, 0x%08x.\n",
-+ start, next);
-+ }
-+ start = next;
-+ mmu_offset += PAGE_SIZE;
-+ }
-+ up_read(&pd->driver->sem);
++ /* Disable MMU for host accesses and clear page fault register */
++ psb_mmu_disable_requestor(driver, _PSB_MMU_ER_HOST);
++ iounmap(vmmu);
++ out_err2:
++ psb_mmu_remove_pages(pd, pfn << PAGE_SHIFT, 1, 0, 0);
++ out_err1:
++ kunmap(p);
++ __free_page(p);
+}
+Index: linux-2.6.28/drivers/gpu/drm/psb/psb_msvdx.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.28/drivers/gpu/drm/psb/psb_msvdx.c 2009-02-12 09:14:42.000000000 +0000
+@@ -0,0 +1,678 @@
++/**
++ * file psb_msvdx.c
++ * MSVDX I/O operations and IRQ handling
++ *
++ */
+
-+#endif
-+
-+void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd,
-+ uint32_t mmu_offset, uint32_t gtt_start,
-+ uint32_t gtt_pages)
-+{
-+ uint32_t *v;
-+ uint32_t start = psb_mmu_pd_index(mmu_offset);
-+ struct psb_mmu_driver *driver = pd->driver;
-+
-+ down_read(&driver->sem);
-+ spin_lock(&driver->lock);
-+
-+ v = kmap_atomic(pd->p, KM_USER0);
-+ v += start;
++/**************************************************************************
++ *
++ * Copyright (c) 2007 Intel Corporation, Hillsboro, OR, USA
++ * Copyright (c) Imagination Technologies Limited, UK
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
++ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
++ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ **************************************************************************/
+
-+ while (gtt_pages--) {
-+ *v++ = gtt_start | pd->pd_mask;
-+ gtt_start += PAGE_SIZE;
-+ }
++#include "drmP.h"
++#include "drm_os_linux.h"
++#include "psb_drv.h"
++#include "psb_drm.h"
++#include "psb_msvdx.h"
+
-+ drm_ttm_cache_flush();
-+ kunmap_atomic(v, KM_USER0);
-+ spin_unlock(&driver->lock);
++#include <asm/io.h>
++#include <linux/delay.h>
+
-+ if (pd->hw_context != -1)
-+ atomic_set(&pd->driver->needs_tlbflush, 1);
++#ifndef list_first_entry
++#define list_first_entry(ptr, type, member) \
++ list_entry((ptr)->next, type, member)
++#endif
+
-+ up_read(&pd->driver->sem);
-+ psb_mmu_flush_pd(pd->driver, 0);
-+}
++static int psb_msvdx_send (struct drm_device *dev, void *cmd,
++ unsigned long cmd_size);
+
-+struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver *driver)
++int
++psb_msvdx_dequeue_send (struct drm_device *dev)
+{
-+ struct psb_mmu_pd *pd;
-+
-+ down_read(&driver->sem);
-+ pd = driver->default_pd;
-+ up_read(&driver->sem);
++ struct drm_psb_private *dev_priv = dev->dev_private;
++ struct psb_msvdx_cmd_queue *msvdx_cmd = NULL;
++ int ret = 0;
+
-+ return pd;
++ if (list_empty (&dev_priv->msvdx_queue))
++ {
++ PSB_DEBUG_GENERAL ("MSVDXQUE: msvdx list empty.\n");
++ dev_priv->msvdx_busy = 0;
++ return -EINVAL;
++ }
++ msvdx_cmd =
++ list_first_entry (&dev_priv->msvdx_queue, struct psb_msvdx_cmd_queue,
++ head);
++ PSB_DEBUG_GENERAL ("MSVDXQUE: Queue has id %08x\n", msvdx_cmd->sequence);
++ ret = psb_msvdx_send (dev, msvdx_cmd->cmd, msvdx_cmd->cmd_size);
++ if (ret)
++ {
++ PSB_DEBUG_GENERAL ("MSVDXQUE: psb_msvdx_send failed\n");
++ ret = -EINVAL;
++ }
++ list_del (&msvdx_cmd->head);
++ kfree (msvdx_cmd->cmd);
++ drm_free (msvdx_cmd, sizeof (struct psb_msvdx_cmd_queue), DRM_MEM_DRIVER);
++ return ret;
+}
+
-+/* Returns the physical address of the PD shared by sgx/msvdx */
-+uint32_t psb_get_default_pd_addr(struct psb_mmu_driver * driver)
++int
++psb_msvdx_map_command (struct drm_device *dev,
++ struct drm_buffer_object *cmd_buffer,
++ unsigned long cmd_offset, unsigned long cmd_size,
++ void **msvdx_cmd, uint32_t sequence, int copy_cmd)
+{
-+ struct psb_mmu_pd *pd;
++ struct drm_psb_private *dev_priv = dev->dev_private;
++ int ret = 0;
++ unsigned long cmd_page_offset = cmd_offset & ~PAGE_MASK;
++ unsigned long cmd_size_remaining;
++ struct drm_bo_kmap_obj cmd_kmap;
++ void *cmd, *tmp, *cmd_start;
++ int is_iomem;
+
-+ pd = psb_mmu_get_default_pd(driver);
-+ return ((page_to_pfn(pd->p) << PAGE_SHIFT));
-+}
++ /* command buffers may not exceed page boundary */
++ if (cmd_size + cmd_page_offset > PAGE_SIZE)
++ return -EINVAL;
+
-+void psb_mmu_driver_takedown(struct psb_mmu_driver *driver)
-+{
-+ psb_iowrite32(driver, driver->bif_ctrl, PSB_CR_BIF_CTRL);
-+ psb_mmu_free_pagedir(driver->default_pd);
-+ kfree(driver);
-+}
++ ret = drm_bo_kmap (cmd_buffer, cmd_offset >> PAGE_SHIFT, 2, &cmd_kmap);
+
-+struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
-+ int trap_pagefaults,
-+ int invalid_type,
-+ atomic_t *msvdx_mmu_invaldc)
-+{
-+ struct psb_mmu_driver *driver;
++ if (ret)
++ {
++ PSB_DEBUG_GENERAL ("MSVDXQUE:ret:%d\n", ret);
++ return ret;
++ }
+
-+ driver = (struct psb_mmu_driver *)kmalloc(sizeof(*driver), GFP_KERNEL);
++ cmd_start =
++ (void *) drm_bmo_virtual (&cmd_kmap, &is_iomem) + cmd_page_offset;
++ cmd = cmd_start;
++ cmd_size_remaining = cmd_size;
+
-+ if (!driver)
-+ return NULL;
++ while (cmd_size_remaining > 0)
++ {
++ uint32_t mmu_ptd;
++ uint32_t cur_cmd_size = MEMIO_READ_FIELD (cmd, FWRK_GENMSG_SIZE);
++ uint32_t cur_cmd_id = MEMIO_READ_FIELD (cmd, FWRK_GENMSG_ID);
++ PSB_DEBUG_GENERAL
++ ("cmd start at %08x cur_cmd_size = %d cur_cmd_id = %02x fence = %08x\n",
++ (uint32_t) cmd, cur_cmd_size, cur_cmd_id, sequence);
++ if ((cur_cmd_size % sizeof (uint32_t))
++ || (cur_cmd_size > cmd_size_remaining))
++ {
++ ret = -EINVAL;
++ PSB_DEBUG_GENERAL ("MSVDX: ret:%d\n", ret);
++ goto out;
++ }
+
-+ driver->default_pd = psb_mmu_alloc_pd(driver, trap_pagefaults,
-+ invalid_type);
-+ if (!driver->default_pd)
-+ goto out_err1;
++ switch (cur_cmd_id)
++ {
++ case VA_MSGID_RENDER:
++ /* Fence ID */
++ MEMIO_WRITE_FIELD (cmd, FW_VA_RENDER_FENCE_VALUE, sequence);
+
-+ spin_lock_init(&driver->lock);
-+ init_rwsem(&driver->sem);
-+ down_write(&driver->sem);
-+ driver->register_map = registers;
-+ atomic_set(&driver->needs_tlbflush, 1);
-+ driver->msvdx_mmu_invaldc = msvdx_mmu_invaldc;
++ mmu_ptd = psb_get_default_pd_addr (dev_priv->mmu);
++ if (atomic_cmpxchg(&dev_priv->msvdx_mmu_invaldc, 1, 0) == 1)
++ {
++ mmu_ptd |= 1;
++ PSB_DEBUG_GENERAL ("MSVDX: Setting MMU invalidate flag\n");
++ }
++ /* PTD */
++ MEMIO_WRITE_FIELD (cmd, FW_VA_RENDER_MMUPTD, mmu_ptd);
++ break;
+
-+ driver->bif_ctrl = psb_ioread32(driver, PSB_CR_BIF_CTRL);
-+ psb_iowrite32(driver, driver->bif_ctrl | _PSB_CB_CTRL_CLEAR_FAULT,
-+ PSB_CR_BIF_CTRL);
-+ psb_iowrite32(driver, driver->bif_ctrl & ~_PSB_CB_CTRL_CLEAR_FAULT,
-+ PSB_CR_BIF_CTRL);
-+
-+ driver->has_clflush = 0;
-+
-+#if defined(CONFIG_X86)
-+ if (boot_cpu_has(X86_FEATURE_CLFLSH)) {
-+ uint32_t tfms, misc, cap0, cap4, clflush_size;
++ default:
++ /* Msg not supported */
++ ret = -EINVAL;
++ PSB_DEBUG_GENERAL ("MSVDX: ret:%d\n", ret);
++ goto out;
++ }
+
-+ /*
-+ * clflush size is determined at kernel setup for x86_64 but not for
-+ * i386. We have to do it here.
-+ */
++ cmd += cur_cmd_size;
++ cmd_size_remaining -= cur_cmd_size;
++ }
+
-+ cpuid(0x00000001, &tfms, &misc, &cap0, &cap4);
-+ clflush_size = ((misc >> 8) & 0xff) * 8;
-+ driver->has_clflush = 1;
-+ driver->clflush_add =
-+ PAGE_SIZE * clflush_size / sizeof(uint32_t);
-+ driver->clflush_mask = driver->clflush_add - 1;
-+ driver->clflush_mask = ~driver->clflush_mask;
++ if (copy_cmd)
++ {
++ PSB_DEBUG_GENERAL
++ ("MSVDXQUE: psb_msvdx_map_command copying command...\n");
++ tmp = drm_calloc (1, cmd_size, DRM_MEM_DRIVER);
++ if (tmp == NULL)
++ {
++ ret = -ENOMEM;
++ PSB_DEBUG_GENERAL ("MSVDX: ret:%d\n", ret);
++ goto out;
+ }
-+#endif
++ memcpy (tmp, cmd_start, cmd_size);
++ *msvdx_cmd = tmp;
++ }
++ else
++ {
++ PSB_DEBUG_GENERAL
++ ("MSVDXQUE: psb_msvdx_map_command did NOT copy command...\n");
++ ret = psb_msvdx_send (dev, cmd_start, cmd_size);
++ if (ret)
++ {
++ PSB_DEBUG_GENERAL ("MSVDXQUE: psb_msvdx_send failed\n");
++ ret = -EINVAL;
++ }
++ }
+
-+ up_write(&driver->sem);
-+ return driver;
++out:
++ drm_bo_kunmap (&cmd_kmap);
+
-+ out_err1:
-+ kfree(driver);
-+ return NULL;
++ return ret;
+}
+
-+#if defined(CONFIG_X86)
-+static void psb_mmu_flush_ptes(struct psb_mmu_pd *pd, unsigned long address,
-+ uint32_t num_pages, uint32_t desired_tile_stride,
-+ uint32_t hw_tile_stride)
++int
++psb_submit_video_cmdbuf (struct drm_device *dev,
++ struct drm_buffer_object *cmd_buffer,
++ unsigned long cmd_offset, unsigned long cmd_size,
++ struct drm_fence_object *fence)
+{
-+ struct psb_mmu_pt *pt;
-+ uint32_t rows = 1;
-+ uint32_t i;
-+ unsigned long addr;
-+ unsigned long end;
-+ unsigned long next;
-+ unsigned long add;
-+ unsigned long row_add;
-+ unsigned long clflush_add = pd->driver->clflush_add;
-+ unsigned long clflush_mask = pd->driver->clflush_mask;
++ struct drm_psb_private *dev_priv = dev->dev_private;
++ uint32_t sequence = fence->sequence;
++ unsigned long irq_flags;
++ int ret = 0;
+
-+ if (!pd->driver->has_clflush) {
-+ drm_ttm_cache_flush();
-+ return;
-+ }
++ mutex_lock (&dev_priv->msvdx_mutex);
++ psb_schedule_watchdog (dev_priv);
+
-+ if (hw_tile_stride)
-+ rows = num_pages / desired_tile_stride;
-+ else
-+ desired_tile_stride = num_pages;
++ spin_lock_irqsave (&dev_priv->msvdx_lock, irq_flags);
++ if (dev_priv->msvdx_needs_reset)
++ {
++ spin_unlock_irqrestore (&dev_priv->msvdx_lock, irq_flags);
++ PSB_DEBUG_GENERAL ("MSVDX: Needs reset\n");
++ if (psb_msvdx_reset (dev_priv))
++ {
++ mutex_unlock (&dev_priv->msvdx_mutex);
++ ret = -EBUSY;
++ PSB_DEBUG_GENERAL ("MSVDX: Reset failed\n");
++ return ret;
++ }
++ PSB_DEBUG_GENERAL ("MSVDX: Reset ok\n");
++ dev_priv->msvdx_needs_reset = 0;
++ dev_priv->msvdx_busy = 0;
++ dev_priv->msvdx_start_idle = 0;
+
-+ add = desired_tile_stride << PAGE_SHIFT;
-+ row_add = hw_tile_stride << PAGE_SHIFT;
-+ mb();
-+ for (i = 0; i < rows; ++i) {
++ psb_msvdx_init (dev);
++ psb_msvdx_irq_preinstall (dev_priv);
++ psb_msvdx_irq_postinstall (dev_priv);
++ PSB_DEBUG_GENERAL ("MSVDX: Init ok\n");
++ spin_lock_irqsave (&dev_priv->msvdx_lock, irq_flags);
++ }
+
-+ addr = address;
-+ end = addr + add;
++ if (!dev_priv->msvdx_busy)
++ {
++ dev_priv->msvdx_busy = 1;
++ spin_unlock_irqrestore (&dev_priv->msvdx_lock, irq_flags);
++ PSB_DEBUG_GENERAL
++ ("MSVDXQUE: nothing in the queue sending sequence:%08x..\n",
++ sequence);
++ ret =
++ psb_msvdx_map_command (dev, cmd_buffer, cmd_offset, cmd_size,
++ NULL, sequence, 0);
++ if (ret)
++ {
++ mutex_unlock (&dev_priv->msvdx_mutex);
++ PSB_DEBUG_GENERAL ("MSVDXQUE: Failed to extract cmd...\n");
++ return ret;
++ }
++ }
++ else
++ {
++ struct psb_msvdx_cmd_queue *msvdx_cmd;
++ void *cmd = NULL;
+
-+ do {
-+ next = psb_pd_addr_end(addr, end);
-+ pt = psb_mmu_pt_map_lock(pd, addr);
-+ if (!pt)
-+ continue;
-+ do {
-+ psb_clflush(&pt->v[psb_mmu_pt_index(addr)]);
-+ } while (addr += clflush_add,
-+ (addr & clflush_mask) < next);
++ spin_unlock_irqrestore (&dev_priv->msvdx_lock, irq_flags);
++ /*queue the command to be sent when the h/w is ready */
++ PSB_DEBUG_GENERAL ("MSVDXQUE: queueing sequence:%08x..\n", sequence);
++ msvdx_cmd =
++ drm_calloc (1, sizeof (struct psb_msvdx_cmd_queue), DRM_MEM_DRIVER);
++ if (msvdx_cmd == NULL)
++ {
++ mutex_unlock (&dev_priv->msvdx_mutex);
++ PSB_DEBUG_GENERAL ("MSVDXQUE: Out of memory...\n");
++ return -ENOMEM;
++ }
+
-+ psb_mmu_pt_unmap_unlock(pt);
-+ } while (addr = next, next != end);
-+ address += row_add;
++ ret =
++ psb_msvdx_map_command (dev, cmd_buffer, cmd_offset, cmd_size,
++ &cmd, sequence, 1);
++ if (ret)
++ {
++ mutex_unlock (&dev_priv->msvdx_mutex);
++ PSB_DEBUG_GENERAL ("MSVDXQUE: Failed to extract cmd...\n");
++ drm_free (msvdx_cmd, sizeof (struct psb_msvdx_cmd_queue),
++ DRM_MEM_DRIVER);
++ return ret;
+ }
-+ mb();
++ msvdx_cmd->cmd = cmd;
++ msvdx_cmd->cmd_size = cmd_size;
++ msvdx_cmd->sequence = sequence;
++ spin_lock_irqsave (&dev_priv->msvdx_lock, irq_flags);
++ list_add_tail (&msvdx_cmd->head, &dev_priv->msvdx_queue);
++ if (!dev_priv->msvdx_busy)
++ {
++ dev_priv->msvdx_busy = 1;
++ PSB_DEBUG_GENERAL ("MSVDXQUE: Need immediate dequeue\n");
++ psb_msvdx_dequeue_send (dev);
++ }
++ spin_unlock_irqrestore (&dev_priv->msvdx_lock, irq_flags);
++ }
++ mutex_unlock (&dev_priv->msvdx_mutex);
++ return ret;
+}
-+#else
-+static void psb_mmu_flush_ptes(struct psb_mmu_pd *pd, unsigned long address,
-+ uint32_t num_pages, uint32_t desired_tile_stride,
-+ uint32_t hw_tile_stride)
++
++int
++psb_msvdx_send (struct drm_device *dev, void *cmd, unsigned long cmd_size)
+{
-+ drm_ttm_cache_flush();
++ int ret = 0;
++ struct drm_psb_private *dev_priv = dev->dev_private;
++
++ while (cmd_size > 0)
++ {
++ uint32_t cur_cmd_size = MEMIO_READ_FIELD (cmd, FWRK_GENMSG_SIZE);
++ if (cur_cmd_size > cmd_size)
++ {
++ ret = -EINVAL;
++ PSB_DEBUG_GENERAL
++ ("MSVDX: cmd_size = %d cur_cmd_size = %d\n",
++ (int) cmd_size, cur_cmd_size);
++ goto out;
++ }
++ /* Send the message to h/w */
++ ret = psb_mtx_send (dev_priv, cmd);
++ if (ret)
++ {
++ PSB_DEBUG_GENERAL ("MSVDX: ret:%d\n", ret);
++ goto out;
++ }
++ cmd += cur_cmd_size;
++ cmd_size -= cur_cmd_size;
++ }
++
++out:
++ PSB_DEBUG_GENERAL ("MSVDX: ret:%d\n", ret);
++ return ret;
+}
-+#endif
+
-+void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
-+ unsigned long address, uint32_t num_pages)
++/***********************************************************************************
++ * Function Name : psb_mtx_send
++ * Inputs :
++ * Outputs :
++ * Returns :
++ * Description :
++ ************************************************************************************/
++int
++psb_mtx_send (struct drm_psb_private *dev_priv, const void *pvMsg)
+{
-+ struct psb_mmu_pt *pt;
-+ unsigned long addr;
-+ unsigned long end;
-+ unsigned long next;
-+ unsigned long f_address = address;
+
-+ down_read(&pd->driver->sem);
++ static uint32_t padMessage[FWRK_PADMSG_SIZE];
+
-+ addr = address;
-+ end = addr + (num_pages << PAGE_SHIFT);
++ const uint32_t *pui32Msg = (uint32_t *) pvMsg;
++ uint32_t msgNumWords, wordsFree, readIndex, writeIndex;
++ int ret = 0;
+
-+ do {
-+ next = psb_pd_addr_end(addr, end);
-+ pt = psb_mmu_pt_alloc_map_lock(pd, addr);
-+ if (!pt)
-+ goto out;
-+ do {
-+ psb_mmu_invalidate_pte(pt, addr);
-+ --pt->count;
-+ } while (addr += PAGE_SIZE, addr < next);
-+ psb_mmu_pt_unmap_unlock(pt);
++ PSB_DEBUG_GENERAL ("MSVDX: psb_mtx_send\n");
+
-+ } while (addr = next, next != end);
++ /* we need clocks enabled before we touch VEC local ram */
++ PSB_WMSVDX32 (clk_enable_all, MSVDX_MAN_CLK_ENABLE);
+
-+ out:
-+ if (pd->hw_context != -1)
-+ psb_mmu_flush_ptes(pd, f_address, num_pages, 1, 1);
++ msgNumWords = (MEMIO_READ_FIELD (pvMsg, FWRK_GENMSG_SIZE) + 3) / 4;
+
-+ up_read(&pd->driver->sem);
++ if (msgNumWords > NUM_WORDS_MTX_BUF)
++ {
++ ret = -EINVAL;
++ PSB_DEBUG_GENERAL ("MSVDX: ret:%d\n", ret);
++ goto out;
++ }
+
-+ if (pd->hw_context != -1)
-+ psb_mmu_flush(pd->driver);
++ readIndex = PSB_RMSVDX32 (MSVDX_COMMS_TO_MTX_RD_INDEX);
++ writeIndex = PSB_RMSVDX32 (MSVDX_COMMS_TO_MTX_WRT_INDEX);
+
-+ return;
-+}
++ if (writeIndex + msgNumWords > NUM_WORDS_MTX_BUF)
++ { /* message would wrap, need to send a pad message */
++ BUG_ON (MEMIO_READ_FIELD (pvMsg, FWRK_GENMSG_ID) == FWRK_MSGID_PADDING); /* Shouldn't happen for a PAD message itself */
++ /* if the read pointer is at zero then we must wait for it to change otherwise the write
++ * pointer will equal the read pointer,which should only happen when the buffer is empty
++ *
++ * This will only happens if we try to overfill the queue, queue management should make
++ * sure this never happens in the first place.
++ */
++ BUG_ON (0 == readIndex);
++ if (0 == readIndex)
++ {
++ ret = -EINVAL;
++ PSB_DEBUG_GENERAL ("MSVDX: ret:%d\n", ret);
++ goto out;
++ }
++ /* Send a pad message */
++ MEMIO_WRITE_FIELD (padMessage, FWRK_GENMSG_SIZE,
++ (NUM_WORDS_MTX_BUF - writeIndex) << 2);
++ MEMIO_WRITE_FIELD (padMessage, FWRK_GENMSG_ID, FWRK_MSGID_PADDING);
++ psb_mtx_send (dev_priv, padMessage);
++ writeIndex = PSB_RMSVDX32 (MSVDX_COMMS_TO_MTX_WRT_INDEX);
++ }
+
-+void psb_mmu_remove_pages(struct psb_mmu_pd *pd, unsigned long address,
-+ uint32_t num_pages, uint32_t desired_tile_stride,
-+ uint32_t hw_tile_stride)
-+{
-+ struct psb_mmu_pt *pt;
-+ uint32_t rows = 1;
-+ uint32_t i;
-+ unsigned long addr;
-+ unsigned long end;
-+ unsigned long next;
-+ unsigned long add;
-+ unsigned long row_add;
-+ unsigned long f_address = address;
++ wordsFree =
++ (writeIndex >=
++ readIndex) ? NUM_WORDS_MTX_BUF - (writeIndex -
++ readIndex) : readIndex - writeIndex;
+
-+ if (hw_tile_stride)
-+ rows = num_pages / desired_tile_stride;
-+ else
-+ desired_tile_stride = num_pages;
++ BUG_ON (msgNumWords > wordsFree);
++ if (msgNumWords > wordsFree)
++ {
++ ret = -EINVAL;
++ PSB_DEBUG_GENERAL ("MSVDX: ret:%d\n", ret);
++ goto out;
++ }
+
-+ add = desired_tile_stride << PAGE_SHIFT;
-+ row_add = hw_tile_stride << PAGE_SHIFT;
++ while (msgNumWords > 0)
++ {
++ PSB_WMSVDX32 (*pui32Msg++, MSVDX_COMMS_TO_MTX_BUF + (writeIndex << 2));
++ msgNumWords--;
++ writeIndex++;
++ if (NUM_WORDS_MTX_BUF == writeIndex)
++ {
++ writeIndex = 0;
++ }
++ }
++ PSB_WMSVDX32 (writeIndex, MSVDX_COMMS_TO_MTX_WRT_INDEX);
+
-+ down_read(&pd->driver->sem);
++ /* Make sure clocks are enabled before we kick */
++ PSB_WMSVDX32 (clk_enable_all, MSVDX_MAN_CLK_ENABLE);
+
-+ /* Make sure we only need to flush this processor's cache */
++ /* signal an interrupt to let the mtx know there is a new message */
++ PSB_WMSVDX32 (1, MSVDX_MTX_KICKI);
+
-+ for (i = 0; i < rows; ++i) {
++out:
++ return ret;
++}
+
-+ addr = address;
-+ end = addr + add;
++/*
++ * MSVDX MTX interrupt
++ */
++void
++psb_msvdx_mtx_interrupt (struct drm_device *dev)
++{
++ static uint32_t msgBuffer[128];
++ uint32_t readIndex, writeIndex;
++ uint32_t msgNumWords, msgWordOffset;
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *) dev->dev_private;
+
-+ do {
-+ next = psb_pd_addr_end(addr, end);
-+ pt = psb_mmu_pt_map_lock(pd, addr);
-+ if (!pt)
-+ continue;
-+ do {
-+ psb_mmu_invalidate_pte(pt, addr);
-+ --pt->count;
++ /* Are clocks enabled - If not enable before attempting to read from VLR */
++ if (PSB_RMSVDX32 (MSVDX_MAN_CLK_ENABLE) != (clk_enable_all))
++ {
++ PSB_DEBUG_GENERAL
++ ("MSVDX: Warning - Clocks disabled when Interupt set\n");
++ PSB_WMSVDX32 (clk_enable_all, MSVDX_MAN_CLK_ENABLE);
++ }
+
-+ } while (addr += PAGE_SIZE, addr < next);
-+ psb_mmu_pt_unmap_unlock(pt);
++ for (;;)
++ {
++ readIndex = PSB_RMSVDX32 (MSVDX_COMMS_TO_HOST_RD_INDEX);
++ writeIndex = PSB_RMSVDX32 (MSVDX_COMMS_TO_HOST_WRT_INDEX);
+
-+ } while (addr = next, next != end);
-+ address += row_add;
-+ }
-+ if (pd->hw_context != -1)
-+ psb_mmu_flush_ptes(pd, f_address, num_pages,
-+ desired_tile_stride, hw_tile_stride);
++ if (readIndex != writeIndex)
++ {
++ msgWordOffset = 0;
+
-+ up_read(&pd->driver->sem);
++ msgBuffer[msgWordOffset] =
++ PSB_RMSVDX32 (MSVDX_COMMS_TO_HOST_BUF + (readIndex << 2));
+
-+ if (pd->hw_context != -1)
-+ psb_mmu_flush(pd->driver);
-+}
++ msgNumWords = (MEMIO_READ_FIELD (msgBuffer, FWRK_GENMSG_SIZE) + 3) / 4; /* round to nearest word */
+
-+int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd, uint32_t start_pfn,
-+ unsigned long address, uint32_t num_pages,
-+ int type)
-+{
-+ struct psb_mmu_pt *pt;
-+ uint32_t pte;
-+ unsigned long addr;
-+ unsigned long end;
-+ unsigned long next;
-+ unsigned long f_address = address;
-+ int ret = -ENOMEM;
++ /*ASSERT(msgNumWords <= sizeof(msgBuffer) / sizeof(uint32_t)); */
+
-+ down_read(&pd->driver->sem);
++ if (++readIndex >= NUM_WORDS_HOST_BUF)
++ readIndex = 0;
+
-+ addr = address;
-+ end = addr + (num_pages << PAGE_SHIFT);
++ for (msgWordOffset++; msgWordOffset < msgNumWords; msgWordOffset++)
++ {
++ msgBuffer[msgWordOffset] =
++ PSB_RMSVDX32 (MSVDX_COMMS_TO_HOST_BUF + (readIndex << 2));
+
-+ do {
-+ next = psb_pd_addr_end(addr, end);
-+ pt = psb_mmu_pt_alloc_map_lock(pd, addr);
-+ if (!pt) {
-+ ret = -ENOMEM;
-+ goto out;
++ if (++readIndex >= NUM_WORDS_HOST_BUF)
++ {
++ readIndex = 0;
+ }
-+ do {
-+ pte = psb_mmu_mask_pte(start_pfn++, type);
-+ psb_mmu_set_pte(pt, addr, pte);
-+ pt->count++;
-+ } while (addr += PAGE_SIZE, addr < next);
-+ psb_mmu_pt_unmap_unlock(pt);
++ }
+
-+ } while (addr = next, next != end);
-+ ret = 0;
++ /* Update the Read index */
++ PSB_WMSVDX32 (readIndex, MSVDX_COMMS_TO_HOST_RD_INDEX);
+
-+ out:
-+ if (pd->hw_context != -1)
-+ psb_mmu_flush_ptes(pd, f_address, num_pages, 1, 1);
++ if (!dev_priv->msvdx_needs_reset)
++ switch (MEMIO_READ_FIELD (msgBuffer, FWRK_GENMSG_ID))
++ {
++ case VA_MSGID_CMD_HW_PANIC:
++ case VA_MSGID_CMD_FAILED:
++ {
++ uint32_t ui32Fence = MEMIO_READ_FIELD (msgBuffer,
++ FW_VA_CMD_FAILED_FENCE_VALUE);
++ uint32_t ui32FaultStatus = MEMIO_READ_FIELD (msgBuffer,
++ FW_VA_CMD_FAILED_IRQSTATUS);
+
-+ up_read(&pd->driver->sem);
++ if(MEMIO_READ_FIELD (msgBuffer, FWRK_GENMSG_ID) == VA_MSGID_CMD_HW_PANIC )
++ PSB_DEBUG_GENERAL
++ ("MSVDX: VA_MSGID_CMD_HW_PANIC: Msvdx fault detected - Fence: %08x, Status: %08x - resetting and ignoring error\n",
++ ui32Fence, ui32FaultStatus);
++ else
++ PSB_DEBUG_GENERAL
++ ("MSVDX: VA_MSGID_CMD_FAILED: Msvdx fault detected - Fence: %08x, Status: %08x - resetting and ignoring error\n",
++ ui32Fence, ui32FaultStatus);
+
-+ if (pd->hw_context != -1)
-+ psb_mmu_flush(pd->driver);
++ dev_priv->msvdx_needs_reset = 1;
+
-+ return 0;
-+}
++ if(MEMIO_READ_FIELD (msgBuffer, FWRK_GENMSG_ID) == VA_MSGID_CMD_HW_PANIC)
++ {
++ if (dev_priv->
++ msvdx_current_sequence
++ - dev_priv->sequence[PSB_ENGINE_VIDEO] > 0x0FFFFFFF)
++ dev_priv->msvdx_current_sequence++;
++ PSB_DEBUG_GENERAL
++ ("MSVDX: Fence ID missing, assuming %08x\n",
++ dev_priv->msvdx_current_sequence);
++ }
++ else
++ dev_priv->msvdx_current_sequence = ui32Fence;
+
-+int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
-+ unsigned long address, uint32_t num_pages,
-+ uint32_t desired_tile_stride, uint32_t hw_tile_stride,
-+ int type)
-+{
-+ struct psb_mmu_pt *pt;
-+ uint32_t rows = 1;
-+ uint32_t i;
-+ uint32_t pte;
-+ unsigned long addr;
-+ unsigned long end;
-+ unsigned long next;
-+ unsigned long add;
-+ unsigned long row_add;
-+ unsigned long f_address = address;
-+ int ret = -ENOMEM;
++ psb_fence_error (dev,
++ PSB_ENGINE_VIDEO,
++ dev_priv->
++ msvdx_current_sequence,
++ DRM_FENCE_TYPE_EXE, DRM_CMD_FAILED);
+
-+ if (hw_tile_stride) {
-+ if (num_pages % desired_tile_stride != 0)
-+ return -EINVAL;
-+ rows = num_pages / desired_tile_stride;
-+ } else {
-+ desired_tile_stride = num_pages;
-+ }
-+
-+ add = desired_tile_stride << PAGE_SHIFT;
-+ row_add = hw_tile_stride << PAGE_SHIFT;
-+
-+ down_read(&pd->driver->sem);
-+
-+ for (i = 0; i < rows; ++i) {
-+
-+ addr = address;
-+ end = addr + add;
++ /* Flush the command queue */
++ psb_msvdx_flush_cmd_queue (dev);
+
-+ do {
-+ next = psb_pd_addr_end(addr, end);
-+ pt = psb_mmu_pt_alloc_map_lock(pd, addr);
-+ if (!pt)
-+ goto out;
-+ do {
-+ pte = psb_mmu_mask_pte(page_to_pfn(*pages++),
-+ type);
-+ psb_mmu_set_pte(pt, addr, pte);
-+ pt->count++;
-+ } while (addr += PAGE_SIZE, addr < next);
-+ psb_mmu_pt_unmap_unlock(pt);
++ goto isrExit;
++ break;
++ }
++ case VA_MSGID_CMD_COMPLETED:
++ {
++ uint32_t ui32Fence = MEMIO_READ_FIELD (msgBuffer,
++ FW_VA_CMD_COMPLETED_FENCE_VALUE);
++ uint32_t ui32Flags =
++ MEMIO_READ_FIELD (msgBuffer, FW_VA_CMD_COMPLETED_FLAGS);
+
-+ } while (addr = next, next != end);
++ PSB_DEBUG_GENERAL
++ ("msvdx VA_MSGID_CMD_COMPLETED: FenceID: %08x, flags: 0x%x\n",
++ ui32Fence, ui32Flags);
++ dev_priv->msvdx_current_sequence = ui32Fence;
+
-+ address += row_add;
-+ }
-+ ret = 0;
-+ out:
-+ if (pd->hw_context != -1)
-+ psb_mmu_flush_ptes(pd, f_address, num_pages,
-+ desired_tile_stride, hw_tile_stride);
++ psb_fence_handler (dev, PSB_ENGINE_VIDEO);
+
-+ up_read(&pd->driver->sem);
+
-+ if (pd->hw_context != -1)
-+ psb_mmu_flush(pd->driver);
++ if (ui32Flags & FW_VA_RENDER_HOST_INT)
++ {
++ /*Now send the next command from the msvdx cmd queue */
++ psb_msvdx_dequeue_send (dev);
++ goto isrExit;
++ }
++ break;
++ }
++ case VA_MSGID_ACK:
++ PSB_DEBUG_GENERAL ("msvdx VA_MSGID_ACK\n");
++ break;
+
-+ return 0;
-+}
++ case VA_MSGID_TEST1:
++ PSB_DEBUG_GENERAL ("msvdx VA_MSGID_TEST1\n");
++ break;
+
-+void psb_mmu_enable_requestor(struct psb_mmu_driver *driver, uint32_t mask)
-+{
-+ mask &= _PSB_MMU_ER_MASK;
-+ psb_iowrite32(driver, psb_ioread32(driver, PSB_CR_BIF_CTRL) & ~mask,
-+ PSB_CR_BIF_CTRL);
-+ (void)psb_ioread32(driver, PSB_CR_BIF_CTRL);
-+}
++ case VA_MSGID_TEST2:
++ PSB_DEBUG_GENERAL ("msvdx VA_MSGID_TEST2\n");
++ break;
++ /* Don't need to do anything with these messages */
+
-+void psb_mmu_disable_requestor(struct psb_mmu_driver *driver, uint32_t mask)
-+{
-+ mask &= _PSB_MMU_ER_MASK;
-+ psb_iowrite32(driver, psb_ioread32(driver, PSB_CR_BIF_CTRL) | mask,
-+ PSB_CR_BIF_CTRL);
-+ (void)psb_ioread32(driver, PSB_CR_BIF_CTRL);
-+}
++ case VA_MSGID_DEBLOCK_REQUIRED:
++ {
++ uint32_t ui32ContextId = MEMIO_READ_FIELD (msgBuffer,
++ FW_VA_DEBLOCK_REQUIRED_CONTEXT);
+
-+int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
-+ unsigned long *pfn)
-+{
-+ int ret;
-+ struct psb_mmu_pt *pt;
-+ uint32_t tmp;
-+ spinlock_t *lock = &pd->driver->lock;
++ /* The BE we now be locked. */
+
-+ down_read(&pd->driver->sem);
-+ pt = psb_mmu_pt_map_lock(pd, virtual);
-+ if (!pt) {
-+ uint32_t *v;
++ /* Unblock rendec by reading the mtx2mtx end of slice */
++ (void) PSB_RMSVDX32 (MSVDX_RENDEC_READ_DATA);
+
-+ spin_lock(lock);
-+ v = kmap_atomic(pd->p, KM_USER0);
-+ tmp = v[psb_mmu_pd_index(virtual)];
-+ kunmap_atomic(v, KM_USER0);
-+ spin_unlock(lock);
++ PSB_DEBUG_GENERAL
++ ("msvdx VA_MSGID_DEBLOCK_REQUIRED Context=%08x\n",
++ ui32ContextId);
++ goto isrExit;
++ break;
++ }
+
-+ if (tmp != pd->invalid_pde || !(tmp & PSB_PTE_VALID) ||
-+ !(pd->invalid_pte & PSB_PTE_VALID)) {
-+ ret = -EINVAL;
-+ goto out;
++ default:
++ {
++ PSB_DEBUG_GENERAL
++ ("ERROR: msvdx Unknown message from MTX \n");
+ }
-+ ret = 0;
-+ *pfn = pd->invalid_pte >> PAGE_SHIFT;
-+ goto out;
++ break;
++
++ }
+ }
-+ tmp = pt->v[psb_mmu_pt_index(virtual)];
-+ if (!(tmp & PSB_PTE_VALID)) {
-+ ret = -EINVAL;
-+ } else {
-+ ret = 0;
-+ *pfn = tmp >> PAGE_SHIFT;
++ else
++ {
++ /* Get out of here if nothing */
++ break;
+ }
-+ psb_mmu_pt_unmap_unlock(pt);
-+ out:
-+ up_read(&pd->driver->sem);
-+ return ret;
-+}
++ }
++isrExit:
+
-+void psb_mmu_test(struct psb_mmu_driver *driver, uint32_t offset)
-+{
-+ struct page *p;
-+ unsigned long pfn;
-+ int ret = 0;
-+ struct psb_mmu_pd *pd;
-+ uint32_t *v;
-+ uint32_t *vmmu;
++#if 1
++ if (!dev_priv->msvdx_busy)
++ {
++ /* check that clocks are enabled before reading VLR */
++ if( PSB_RMSVDX32( MSVDX_MAN_CLK_ENABLE ) != (clk_enable_all) )
++ PSB_WMSVDX32 (clk_enable_all, MSVDX_MAN_CLK_ENABLE);
+
-+ pd = driver->default_pd;
-+ if (!pd) {
-+ printk(KERN_WARNING "Could not get default pd\n");
-+ }
++ /* If the firmware says the hardware is idle and the CCB is empty then we can power down */
++ {
++ uint32_t ui32FWStatus = PSB_RMSVDX32( MSVDX_COMMS_FW_STATUS );
++ uint32_t ui32CCBRoff = PSB_RMSVDX32 ( MSVDX_COMMS_TO_MTX_RD_INDEX );
++ uint32_t ui32CCBWoff = PSB_RMSVDX32 ( MSVDX_COMMS_TO_MTX_WRT_INDEX );
+
-+ p = alloc_page(GFP_DMA32);
++ if( (ui32FWStatus & MSVDX_FW_STATUS_HW_IDLE) && (ui32CCBRoff == ui32CCBWoff))
++ {
++ PSB_DEBUG_GENERAL("MSVDX_CLOCK: Setting clock to minimal...\n");
++ PSB_WMSVDX32 (clk_enable_minimal, MSVDX_MAN_CLK_ENABLE);
++ }
++ }
++ }
++#endif
++ DRM_MEMORYBARRIER ();
++}
+
-+ if (!p) {
-+ printk(KERN_WARNING "Failed allocating page\n");
-+ return;
-+ }
++void
++psb_msvdx_lockup (struct drm_psb_private *dev_priv,
++ int *msvdx_lockup, int *msvdx_idle)
++{
++ unsigned long irq_flags;
++// struct psb_scheduler *scheduler = &dev_priv->scheduler;
+
-+ v = kmap(p);
-+ memset(v, 0x67, PAGE_SIZE);
++ spin_lock_irqsave (&dev_priv->msvdx_lock, irq_flags);
++ *msvdx_lockup = 0;
++ *msvdx_idle = 1;
+
-+ pfn = (offset >> PAGE_SHIFT);
++ if (!dev_priv->has_msvdx)
++ {
++ spin_unlock_irqrestore (&dev_priv->msvdx_lock, irq_flags);
++ return;
++ }
++#if 0
++ PSB_DEBUG_GENERAL ("MSVDXTimer: current_sequence:%d "
++ "last_sequence:%d and last_submitted_sequence :%d\n",
++ dev_priv->msvdx_current_sequence,
++ dev_priv->msvdx_last_sequence,
++ dev_priv->sequence[PSB_ENGINE_VIDEO]);
++#endif
++ if (dev_priv->msvdx_current_sequence -
++ dev_priv->sequence[PSB_ENGINE_VIDEO] > 0x0FFFFFFF)
++ {
+
-+ ret = psb_mmu_insert_pages(pd, &p, pfn << PAGE_SHIFT, 1, 0, 0,
-+ PSB_MMU_CACHED_MEMORY);
-+ if (ret) {
-+ printk(KERN_WARNING "Failed inserting mmu page\n");
-+ goto out_err1;
++ if (dev_priv->msvdx_current_sequence == dev_priv->msvdx_last_sequence)
++ {
++ PSB_DEBUG_GENERAL
++ ("MSVDXTimer: msvdx locked-up for sequence:%d\n",
++ dev_priv->msvdx_current_sequence);
++ *msvdx_lockup = 1;
+ }
-+
-+ /* Ioremap the page through the GART aperture */
-+
-+ vmmu = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE);
-+ if (!vmmu) {
-+ printk(KERN_WARNING "Failed ioremapping page\n");
-+ goto out_err2;
++ else
++ {
++ PSB_DEBUG_GENERAL ("MSVDXTimer: msvdx responded fine so far...\n");
++ dev_priv->msvdx_last_sequence = dev_priv->msvdx_current_sequence;
++ *msvdx_idle = 0;
+ }
-+
-+ /* Read from the page with mmu disabled. */
-+ printk(KERN_INFO "Page first dword is 0x%08x\n", ioread32(vmmu));
-+
-+ /* Enable the mmu for host accesses and read again. */
-+ psb_mmu_enable_requestor(driver, _PSB_MMU_ER_HOST);
-+
-+ printk(KERN_INFO "MMU Page first dword is (0x67676767) 0x%08x\n",
-+ ioread32(vmmu));
-+ *v = 0x15243705;
-+ printk(KERN_INFO "MMU Page new dword is (0x15243705) 0x%08x\n",
-+ ioread32(vmmu));
-+ iowrite32(0x16243355, vmmu);
-+ (void)ioread32(vmmu);
-+ printk(KERN_INFO "Page new dword is (0x16243355) 0x%08x\n", *v);
-+
-+ printk(KERN_INFO "Int stat is 0x%08x\n",
-+ psb_ioread32(driver, PSB_CR_BIF_INT_STAT));
-+ printk(KERN_INFO "Fault is 0x%08x\n",
-+ psb_ioread32(driver, PSB_CR_BIF_FAULT));
-+
-+ /* Disable MMU for host accesses and clear page fault register */
-+ psb_mmu_disable_requestor(driver, _PSB_MMU_ER_HOST);
-+ iounmap(vmmu);
-+ out_err2:
-+ psb_mmu_remove_pages(pd, pfn << PAGE_SHIFT, 1, 0, 0);
-+ out_err1:
-+ kunmap(p);
-+ __free_page(p);
++ if (dev_priv->msvdx_start_idle)
++ dev_priv->msvdx_start_idle = 0;
++ }
++ else
++ {
++ if (dev_priv->msvdx_needs_reset == 0)
++ {
++ if (dev_priv->msvdx_start_idle && (dev_priv->msvdx_finished_sequence == dev_priv->msvdx_current_sequence))
++ {
++ //if (dev_priv->msvdx_idle_start_jiffies + MSVDX_MAX_IDELTIME >= jiffies)
++ if (time_after_eq(jiffies, dev_priv->msvdx_idle_start_jiffies + MSVDX_MAX_IDELTIME))
++ {
++ printk("set the msvdx clock to 0 in the %s\n", __FUNCTION__);
++ PSB_WMSVDX32 (0, MSVDX_MAN_CLK_ENABLE);
++ dev_priv->msvdx_needs_reset = 1;
++ }
++ else
++ {
++ *msvdx_idle = 0;
++ }
++ }
++ else
++ {
++ dev_priv->msvdx_start_idle = 1;
++ dev_priv->msvdx_idle_start_jiffies = jiffies;
++ dev_priv->msvdx_finished_sequence = dev_priv->msvdx_current_sequence;
++ *msvdx_idle = 0;
++ }
++ }
++ }
++ spin_unlock_irqrestore (&dev_priv->msvdx_lock, irq_flags);
+}
-Index: linux-2.6.28/drivers/gpu/drm/psb/psb_msvdx.c
+Index: linux-2.6.28/drivers/gpu/drm/psb/psb_msvdx.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/psb/psb_msvdx.c 2009-02-12 09:14:42.000000000 +0000
-@@ -0,0 +1,678 @@
-+/**
-+ * file psb_msvdx.c
-+ * MSVDX I/O operations and IRQ handling
-+ *
-+ */
-+
++++ linux-2.6.28/drivers/gpu/drm/psb/psb_msvdx.h 2009-02-12 09:14:42.000000000 +0000
+@@ -0,0 +1,564 @@
+/**************************************************************************
+ *
+ * Copyright (c) 2007 Intel Corporation, Hillsboro, OR, USA
+ *
+ **************************************************************************/
+
-+#include "drmP.h"
-+#include "drm_os_linux.h"
-+#include "psb_drv.h"
-+#include "psb_drm.h"
-+#include "psb_msvdx.h"
-+
-+#include <asm/io.h>
-+#include <linux/delay.h>
++#ifndef _PSB_MSVDX_H_
++#define _PSB_MSVDX_H_
+
-+#ifndef list_first_entry
-+#define list_first_entry(ptr, type, member) \
-+ list_entry((ptr)->next, type, member)
-+#endif
++#define assert(expr) \
++ if(unlikely(!(expr))) { \
++ printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
++ #expr,__FILE__,__FUNCTION__,__LINE__); \
++ }
+
-+static int psb_msvdx_send (struct drm_device *dev, void *cmd,
-+ unsigned long cmd_size);
++#define PSB_ASSERT(x) assert (x)
++#define IMG_ASSERT(x) assert (x)
+
++#include "psb_drv.h"
+int
-+psb_msvdx_dequeue_send (struct drm_device *dev)
-+{
-+ struct drm_psb_private *dev_priv = dev->dev_private;
-+ struct psb_msvdx_cmd_queue *msvdx_cmd = NULL;
-+ int ret = 0;
++psb_wait_for_register (struct drm_psb_private *dev_priv,
++ uint32_t ui32Offset,
++ uint32_t ui32Value, uint32_t ui32Enable);
+
-+ if (list_empty (&dev_priv->msvdx_queue))
-+ {
-+ PSB_DEBUG_GENERAL ("MSVDXQUE: msvdx list empty.\n");
-+ dev_priv->msvdx_busy = 0;
-+ return -EINVAL;
-+ }
-+ msvdx_cmd =
-+ list_first_entry (&dev_priv->msvdx_queue, struct psb_msvdx_cmd_queue,
-+ head);
-+ PSB_DEBUG_GENERAL ("MSVDXQUE: Queue has id %08x\n", msvdx_cmd->sequence);
-+ ret = psb_msvdx_send (dev, msvdx_cmd->cmd, msvdx_cmd->cmd_size);
-+ if (ret)
-+ {
-+ PSB_DEBUG_GENERAL ("MSVDXQUE: psb_msvdx_send failed\n");
-+ ret = -EINVAL;
-+ }
-+ list_del (&msvdx_cmd->head);
-+ kfree (msvdx_cmd->cmd);
-+ drm_free (msvdx_cmd, sizeof (struct psb_msvdx_cmd_queue), DRM_MEM_DRIVER);
-+ return ret;
-+}
++void psb_msvdx_mtx_interrupt (struct drm_device *dev);
++int psb_msvdx_init (struct drm_device *dev);
++int psb_msvdx_uninit (struct drm_device *dev);
++int psb_msvdx_reset (struct drm_psb_private *dev_priv);
++uint32_t psb_get_default_pd_addr (struct psb_mmu_driver *driver);
++int psb_mtx_send (struct drm_psb_private *dev_priv, const void *pvMsg);
++void psb_msvdx_irq_preinstall (struct drm_psb_private *dev_priv);
++void psb_msvdx_irq_postinstall (struct drm_psb_private *dev_priv);
++void psb_msvdx_flush_cmd_queue (struct drm_device *dev);
++extern void psb_msvdx_lockup (struct drm_psb_private *dev_priv,
++ int *msvdx_lockup, int *msvdx_idle);
++#define MSVDX_DEVICE_NODE_FLAGS_MMU_NONOPT_INV 2 /* Non-Optimal Invalidation is not default */
++#define FW_VA_RENDER_HOST_INT 0x00004000
++#define MSVDX_DEVICE_NODE_FLAGS_MMU_HW_INVALIDATION 0x00000020
+
-+int
-+psb_msvdx_map_command (struct drm_device *dev,
-+ struct drm_buffer_object *cmd_buffer,
-+ unsigned long cmd_offset, unsigned long cmd_size,
-+ void **msvdx_cmd, uint32_t sequence, int copy_cmd)
-+{
-+ struct drm_psb_private *dev_priv = dev->dev_private;
-+ int ret = 0;
-+ unsigned long cmd_page_offset = cmd_offset & ~PAGE_MASK;
-+ unsigned long cmd_size_remaining;
-+ struct drm_bo_kmap_obj cmd_kmap;
-+ void *cmd, *tmp, *cmd_start;
-+ int is_iomem;
++#define MSVDX_DEVICE_NODE_FLAG_BRN23154_BLOCK_ON_FE 0x00000200
+
-+ /* command buffers may not exceed page boundary */
-+ if (cmd_size + cmd_page_offset > PAGE_SIZE)
-+ return -EINVAL;
++#define MSVDX_DEVICE_NODE_FLAGS_DEFAULT_D0 (MSVDX_DEVICE_NODE_FLAGS_MMU_NONOPT_INV | MSVDX_DEVICE_NODE_FLAGS_MMU_HW_INVALIDATION \
++ | MSVDX_DEVICE_NODE_FLAG_BRN23154_BLOCK_ON_FE)
++#define MSVDX_DEVICE_NODE_FLAGS_DEFAULT_D1 (MSVDX_DEVICE_NODE_FLAGS_MMU_HW_INVALIDATION \
++ | MSVDX_DEVICE_NODE_FLAG_BRN23154_BLOCK_ON_FE)
+
-+ ret = drm_bo_kmap (cmd_buffer, cmd_offset >> PAGE_SHIFT, 2, &cmd_kmap);
+
-+ if (ret)
-+ {
-+ PSB_DEBUG_GENERAL ("MSVDXQUE:ret:%d\n", ret);
-+ return ret;
-+ }
++#define POULSBO_D0 0x5
++#define POULSBO_D1 0x6
++#define PSB_REVID_OFFSET 0x8
+
-+ cmd_start =
-+ (void *) drm_bmo_virtual (&cmd_kmap, &is_iomem) + cmd_page_offset;
-+ cmd = cmd_start;
-+ cmd_size_remaining = cmd_size;
++#define MSVDX_FW_STATUS_HW_IDLE 0x00000001 /* There is no work currently underway on the hardware*/
+
-+ while (cmd_size_remaining > 0)
-+ {
-+ uint32_t mmu_ptd;
-+ uint32_t cur_cmd_size = MEMIO_READ_FIELD (cmd, FWRK_GENMSG_SIZE);
-+ uint32_t cur_cmd_id = MEMIO_READ_FIELD (cmd, FWRK_GENMSG_ID);
-+ PSB_DEBUG_GENERAL
-+ ("cmd start at %08x cur_cmd_size = %d cur_cmd_id = %02x fence = %08x\n",
-+ (uint32_t) cmd, cur_cmd_size, cur_cmd_id, sequence);
-+ if ((cur_cmd_size % sizeof (uint32_t))
-+ || (cur_cmd_size > cmd_size_remaining))
-+ {
-+ ret = -EINVAL;
-+ PSB_DEBUG_GENERAL ("MSVDX: ret:%d\n", ret);
-+ goto out;
-+ }
++#define clk_enable_all MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_CORE_MAN_CLK_ENABLE_MASK | \
++ MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDEB_PROCESS_MAN_CLK_ENABLE_MASK | \
++ MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDEB_ACCESS_MAN_CLK_ENABLE_MASK | \
++ MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDMC_MAN_CLK_ENABLE_MASK | \
++ MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VEC_ENTDEC_MAN_CLK_ENABLE_MASK | \
++ MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VEC_ITRANS_MAN_CLK_ENABLE_MASK | \
++ MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_MTX_MAN_CLK_ENABLE_MASK
+
-+ switch (cur_cmd_id)
-+ {
-+ case VA_MSGID_RENDER:
-+ /* Fence ID */
-+ MEMIO_WRITE_FIELD (cmd, FW_VA_RENDER_FENCE_VALUE, sequence);
++#define clk_enable_minimal MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_CORE_MAN_CLK_ENABLE_MASK | \
++ MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_MTX_MAN_CLK_ENABLE_MASK
+
-+ mmu_ptd = psb_get_default_pd_addr (dev_priv->mmu);
-+ if (atomic_cmpxchg(&dev_priv->msvdx_mmu_invaldc, 1, 0) == 1)
-+ {
-+ mmu_ptd |= 1;
-+ PSB_DEBUG_GENERAL ("MSVDX: Setting MMU invalidate flag\n");
-+ }
-+ /* PTD */
-+ MEMIO_WRITE_FIELD (cmd, FW_VA_RENDER_MMUPTD, mmu_ptd);
-+ break;
++#define clk_enable_auto MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDEB_PROCESS_AUTO_CLK_ENABLE_MASK | \
++ MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDEB_ACCESS_AUTO_CLK_ENABLE_MASK | \
++ MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDMC_AUTO_CLK_ENABLE_MASK | \
++ MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VEC_ENTDEC_AUTO_CLK_ENABLE_MASK | \
++ MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VEC_ITRANS_AUTO_CLK_ENABLE_MASK | \
++ MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_CORE_MAN_CLK_ENABLE_MASK | \
++ MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_MTX_MAN_CLK_ENABLE_MASK
+
-+ default:
-+ /* Msg not supported */
-+ ret = -EINVAL;
-+ PSB_DEBUG_GENERAL ("MSVDX: ret:%d\n", ret);
-+ goto out;
-+ }
++#define msvdx_sw_reset_all MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_SOFT_RESET_MASK | \
++ MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_FE_SOFT_RESET_MASK | \
++ MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_BE_SOFT_RESET_MASK | \
++ MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_VEC_MEMIF_SOFT_RESET_MASK | \
++ MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_VEC_RENDEC_DEC_SOFT_RESET_MASK
+
-+ cmd += cur_cmd_size;
-+ cmd_size_remaining -= cur_cmd_size;
-+ }
+
-+ if (copy_cmd)
-+ {
-+ PSB_DEBUG_GENERAL
-+ ("MSVDXQUE: psb_msvdx_map_command copying command...\n");
-+ tmp = drm_calloc (1, cmd_size, DRM_MEM_DRIVER);
-+ if (tmp == NULL)
-+ {
-+ ret = -ENOMEM;
-+ PSB_DEBUG_GENERAL ("MSVDX: ret:%d\n", ret);
-+ goto out;
-+ }
-+ memcpy (tmp, cmd_start, cmd_size);
-+ *msvdx_cmd = tmp;
-+ }
-+ else
-+ {
-+ PSB_DEBUG_GENERAL
-+ ("MSVDXQUE: psb_msvdx_map_command did NOT copy command...\n");
-+ ret = psb_msvdx_send (dev, cmd_start, cmd_size);
-+ if (ret)
-+ {
-+ PSB_DEBUG_GENERAL ("MSVDXQUE: psb_msvdx_send failed\n");
-+ ret = -EINVAL;
-+ }
-+ }
++#define PCI_PORT5_REG80_FFUSE 0xD0058000
++#define MTX_CODE_BASE (0x80900000)
++#define MTX_DATA_BASE (0x82880000)
++#define PC_START_ADDRESS (0x80900000)
+
-+out:
-+ drm_bo_kunmap (&cmd_kmap);
++#define MTX_CORE_CODE_MEM (0x10 )
++#define MTX_CORE_DATA_MEM (0x18 )
+
-+ return ret;
-+}
++#define MTX_INTERNAL_REG( R_SPECIFIER , U_SPECIFIER ) ( ((R_SPECIFIER)<<4) | (U_SPECIFIER) )
++#define MTX_PC MTX_INTERNAL_REG( 0 , 5 )
+
-+int
-+psb_submit_video_cmdbuf (struct drm_device *dev,
-+ struct drm_buffer_object *cmd_buffer,
-+ unsigned long cmd_offset, unsigned long cmd_size,
-+ struct drm_fence_object *fence)
-+{
-+ struct drm_psb_private *dev_priv = dev->dev_private;
-+ uint32_t sequence = fence->sequence;
-+ unsigned long irq_flags;
-+ int ret = 0;
++#define RENDEC_A_SIZE ( 2 * 1024* 1024 )
++#define RENDEC_B_SIZE ( RENDEC_A_SIZE / 4 )
+
-+ mutex_lock (&dev_priv->msvdx_mutex);
-+ psb_schedule_watchdog (dev_priv);
++#define MEMIO_READ_FIELD(vpMem, field) \
++ ((uint32_t)(((*((field##_TYPE *)(((uint32_t)vpMem) + field##_OFFSET))) & field##_MASK) >> field##_SHIFT))
+
-+ spin_lock_irqsave (&dev_priv->msvdx_lock, irq_flags);
-+ if (dev_priv->msvdx_needs_reset)
-+ {
-+ spin_unlock_irqrestore (&dev_priv->msvdx_lock, irq_flags);
-+ PSB_DEBUG_GENERAL ("MSVDX: Needs reset\n");
-+ if (psb_msvdx_reset (dev_priv))
-+ {
-+ mutex_unlock (&dev_priv->msvdx_mutex);
-+ ret = -EBUSY;
-+ PSB_DEBUG_GENERAL ("MSVDX: Reset failed\n");
-+ return ret;
-+ }
-+ PSB_DEBUG_GENERAL ("MSVDX: Reset ok\n");
-+ dev_priv->msvdx_needs_reset = 0;
-+ dev_priv->msvdx_busy = 0;
-+ dev_priv->msvdx_start_idle = 0;
++#define MEMIO_WRITE_FIELD(vpMem, field, ui32Value) \
++ (*((field##_TYPE *)(((uint32_t)vpMem) + field##_OFFSET))) = \
++ ((*((field##_TYPE *)(((uint32_t)vpMem) + field##_OFFSET))) & (field##_TYPE)~field##_MASK) | \
++ (field##_TYPE)(( (uint32_t) (ui32Value) << field##_SHIFT) & field##_MASK);
+
-+ psb_msvdx_init (dev);
-+ psb_msvdx_irq_preinstall (dev_priv);
-+ psb_msvdx_irq_postinstall (dev_priv);
-+ PSB_DEBUG_GENERAL ("MSVDX: Init ok\n");
-+ spin_lock_irqsave (&dev_priv->msvdx_lock, irq_flags);
-+ }
++#define MEMIO_WRITE_FIELD_LITE(vpMem, field, ui32Value) \
++ (*((field##_TYPE *)(((uint32_t)vpMem) + field##_OFFSET))) = \
++ ((*((field##_TYPE *)(((uint32_t)vpMem) + field##_OFFSET))) | \
++ (field##_TYPE) (( (uint32_t) (ui32Value) << field##_SHIFT)) );
+
-+ if (!dev_priv->msvdx_busy)
-+ {
-+ dev_priv->msvdx_busy = 1;
-+ spin_unlock_irqrestore (&dev_priv->msvdx_lock, irq_flags);
-+ PSB_DEBUG_GENERAL
-+ ("MSVDXQUE: nothing in the queue sending sequence:%08x..\n",
-+ sequence);
-+ ret =
-+ psb_msvdx_map_command (dev, cmd_buffer, cmd_offset, cmd_size,
-+ NULL, sequence, 0);
-+ if (ret)
-+ {
-+ mutex_unlock (&dev_priv->msvdx_mutex);
-+ PSB_DEBUG_GENERAL ("MSVDXQUE: Failed to extract cmd...\n");
-+ return ret;
-+ }
-+ }
-+ else
-+ {
-+ struct psb_msvdx_cmd_queue *msvdx_cmd;
-+ void *cmd = NULL;
++#define REGIO_READ_FIELD(ui32RegValue, reg, field) \
++ ((ui32RegValue & reg##_##field##_MASK) >> reg##_##field##_SHIFT)
+
-+ spin_unlock_irqrestore (&dev_priv->msvdx_lock, irq_flags);
-+ /*queue the command to be sent when the h/w is ready */
-+ PSB_DEBUG_GENERAL ("MSVDXQUE: queueing sequence:%08x..\n", sequence);
-+ msvdx_cmd =
-+ drm_calloc (1, sizeof (struct psb_msvdx_cmd_queue), DRM_MEM_DRIVER);
-+ if (msvdx_cmd == NULL)
-+ {
-+ mutex_unlock (&dev_priv->msvdx_mutex);
-+ PSB_DEBUG_GENERAL ("MSVDXQUE: Out of memory...\n");
-+ return -ENOMEM;
-+ }
++#define REGIO_WRITE_FIELD(ui32RegValue, reg, field, ui32Value) \
++ (ui32RegValue) = \
++ ((ui32RegValue) & ~(reg##_##field##_MASK)) | \
++ (((ui32Value) << (reg##_##field##_SHIFT)) & (reg##_##field##_MASK));
+
-+ ret =
-+ psb_msvdx_map_command (dev, cmd_buffer, cmd_offset, cmd_size,
-+ &cmd, sequence, 1);
-+ if (ret)
-+ {
-+ mutex_unlock (&dev_priv->msvdx_mutex);
-+ PSB_DEBUG_GENERAL ("MSVDXQUE: Failed to extract cmd...\n");
-+ drm_free (msvdx_cmd, sizeof (struct psb_msvdx_cmd_queue),
-+ DRM_MEM_DRIVER);
-+ return ret;
-+ }
-+ msvdx_cmd->cmd = cmd;
-+ msvdx_cmd->cmd_size = cmd_size;
-+ msvdx_cmd->sequence = sequence;
-+ spin_lock_irqsave (&dev_priv->msvdx_lock, irq_flags);
-+ list_add_tail (&msvdx_cmd->head, &dev_priv->msvdx_queue);
-+ if (!dev_priv->msvdx_busy)
-+ {
-+ dev_priv->msvdx_busy = 1;
-+ PSB_DEBUG_GENERAL ("MSVDXQUE: Need immediate dequeue\n");
-+ psb_msvdx_dequeue_send (dev);
-+ }
-+ spin_unlock_irqrestore (&dev_priv->msvdx_lock, irq_flags);
-+ }
-+ mutex_unlock (&dev_priv->msvdx_mutex);
-+ return ret;
-+}
++#define REGIO_WRITE_FIELD_LITE(ui32RegValue, reg, field, ui32Value) \
++ (ui32RegValue) = \
++ ( (ui32RegValue) | ( (ui32Value) << (reg##_##field##_SHIFT) ) );
+
-+int
-+psb_msvdx_send (struct drm_device *dev, void *cmd, unsigned long cmd_size)
-+{
-+ int ret = 0;
-+ struct drm_psb_private *dev_priv = dev->dev_private;
++#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_CORE_MAN_CLK_ENABLE_MASK (0x00000001)
++#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDEB_PROCESS_MAN_CLK_ENABLE_MASK (0x00000002)
++#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDEB_ACCESS_MAN_CLK_ENABLE_MASK (0x00000004)
++#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDMC_MAN_CLK_ENABLE_MASK (0x00000008)
++#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VEC_ENTDEC_MAN_CLK_ENABLE_MASK (0x00000010)
++#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VEC_ITRANS_MAN_CLK_ENABLE_MASK (0x00000020)
++#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_MTX_MAN_CLK_ENABLE_MASK (0x00000040)
++#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDEB_ACCESS_AUTO_CLK_ENABLE_MASK (0x00040000)
++#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDMC_AUTO_CLK_ENABLE_MASK (0x00080000)
++#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VEC_ENTDEC_AUTO_CLK_ENABLE_MASK (0x00100000)
++#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VEC_ITRANS_AUTO_CLK_ENABLE_MASK (0x00200000)
++#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_SOFT_RESET_MASK (0x00000100)
++#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_FE_SOFT_RESET_MASK (0x00010000)
++#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_BE_SOFT_RESET_MASK (0x00100000)
++#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_VEC_MEMIF_SOFT_RESET_MASK (0x01000000)
++#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_VEC_RENDEC_DEC_SOFT_RESET_MASK (0x10000000)
+
-+ while (cmd_size > 0)
-+ {
-+ uint32_t cur_cmd_size = MEMIO_READ_FIELD (cmd, FWRK_GENMSG_SIZE);
-+ if (cur_cmd_size > cmd_size)
-+ {
-+ ret = -EINVAL;
-+ PSB_DEBUG_GENERAL
-+ ("MSVDX: cmd_size = %d cur_cmd_size = %d\n",
-+ (int) cmd_size, cur_cmd_size);
-+ goto out;
-+ }
-+ /* Send the message to h/w */
-+ ret = psb_mtx_send (dev_priv, cmd);
-+ if (ret)
-+ {
-+ PSB_DEBUG_GENERAL ("MSVDX: ret:%d\n", ret);
-+ goto out;
-+ }
-+ cmd += cur_cmd_size;
-+ cmd_size -= cur_cmd_size;
-+ }
++/* MTX registers */
++#define MSVDX_MTX_ENABLE (0x0000)
++#define MSVDX_MTX_KICKI (0x0088)
++#define MSVDX_MTX_REGISTER_READ_WRITE_REQUEST (0x00FC)
++#define MSVDX_MTX_REGISTER_READ_WRITE_DATA (0x00F8)
++#define MSVDX_MTX_RAM_ACCESS_DATA_TRANSFER (0x0104)
++#define MSVDX_MTX_RAM_ACCESS_CONTROL (0x0108)
++#define MSVDX_MTX_RAM_ACCESS_STATUS (0x010C)
++#define MSVDX_MTX_SOFT_RESET (0x0200)
+
-+out:
-+ PSB_DEBUG_GENERAL ("MSVDX: ret:%d\n", ret);
-+ return ret;
-+}
++/* MSVDX registers */
++#define MSVDX_CONTROL (0x0600)
++#define MSVDX_INTERRUPT_CLEAR (0x060C)
++#define MSVDX_INTERRUPT_STATUS (0x0608)
++#define MSVDX_HOST_INTERRUPT_ENABLE (0x0610)
++#define MSVDX_MMU_CONTROL0 (0x0680)
++#define MSVDX_MTX_RAM_BANK (0x06F0)
++#define MSVDX_MAN_CLK_ENABLE (0x0620)
+
-+/***********************************************************************************
-+ * Function Name : psb_mtx_send
-+ * Inputs :
-+ * Outputs :
-+ * Returns :
-+ * Description :
-+ ************************************************************************************/
-+int
-+psb_mtx_send (struct drm_psb_private *dev_priv, const void *pvMsg)
-+{
++/* RENDEC registers */
++#define MSVDX_RENDEC_CONTROL0 (0x0868)
++#define MSVDX_RENDEC_CONTROL1 (0x086C)
++#define MSVDX_RENDEC_BUFFER_SIZE (0x0870)
++#define MSVDX_RENDEC_BASE_ADDR0 (0x0874)
++#define MSVDX_RENDEC_BASE_ADDR1 (0x0878)
++#define MSVDX_RENDEC_READ_DATA (0x0898)
++#define MSVDX_RENDEC_CONTEXT0 (0x0950)
++#define MSVDX_RENDEC_CONTEXT1 (0x0954)
++#define MSVDX_RENDEC_CONTEXT2 (0x0958)
++#define MSVDX_RENDEC_CONTEXT3 (0x095C)
++#define MSVDX_RENDEC_CONTEXT4 (0x0960)
++#define MSVDX_RENDEC_CONTEXT5 (0x0964)
+
-+ static uint32_t padMessage[FWRK_PADMSG_SIZE];
++/*
++ * This defines the MSVDX communication buffer
++ */
++#define MSVDX_COMMS_SIGNATURE_VALUE (0xA5A5A5A5) /*!< Signature value */
++#define NUM_WORDS_HOST_BUF (100) /*!< Host buffer size (in 32-bit words) */
++#define NUM_WORDS_MTX_BUF (100) /*!< MTX buffer size (in 32-bit words) */
+
-+ const uint32_t *pui32Msg = (uint32_t *) pvMsg;
-+ uint32_t msgNumWords, wordsFree, readIndex, writeIndex;
-+ int ret = 0;
++#define MSVDX_COMMS_AREA_ADDR (0x02cc0)
+
-+ PSB_DEBUG_GENERAL ("MSVDX: psb_mtx_send\n");
++#define MSVDX_COMMS_FW_STATUS (MSVDX_COMMS_AREA_ADDR - 0x10)
++#define MSVDX_COMMS_SCRATCH (MSVDX_COMMS_AREA_ADDR - 0x08)
++#define MSVDX_COMMS_MSG_COUNTER (MSVDX_COMMS_AREA_ADDR - 0x04)
++#define MSVDX_COMMS_SIGNATURE (MSVDX_COMMS_AREA_ADDR + 0x00)
++#define MSVDX_COMMS_TO_HOST_BUF_SIZE (MSVDX_COMMS_AREA_ADDR + 0x04)
++#define MSVDX_COMMS_TO_HOST_RD_INDEX (MSVDX_COMMS_AREA_ADDR + 0x08)
++#define MSVDX_COMMS_TO_HOST_WRT_INDEX (MSVDX_COMMS_AREA_ADDR + 0x0C)
++#define MSVDX_COMMS_TO_MTX_BUF_SIZE (MSVDX_COMMS_AREA_ADDR + 0x10)
++#define MSVDX_COMMS_TO_MTX_RD_INDEX (MSVDX_COMMS_AREA_ADDR + 0x14)
++#define MSVDX_COMMS_OFFSET_FLAGS (MSVDX_COMMS_AREA_ADDR + 0x18)
++#define MSVDX_COMMS_TO_MTX_WRT_INDEX (MSVDX_COMMS_AREA_ADDR + 0x1C)
++#define MSVDX_COMMS_TO_HOST_BUF (MSVDX_COMMS_AREA_ADDR + 0x20)
++#define MSVDX_COMMS_TO_MTX_BUF (MSVDX_COMMS_TO_HOST_BUF + (NUM_WORDS_HOST_BUF << 2))
+
-+ /* we need clocks enabled before we touch VEC local ram */
-+ PSB_WMSVDX32 (clk_enable_all, MSVDX_MAN_CLK_ENABLE);
++#define MSVDX_COMMS_AREA_END (MSVDX_COMMS_TO_MTX_BUF + (NUM_WORDS_HOST_BUF << 2))
+
-+ msgNumWords = (MEMIO_READ_FIELD (pvMsg, FWRK_GENMSG_SIZE) + 3) / 4;
++#if (MSVDX_COMMS_AREA_END != 0x03000)
++#error
++#endif
+
-+ if (msgNumWords > NUM_WORDS_MTX_BUF)
-+ {
-+ ret = -EINVAL;
-+ PSB_DEBUG_GENERAL ("MSVDX: ret:%d\n", ret);
-+ goto out;
-+ }
++#define MSVDX_MTX_REGISTER_READ_WRITE_REQUEST_MTX_DREADY_MASK (0x80000000)
++#define MSVDX_MTX_REGISTER_READ_WRITE_REQUEST_MTX_DREADY_SHIFT (31)
+
-+ readIndex = PSB_RMSVDX32 (MSVDX_COMMS_TO_MTX_RD_INDEX);
-+ writeIndex = PSB_RMSVDX32 (MSVDX_COMMS_TO_MTX_WRT_INDEX);
++#define MSVDX_MTX_REGISTER_READ_WRITE_REQUEST_MTX_RNW_MASK (0x00010000)
++#define MSVDX_MTX_REGISTER_READ_WRITE_REQUEST_MTX_RNW_SHIFT (16)
+
-+ if (writeIndex + msgNumWords > NUM_WORDS_MTX_BUF)
-+ { /* message would wrap, need to send a pad message */
-+ BUG_ON (MEMIO_READ_FIELD (pvMsg, FWRK_GENMSG_ID) == FWRK_MSGID_PADDING); /* Shouldn't happen for a PAD message itself */
-+ /* if the read pointer is at zero then we must wait for it to change otherwise the write
-+ * pointer will equal the read pointer,which should only happen when the buffer is empty
-+ *
-+ * This will only happens if we try to overfill the queue, queue management should make
-+ * sure this never happens in the first place.
-+ */
-+ BUG_ON (0 == readIndex);
-+ if (0 == readIndex)
-+ {
-+ ret = -EINVAL;
-+ PSB_DEBUG_GENERAL ("MSVDX: ret:%d\n", ret);
-+ goto out;
-+ }
-+ /* Send a pad message */
-+ MEMIO_WRITE_FIELD (padMessage, FWRK_GENMSG_SIZE,
-+ (NUM_WORDS_MTX_BUF - writeIndex) << 2);
-+ MEMIO_WRITE_FIELD (padMessage, FWRK_GENMSG_ID, FWRK_MSGID_PADDING);
-+ psb_mtx_send (dev_priv, padMessage);
-+ writeIndex = PSB_RMSVDX32 (MSVDX_COMMS_TO_MTX_WRT_INDEX);
-+ }
++#define MSVDX_MTX_RAM_ACCESS_CONTROL_MTX_MCMID_MASK (0x0FF00000)
++#define MSVDX_MTX_RAM_ACCESS_CONTROL_MTX_MCMID_SHIFT (20)
+
-+ wordsFree =
-+ (writeIndex >=
-+ readIndex) ? NUM_WORDS_MTX_BUF - (writeIndex -
-+ readIndex) : readIndex - writeIndex;
++#define MSVDX_MTX_RAM_ACCESS_CONTROL_MTX_MCM_ADDR_MASK (0x000FFFFC)
++#define MSVDX_MTX_RAM_ACCESS_CONTROL_MTX_MCM_ADDR_SHIFT (2)
+
-+ BUG_ON (msgNumWords > wordsFree);
-+ if (msgNumWords > wordsFree)
-+ {
-+ ret = -EINVAL;
-+ PSB_DEBUG_GENERAL ("MSVDX: ret:%d\n", ret);
-+ goto out;
-+ }
++#define MSVDX_MTX_RAM_ACCESS_CONTROL_MTX_MCMAI_MASK (0x00000002)
++#define MSVDX_MTX_RAM_ACCESS_CONTROL_MTX_MCMAI_SHIFT (1)
+
-+ while (msgNumWords > 0)
-+ {
-+ PSB_WMSVDX32 (*pui32Msg++, MSVDX_COMMS_TO_MTX_BUF + (writeIndex << 2));
-+ msgNumWords--;
-+ writeIndex++;
-+ if (NUM_WORDS_MTX_BUF == writeIndex)
-+ {
-+ writeIndex = 0;
-+ }
-+ }
-+ PSB_WMSVDX32 (writeIndex, MSVDX_COMMS_TO_MTX_WRT_INDEX);
++#define MSVDX_MTX_RAM_ACCESS_CONTROL_MTX_MCMR_MASK (0x00000001)
++#define MSVDX_MTX_RAM_ACCESS_CONTROL_MTX_MCMR_SHIFT (0)
+
-+ /* Make sure clocks are enabled before we kick */
-+ PSB_WMSVDX32 (clk_enable_all, MSVDX_MAN_CLK_ENABLE);
++#define MSVDX_MTX_SOFT_RESET_MTX_RESET_MASK (0x00000001)
++#define MSVDX_MTX_SOFT_RESET_MTX_RESET_SHIFT (0)
+
-+ /* signal an interrupt to let the mtx know there is a new message */
-+ PSB_WMSVDX32 (1, MSVDX_MTX_KICKI);
++#define MSVDX_MTX_ENABLE_MTX_ENABLE_MASK (0x00000001)
++#define MSVDX_MTX_ENABLE_MTX_ENABLE_SHIFT (0)
+
-+out:
-+ return ret;
-+}
++#define MSVDX_CONTROL_CR_MSVDX_SOFT_RESET_MASK (0x00000100)
++#define MSVDX_CONTROL_CR_MSVDX_SOFT_RESET_SHIFT (8)
+
-+/*
-+ * MSVDX MTX interrupt
-+ */
-+void
-+psb_msvdx_mtx_interrupt (struct drm_device *dev)
-+{
-+ static uint32_t msgBuffer[128];
-+ uint32_t readIndex, writeIndex;
-+ uint32_t msgNumWords, msgWordOffset;
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *) dev->dev_private;
++#define MSVDX_INTERRUPT_STATUS_CR_MMU_FAULT_IRQ_MASK (0x00000F00)
++#define MSVDX_INTERRUPT_STATUS_CR_MMU_FAULT_IRQ_SHIFT (8)
+
-+ /* Are clocks enabled - If not enable before attempting to read from VLR */
-+ if (PSB_RMSVDX32 (MSVDX_MAN_CLK_ENABLE) != (clk_enable_all))
-+ {
-+ PSB_DEBUG_GENERAL
-+ ("MSVDX: Warning - Clocks disabled when Interupt set\n");
-+ PSB_WMSVDX32 (clk_enable_all, MSVDX_MAN_CLK_ENABLE);
-+ }
++#define MSVDX_INTERRUPT_STATUS_CR_MTX_IRQ_MASK (0x00004000)
++#define MSVDX_INTERRUPT_STATUS_CR_MTX_IRQ_SHIFT (14)
+
-+ for (;;)
-+ {
-+ readIndex = PSB_RMSVDX32 (MSVDX_COMMS_TO_HOST_RD_INDEX);
-+ writeIndex = PSB_RMSVDX32 (MSVDX_COMMS_TO_HOST_WRT_INDEX);
++#define MSVDX_MMU_CONTROL0_CR_MMU_PAUSE_MASK (0x00000002)
++#define MSVDX_MMU_CONTROL0_CR_MMU_PAUSE_SHIFT (1)
+
-+ if (readIndex != writeIndex)
-+ {
-+ msgWordOffset = 0;
++#define MSVDX_MTX_RAM_BANK_CR_MTX_RAM_BANK_SIZE_MASK (0x000F0000)
++#define MSVDX_MTX_RAM_BANK_CR_MTX_RAM_BANK_SIZE_SHIFT (16)
+
-+ msgBuffer[msgWordOffset] =
-+ PSB_RMSVDX32 (MSVDX_COMMS_TO_HOST_BUF + (readIndex << 2));
++#define MSVDX_RENDEC_BUFFER_SIZE_RENDEC_BUFFER_SIZE0_MASK (0x0000FFFF)
++#define MSVDX_RENDEC_BUFFER_SIZE_RENDEC_BUFFER_SIZE0_SHIFT (0)
+
-+ msgNumWords = (MEMIO_READ_FIELD (msgBuffer, FWRK_GENMSG_SIZE) + 3) / 4; /* round to nearest word */
++#define MSVDX_RENDEC_BUFFER_SIZE_RENDEC_BUFFER_SIZE1_MASK (0xFFFF0000)
++#define MSVDX_RENDEC_BUFFER_SIZE_RENDEC_BUFFER_SIZE1_SHIFT (16)
+
-+ /*ASSERT(msgNumWords <= sizeof(msgBuffer) / sizeof(uint32_t)); */
++#define MSVDX_RENDEC_CONTROL1_RENDEC_DECODE_START_SIZE_MASK (0x000000FF)
++#define MSVDX_RENDEC_CONTROL1_RENDEC_DECODE_START_SIZE_SHIFT (0)
+
-+ if (++readIndex >= NUM_WORDS_HOST_BUF)
-+ readIndex = 0;
++#define MSVDX_RENDEC_CONTROL1_RENDEC_BURST_SIZE_W_MASK (0x000C0000)
++#define MSVDX_RENDEC_CONTROL1_RENDEC_BURST_SIZE_W_SHIFT (18)
+
-+ for (msgWordOffset++; msgWordOffset < msgNumWords; msgWordOffset++)
-+ {
-+ msgBuffer[msgWordOffset] =
-+ PSB_RMSVDX32 (MSVDX_COMMS_TO_HOST_BUF + (readIndex << 2));
++#define MSVDX_RENDEC_CONTROL1_RENDEC_BURST_SIZE_R_MASK (0x00030000)
++#define MSVDX_RENDEC_CONTROL1_RENDEC_BURST_SIZE_R_SHIFT (16)
+
-+ if (++readIndex >= NUM_WORDS_HOST_BUF)
-+ {
-+ readIndex = 0;
-+ }
-+ }
++#define MSVDX_RENDEC_CONTROL1_RENDEC_EXTERNAL_MEMORY_MASK (0x01000000)
++#define MSVDX_RENDEC_CONTROL1_RENDEC_EXTERNAL_MEMORY_SHIFT (24)
+
-+ /* Update the Read index */
-+ PSB_WMSVDX32 (readIndex, MSVDX_COMMS_TO_HOST_RD_INDEX);
++#define MSVDX_RENDEC_CONTROL0_RENDEC_INITIALISE_MASK (0x00000001)
++#define MSVDX_RENDEC_CONTROL0_RENDEC_INITIALISE_SHIFT (0)
+
-+ if (!dev_priv->msvdx_needs_reset)
-+ switch (MEMIO_READ_FIELD (msgBuffer, FWRK_GENMSG_ID))
-+ {
-+ case VA_MSGID_CMD_HW_PANIC:
-+ case VA_MSGID_CMD_FAILED:
-+ {
-+ uint32_t ui32Fence = MEMIO_READ_FIELD (msgBuffer,
-+ FW_VA_CMD_FAILED_FENCE_VALUE);
-+ uint32_t ui32FaultStatus = MEMIO_READ_FIELD (msgBuffer,
-+ FW_VA_CMD_FAILED_IRQSTATUS);
++#define FWRK_MSGID_START_PSR_HOSTMTX_MSG (0x80) /*!< Start of parser specific Host->MTX messages. */
++#define FWRK_MSGID_START_PSR_MTXHOST_MSG (0xC0) /*!< Start of parser specific MTX->Host messages. */
++#define FWRK_MSGID_PADDING ( 0 )
+
-+ if(MEMIO_READ_FIELD (msgBuffer, FWRK_GENMSG_ID) == VA_MSGID_CMD_HW_PANIC )
-+ PSB_DEBUG_GENERAL
-+ ("MSVDX: VA_MSGID_CMD_HW_PANIC: Msvdx fault detected - Fence: %08x, Status: %08x - resetting and ignoring error\n",
-+ ui32Fence, ui32FaultStatus);
-+ else
-+ PSB_DEBUG_GENERAL
-+ ("MSVDX: VA_MSGID_CMD_FAILED: Msvdx fault detected - Fence: %08x, Status: %08x - resetting and ignoring error\n",
-+ ui32Fence, ui32FaultStatus);
++#define FWRK_GENMSG_SIZE_TYPE uint8_t
++#define FWRK_GENMSG_SIZE_MASK (0xFF)
++#define FWRK_GENMSG_SIZE_SHIFT (0)
++#define FWRK_GENMSG_SIZE_OFFSET (0x0000)
++#define FWRK_GENMSG_ID_TYPE uint8_t
++#define FWRK_GENMSG_ID_MASK (0xFF)
++#define FWRK_GENMSG_ID_SHIFT (0)
++#define FWRK_GENMSG_ID_OFFSET (0x0001)
++#define FWRK_PADMSG_SIZE (2)
+
-+ dev_priv->msvdx_needs_reset = 1;
++/*!
++******************************************************************************
++ This type defines the framework specified message ids
++******************************************************************************/
++enum
++{
++ /*! Sent by the DXVA driver on the host to the mtx firmware.
++ */
++ VA_MSGID_INIT = FWRK_MSGID_START_PSR_HOSTMTX_MSG,
++ VA_MSGID_RENDER,
++ VA_MSGID_DEBLOCK,
++ VA_MSGID_OOLD,
+
-+ if(MEMIO_READ_FIELD (msgBuffer, FWRK_GENMSG_ID) == VA_MSGID_CMD_HW_PANIC)
-+ {
-+ if (dev_priv->
-+ msvdx_current_sequence
-+ - dev_priv->sequence[PSB_ENGINE_VIDEO] > 0x0FFFFFFF)
-+ dev_priv->msvdx_current_sequence++;
-+ PSB_DEBUG_GENERAL
-+ ("MSVDX: Fence ID missing, assuming %08x\n",
-+ dev_priv->msvdx_current_sequence);
-+ }
-+ else
-+ dev_priv->msvdx_current_sequence = ui32Fence;
++ /* Test Messages */
++ VA_MSGID_TEST1,
++ VA_MSGID_TEST2,
+
-+ psb_fence_error (dev,
-+ PSB_ENGINE_VIDEO,
-+ dev_priv->
-+ msvdx_current_sequence,
-+ DRM_FENCE_TYPE_EXE, DRM_CMD_FAILED);
++ /*! Sent by the mtx firmware to itself.
++ */
++ VA_MSGID_RENDER_MC_INTERRUPT,
+
-+ /* Flush the command queue */
-+ psb_msvdx_flush_cmd_queue (dev);
++ /*! Sent by the DXVA firmware on the MTX to the host.
++ */
++ VA_MSGID_CMD_COMPLETED = FWRK_MSGID_START_PSR_MTXHOST_MSG,
++ VA_MSGID_CMD_COMPLETED_BATCH,
++ VA_MSGID_DEBLOCK_REQUIRED,
++ VA_MSGID_TEST_RESPONCE,
++ VA_MSGID_ACK,
+
-+ goto isrExit;
-+ break;
-+ }
-+ case VA_MSGID_CMD_COMPLETED:
-+ {
-+ uint32_t ui32Fence = MEMIO_READ_FIELD (msgBuffer,
-+ FW_VA_CMD_COMPLETED_FENCE_VALUE);
-+ uint32_t ui32Flags =
-+ MEMIO_READ_FIELD (msgBuffer, FW_VA_CMD_COMPLETED_FLAGS);
++ VA_MSGID_CMD_FAILED,
++ VA_MSGID_CMD_UNSUPPORTED,
++ VA_MSGID_CMD_HW_PANIC,
++};
+
-+ PSB_DEBUG_GENERAL
-+ ("msvdx VA_MSGID_CMD_COMPLETED: FenceID: %08x, flags: 0x%x\n",
-+ ui32Fence, ui32Flags);
-+ dev_priv->msvdx_current_sequence = ui32Fence;
++/* MSVDX Firmware interface */
+
-+ psb_fence_handler (dev, PSB_ENGINE_VIDEO);
++#define FW_VA_RENDER_SIZE (32)
+
++// FW_VA_RENDER MSG_SIZE
++#define FW_VA_RENDER_MSG_SIZE_ALIGNMENT (1)
++#define FW_VA_RENDER_MSG_SIZE_TYPE uint8_t
++#define FW_VA_RENDER_MSG_SIZE_MASK (0xFF)
++#define FW_VA_RENDER_MSG_SIZE_LSBMASK (0xFF)
++#define FW_VA_RENDER_MSG_SIZE_OFFSET (0x0000)
++#define FW_VA_RENDER_MSG_SIZE_SHIFT (0)
+
-+ if (ui32Flags & FW_VA_RENDER_HOST_INT)
-+ {
-+ /*Now send the next command from the msvdx cmd queue */
-+ psb_msvdx_dequeue_send (dev);
-+ goto isrExit;
-+ }
-+ break;
-+ }
-+ case VA_MSGID_ACK:
-+ PSB_DEBUG_GENERAL ("msvdx VA_MSGID_ACK\n");
-+ break;
++// FW_VA_RENDER ID
++#define FW_VA_RENDER_ID_ALIGNMENT (1)
++#define FW_VA_RENDER_ID_TYPE uint8_t
++#define FW_VA_RENDER_ID_MASK (0xFF)
++#define FW_VA_RENDER_ID_LSBMASK (0xFF)
++#define FW_VA_RENDER_ID_OFFSET (0x0001)
++#define FW_VA_RENDER_ID_SHIFT (0)
+
-+ case VA_MSGID_TEST1:
-+ PSB_DEBUG_GENERAL ("msvdx VA_MSGID_TEST1\n");
-+ break;
++// FW_VA_RENDER BUFFER_SIZE
++#define FW_VA_RENDER_BUFFER_SIZE_ALIGNMENT (2)
++#define FW_VA_RENDER_BUFFER_SIZE_TYPE uint16_t
++#define FW_VA_RENDER_BUFFER_SIZE_MASK (0x0FFF)
++#define FW_VA_RENDER_BUFFER_SIZE_LSBMASK (0x0FFF)
++#define FW_VA_RENDER_BUFFER_SIZE_OFFSET (0x0002)
++#define FW_VA_RENDER_BUFFER_SIZE_SHIFT (0)
+
-+ case VA_MSGID_TEST2:
-+ PSB_DEBUG_GENERAL ("msvdx VA_MSGID_TEST2\n");
-+ break;
-+ /* Don't need to do anything with these messages */
++// FW_VA_RENDER MMUPTD
++#define FW_VA_RENDER_MMUPTD_ALIGNMENT (4)
++#define FW_VA_RENDER_MMUPTD_TYPE uint32_t
++#define FW_VA_RENDER_MMUPTD_MASK (0xFFFFFFFF)
++#define FW_VA_RENDER_MMUPTD_LSBMASK (0xFFFFFFFF)
++#define FW_VA_RENDER_MMUPTD_OFFSET (0x0004)
++#define FW_VA_RENDER_MMUPTD_SHIFT (0)
+
-+ case VA_MSGID_DEBLOCK_REQUIRED:
-+ {
-+ uint32_t ui32ContextId = MEMIO_READ_FIELD (msgBuffer,
-+ FW_VA_DEBLOCK_REQUIRED_CONTEXT);
++// FW_VA_RENDER LLDMA_ADDRESS
++#define FW_VA_RENDER_LLDMA_ADDRESS_ALIGNMENT (4)
++#define FW_VA_RENDER_LLDMA_ADDRESS_TYPE uint32_t
++#define FW_VA_RENDER_LLDMA_ADDRESS_MASK (0xFFFFFFFF)
++#define FW_VA_RENDER_LLDMA_ADDRESS_LSBMASK (0xFFFFFFFF)
++#define FW_VA_RENDER_LLDMA_ADDRESS_OFFSET (0x0008)
++#define FW_VA_RENDER_LLDMA_ADDRESS_SHIFT (0)
+
-+ /* The BE we now be locked. */
++// FW_VA_RENDER CONTEXT
++#define FW_VA_RENDER_CONTEXT_ALIGNMENT (4)
++#define FW_VA_RENDER_CONTEXT_TYPE uint32_t
++#define FW_VA_RENDER_CONTEXT_MASK (0xFFFFFFFF)
++#define FW_VA_RENDER_CONTEXT_LSBMASK (0xFFFFFFFF)
++#define FW_VA_RENDER_CONTEXT_OFFSET (0x000C)
++#define FW_VA_RENDER_CONTEXT_SHIFT (0)
+
-+ /* Unblock rendec by reading the mtx2mtx end of slice */
-+ (void) PSB_RMSVDX32 (MSVDX_RENDEC_READ_DATA);
++// FW_VA_RENDER FENCE_VALUE
++#define FW_VA_RENDER_FENCE_VALUE_ALIGNMENT (4)
++#define FW_VA_RENDER_FENCE_VALUE_TYPE uint32_t
++#define FW_VA_RENDER_FENCE_VALUE_MASK (0xFFFFFFFF)
++#define FW_VA_RENDER_FENCE_VALUE_LSBMASK (0xFFFFFFFF)
++#define FW_VA_RENDER_FENCE_VALUE_OFFSET (0x0010)
++#define FW_VA_RENDER_FENCE_VALUE_SHIFT (0)
+
-+ PSB_DEBUG_GENERAL
-+ ("msvdx VA_MSGID_DEBLOCK_REQUIRED Context=%08x\n",
-+ ui32ContextId);
-+ goto isrExit;
-+ break;
-+ }
++// FW_VA_RENDER OPERATING_MODE
++#define FW_VA_RENDER_OPERATING_MODE_ALIGNMENT (4)
++#define FW_VA_RENDER_OPERATING_MODE_TYPE uint32_t
++#define FW_VA_RENDER_OPERATING_MODE_MASK (0xFFFFFFFF)
++#define FW_VA_RENDER_OPERATING_MODE_LSBMASK (0xFFFFFFFF)
++#define FW_VA_RENDER_OPERATING_MODE_OFFSET (0x0014)
++#define FW_VA_RENDER_OPERATING_MODE_SHIFT (0)
+
-+ default:
-+ {
-+ PSB_DEBUG_GENERAL
-+ ("ERROR: msvdx Unknown message from MTX \n");
-+ }
-+ break;
++// FW_VA_RENDER FIRST_MB_IN_SLICE
++#define FW_VA_RENDER_FIRST_MB_IN_SLICE_ALIGNMENT (2)
++#define FW_VA_RENDER_FIRST_MB_IN_SLICE_TYPE uint16_t
++#define FW_VA_RENDER_FIRST_MB_IN_SLICE_MASK (0xFFFF)
++#define FW_VA_RENDER_FIRST_MB_IN_SLICE_LSBMASK (0xFFFF)
++#define FW_VA_RENDER_FIRST_MB_IN_SLICE_OFFSET (0x0018)
++#define FW_VA_RENDER_FIRST_MB_IN_SLICE_SHIFT (0)
+
-+ }
-+ }
-+ else
-+ {
-+ /* Get out of here if nothing */
-+ break;
-+ }
-+ }
-+isrExit:
++// FW_VA_RENDER LAST_MB_IN_FRAME
++#define FW_VA_RENDER_LAST_MB_IN_FRAME_ALIGNMENT (2)
++#define FW_VA_RENDER_LAST_MB_IN_FRAME_TYPE uint16_t
++#define FW_VA_RENDER_LAST_MB_IN_FRAME_MASK (0xFFFF)
++#define FW_VA_RENDER_LAST_MB_IN_FRAME_LSBMASK (0xFFFF)
++#define FW_VA_RENDER_LAST_MB_IN_FRAME_OFFSET (0x001A)
++#define FW_VA_RENDER_LAST_MB_IN_FRAME_SHIFT (0)
+
-+#if 1
-+ if (!dev_priv->msvdx_busy)
-+ {
-+ /* check that clocks are enabled before reading VLR */
-+ if( PSB_RMSVDX32( MSVDX_MAN_CLK_ENABLE ) != (clk_enable_all) )
-+ PSB_WMSVDX32 (clk_enable_all, MSVDX_MAN_CLK_ENABLE);
++// FW_VA_RENDER FLAGS
++#define FW_VA_RENDER_FLAGS_ALIGNMENT (4)
++#define FW_VA_RENDER_FLAGS_TYPE uint32_t
++#define FW_VA_RENDER_FLAGS_MASK (0xFFFFFFFF)
++#define FW_VA_RENDER_FLAGS_LSBMASK (0xFFFFFFFF)
++#define FW_VA_RENDER_FLAGS_OFFSET (0x001C)
++#define FW_VA_RENDER_FLAGS_SHIFT (0)
+
-+ /* If the firmware says the hardware is idle and the CCB is empty then we can power down */
-+ {
-+ uint32_t ui32FWStatus = PSB_RMSVDX32( MSVDX_COMMS_FW_STATUS );
-+ uint32_t ui32CCBRoff = PSB_RMSVDX32 ( MSVDX_COMMS_TO_MTX_RD_INDEX );
-+ uint32_t ui32CCBWoff = PSB_RMSVDX32 ( MSVDX_COMMS_TO_MTX_WRT_INDEX );
++#define FW_VA_CMD_COMPLETED_SIZE (12)
+
-+ if( (ui32FWStatus & MSVDX_FW_STATUS_HW_IDLE) && (ui32CCBRoff == ui32CCBWoff))
-+ {
-+ PSB_DEBUG_GENERAL("MSVDX_CLOCK: Setting clock to minimal...\n");
-+ PSB_WMSVDX32 (clk_enable_minimal, MSVDX_MAN_CLK_ENABLE);
-+ }
-+ }
-+ }
-+#endif
-+ DRM_MEMORYBARRIER ();
-+}
++// FW_VA_CMD_COMPLETED MSG_SIZE
++#define FW_VA_CMD_COMPLETED_MSG_SIZE_ALIGNMENT (1)
++#define FW_VA_CMD_COMPLETED_MSG_SIZE_TYPE uint8_t
++#define FW_VA_CMD_COMPLETED_MSG_SIZE_MASK (0xFF)
++#define FW_VA_CMD_COMPLETED_MSG_SIZE_LSBMASK (0xFF)
++#define FW_VA_CMD_COMPLETED_MSG_SIZE_OFFSET (0x0000)
++#define FW_VA_CMD_COMPLETED_MSG_SIZE_SHIFT (0)
+
-+void
-+psb_msvdx_lockup (struct drm_psb_private *dev_priv,
-+ int *msvdx_lockup, int *msvdx_idle)
-+{
-+ unsigned long irq_flags;
-+// struct psb_scheduler *scheduler = &dev_priv->scheduler;
++// FW_VA_CMD_COMPLETED ID
++#define FW_VA_CMD_COMPLETED_ID_ALIGNMENT (1)
++#define FW_VA_CMD_COMPLETED_ID_TYPE uint8_t
++#define FW_VA_CMD_COMPLETED_ID_MASK (0xFF)
++#define FW_VA_CMD_COMPLETED_ID_LSBMASK (0xFF)
++#define FW_VA_CMD_COMPLETED_ID_OFFSET (0x0001)
++#define FW_VA_CMD_COMPLETED_ID_SHIFT (0)
+
-+ spin_lock_irqsave (&dev_priv->msvdx_lock, irq_flags);
-+ *msvdx_lockup = 0;
-+ *msvdx_idle = 1;
++// FW_VA_CMD_COMPLETED FENCE_VALUE
++#define FW_VA_CMD_COMPLETED_FENCE_VALUE_ALIGNMENT (4)
++#define FW_VA_CMD_COMPLETED_FENCE_VALUE_TYPE uint32_t
++#define FW_VA_CMD_COMPLETED_FENCE_VALUE_MASK (0xFFFFFFFF)
++#define FW_VA_CMD_COMPLETED_FENCE_VALUE_LSBMASK (0xFFFFFFFF)
++#define FW_VA_CMD_COMPLETED_FENCE_VALUE_OFFSET (0x0004)
++#define FW_VA_CMD_COMPLETED_FENCE_VALUE_SHIFT (0)
+
-+ if (!dev_priv->has_msvdx)
-+ {
-+ spin_unlock_irqrestore (&dev_priv->msvdx_lock, irq_flags);
-+ return;
-+ }
-+#if 0
-+ PSB_DEBUG_GENERAL ("MSVDXTimer: current_sequence:%d "
-+ "last_sequence:%d and last_submitted_sequence :%d\n",
-+ dev_priv->msvdx_current_sequence,
-+ dev_priv->msvdx_last_sequence,
-+ dev_priv->sequence[PSB_ENGINE_VIDEO]);
-+#endif
-+ if (dev_priv->msvdx_current_sequence -
-+ dev_priv->sequence[PSB_ENGINE_VIDEO] > 0x0FFFFFFF)
-+ {
++// FW_VA_CMD_COMPLETED FLAGS
++#define FW_VA_CMD_COMPLETED_FLAGS_ALIGNMENT (4)
++#define FW_VA_CMD_COMPLETED_FLAGS_TYPE uint32_t
++#define FW_VA_CMD_COMPLETED_FLAGS_MASK (0xFFFFFFFF)
++#define FW_VA_CMD_COMPLETED_FLAGS_LSBMASK (0xFFFFFFFF)
++#define FW_VA_CMD_COMPLETED_FLAGS_OFFSET (0x0008)
++#define FW_VA_CMD_COMPLETED_FLAGS_SHIFT (0)
+
-+ if (dev_priv->msvdx_current_sequence == dev_priv->msvdx_last_sequence)
-+ {
-+ PSB_DEBUG_GENERAL
-+ ("MSVDXTimer: msvdx locked-up for sequence:%d\n",
-+ dev_priv->msvdx_current_sequence);
-+ *msvdx_lockup = 1;
-+ }
-+ else
-+ {
-+ PSB_DEBUG_GENERAL ("MSVDXTimer: msvdx responded fine so far...\n");
-+ dev_priv->msvdx_last_sequence = dev_priv->msvdx_current_sequence;
-+ *msvdx_idle = 0;
-+ }
-+ if (dev_priv->msvdx_start_idle)
-+ dev_priv->msvdx_start_idle = 0;
-+ }
-+ else
-+ {
-+ if (dev_priv->msvdx_needs_reset == 0)
-+ {
-+ if (dev_priv->msvdx_start_idle && (dev_priv->msvdx_finished_sequence == dev_priv->msvdx_current_sequence))
-+ {
-+ //if (dev_priv->msvdx_idle_start_jiffies + MSVDX_MAX_IDELTIME >= jiffies)
-+ if (time_after_eq(jiffies, dev_priv->msvdx_idle_start_jiffies + MSVDX_MAX_IDELTIME))
-+ {
-+ printk("set the msvdx clock to 0 in the %s\n", __FUNCTION__);
-+ PSB_WMSVDX32 (0, MSVDX_MAN_CLK_ENABLE);
-+ dev_priv->msvdx_needs_reset = 1;
-+ }
-+ else
-+ {
-+ *msvdx_idle = 0;
-+ }
-+ }
-+ else
-+ {
-+ dev_priv->msvdx_start_idle = 1;
-+ dev_priv->msvdx_idle_start_jiffies = jiffies;
-+ dev_priv->msvdx_finished_sequence = dev_priv->msvdx_current_sequence;
-+ *msvdx_idle = 0;
-+ }
-+ }
-+ }
-+ spin_unlock_irqrestore (&dev_priv->msvdx_lock, irq_flags);
-+}
-Index: linux-2.6.28/drivers/gpu/drm/psb/psb_msvdx.h
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/psb/psb_msvdx.h 2009-02-12 09:14:42.000000000 +0000
-@@ -0,0 +1,564 @@
-+/**************************************************************************
-+ *
-+ * Copyright (c) 2007 Intel Corporation, Hillsboro, OR, USA
-+ * Copyright (c) Imagination Technologies Limited, UK
-+ * All Rights Reserved.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the
-+ * "Software"), to deal in the Software without restriction, including
-+ * without limitation the rights to use, copy, modify, merge, publish,
-+ * distribute, sub license, and/or sell copies of the Software, and to
-+ * permit persons to whom the Software is furnished to do so, subject to
-+ * the following conditions:
-+ *
-+ * The above copyright notice and this permission notice (including the
-+ * next paragraph) shall be included in all copies or substantial portions
-+ * of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
-+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ **************************************************************************/
++#define FW_VA_CMD_FAILED_SIZE (12)
+
-+#ifndef _PSB_MSVDX_H_
-+#define _PSB_MSVDX_H_
++// FW_VA_CMD_FAILED MSG_SIZE
++#define FW_VA_CMD_FAILED_MSG_SIZE_ALIGNMENT (1)
++#define FW_VA_CMD_FAILED_MSG_SIZE_TYPE uint8_t
++#define FW_VA_CMD_FAILED_MSG_SIZE_MASK (0xFF)
++#define FW_VA_CMD_FAILED_MSG_SIZE_LSBMASK (0xFF)
++#define FW_VA_CMD_FAILED_MSG_SIZE_OFFSET (0x0000)
++#define FW_VA_CMD_FAILED_MSG_SIZE_SHIFT (0)
+
-+#define assert(expr) \
-+ if(unlikely(!(expr))) { \
-+ printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
-+ #expr,__FILE__,__FUNCTION__,__LINE__); \
-+ }
++// FW_VA_CMD_FAILED ID
++#define FW_VA_CMD_FAILED_ID_ALIGNMENT (1)
++#define FW_VA_CMD_FAILED_ID_TYPE uint8_t
++#define FW_VA_CMD_FAILED_ID_MASK (0xFF)
++#define FW_VA_CMD_FAILED_ID_LSBMASK (0xFF)
++#define FW_VA_CMD_FAILED_ID_OFFSET (0x0001)
++#define FW_VA_CMD_FAILED_ID_SHIFT (0)
+
-+#define PSB_ASSERT(x) assert (x)
-+#define IMG_ASSERT(x) assert (x)
++// FW_VA_CMD_FAILED FLAGS
++#define FW_VA_CMD_FAILED_FLAGS_ALIGNMENT (2)
++#define FW_VA_CMD_FAILED_FLAGS_TYPE uint16_t
++#define FW_VA_CMD_FAILED_FLAGS_MASK (0xFFFF)
++#define FW_VA_CMD_FAILED_FLAGS_LSBMASK (0xFFFF)
++#define FW_VA_CMD_FAILED_FLAGS_OFFSET (0x0002)
++#define FW_VA_CMD_FAILED_FLAGS_SHIFT (0)
+
-+#include "psb_drv.h"
-+int
-+psb_wait_for_register (struct drm_psb_private *dev_priv,
-+ uint32_t ui32Offset,
-+ uint32_t ui32Value, uint32_t ui32Enable);
++// FW_VA_CMD_FAILED FENCE_VALUE
++#define FW_VA_CMD_FAILED_FENCE_VALUE_ALIGNMENT (4)
++#define FW_VA_CMD_FAILED_FENCE_VALUE_TYPE uint32_t
++#define FW_VA_CMD_FAILED_FENCE_VALUE_MASK (0xFFFFFFFF)
++#define FW_VA_CMD_FAILED_FENCE_VALUE_LSBMASK (0xFFFFFFFF)
++#define FW_VA_CMD_FAILED_FENCE_VALUE_OFFSET (0x0004)
++#define FW_VA_CMD_FAILED_FENCE_VALUE_SHIFT (0)
+
-+void psb_msvdx_mtx_interrupt (struct drm_device *dev);
-+int psb_msvdx_init (struct drm_device *dev);
-+int psb_msvdx_uninit (struct drm_device *dev);
-+int psb_msvdx_reset (struct drm_psb_private *dev_priv);
-+uint32_t psb_get_default_pd_addr (struct psb_mmu_driver *driver);
-+int psb_mtx_send (struct drm_psb_private *dev_priv, const void *pvMsg);
-+void psb_msvdx_irq_preinstall (struct drm_psb_private *dev_priv);
-+void psb_msvdx_irq_postinstall (struct drm_psb_private *dev_priv);
-+void psb_msvdx_flush_cmd_queue (struct drm_device *dev);
-+extern void psb_msvdx_lockup (struct drm_psb_private *dev_priv,
-+ int *msvdx_lockup, int *msvdx_idle);
-+#define MSVDX_DEVICE_NODE_FLAGS_MMU_NONOPT_INV 2 /* Non-Optimal Invalidation is not default */
-+#define FW_VA_RENDER_HOST_INT 0x00004000
-+#define MSVDX_DEVICE_NODE_FLAGS_MMU_HW_INVALIDATION 0x00000020
++// FW_VA_CMD_FAILED IRQSTATUS
++#define FW_VA_CMD_FAILED_IRQSTATUS_ALIGNMENT (4)
++#define FW_VA_CMD_FAILED_IRQSTATUS_TYPE uint32_t
++#define FW_VA_CMD_FAILED_IRQSTATUS_MASK (0xFFFFFFFF)
++#define FW_VA_CMD_FAILED_IRQSTATUS_LSBMASK (0xFFFFFFFF)
++#define FW_VA_CMD_FAILED_IRQSTATUS_OFFSET (0x0008)
++#define FW_VA_CMD_FAILED_IRQSTATUS_SHIFT (0)
+
-+#define MSVDX_DEVICE_NODE_FLAG_BRN23154_BLOCK_ON_FE 0x00000200
++#define FW_VA_DEBLOCK_REQUIRED_SIZE (8)
+
-+#define MSVDX_DEVICE_NODE_FLAGS_DEFAULT_D0 (MSVDX_DEVICE_NODE_FLAGS_MMU_NONOPT_INV | MSVDX_DEVICE_NODE_FLAGS_MMU_HW_INVALIDATION \
-+ | MSVDX_DEVICE_NODE_FLAG_BRN23154_BLOCK_ON_FE)
-+#define MSVDX_DEVICE_NODE_FLAGS_DEFAULT_D1 (MSVDX_DEVICE_NODE_FLAGS_MMU_HW_INVALIDATION \
-+ | MSVDX_DEVICE_NODE_FLAG_BRN23154_BLOCK_ON_FE)
++// FW_VA_DEBLOCK_REQUIRED MSG_SIZE
++#define FW_VA_DEBLOCK_REQUIRED_MSG_SIZE_ALIGNMENT (1)
++#define FW_VA_DEBLOCK_REQUIRED_MSG_SIZE_TYPE uint8_t
++#define FW_VA_DEBLOCK_REQUIRED_MSG_SIZE_MASK (0xFF)
++#define FW_VA_DEBLOCK_REQUIRED_MSG_SIZE_LSBMASK (0xFF)
++#define FW_VA_DEBLOCK_REQUIRED_MSG_SIZE_OFFSET (0x0000)
++#define FW_VA_DEBLOCK_REQUIRED_MSG_SIZE_SHIFT (0)
+
++// FW_VA_DEBLOCK_REQUIRED ID
++#define FW_VA_DEBLOCK_REQUIRED_ID_ALIGNMENT (1)
++#define FW_VA_DEBLOCK_REQUIRED_ID_TYPE uint8_t
++#define FW_VA_DEBLOCK_REQUIRED_ID_MASK (0xFF)
++#define FW_VA_DEBLOCK_REQUIRED_ID_LSBMASK (0xFF)
++#define FW_VA_DEBLOCK_REQUIRED_ID_OFFSET (0x0001)
++#define FW_VA_DEBLOCK_REQUIRED_ID_SHIFT (0)
+
-+#define POULSBO_D0 0x5
-+#define POULSBO_D1 0x6
-+#define PSB_REVID_OFFSET 0x8
++// FW_VA_DEBLOCK_REQUIRED CONTEXT
++#define FW_VA_DEBLOCK_REQUIRED_CONTEXT_ALIGNMENT (4)
++#define FW_VA_DEBLOCK_REQUIRED_CONTEXT_TYPE uint32_t
++#define FW_VA_DEBLOCK_REQUIRED_CONTEXT_MASK (0xFFFFFFFF)
++#define FW_VA_DEBLOCK_REQUIRED_CONTEXT_LSBMASK (0xFFFFFFFF)
++#define FW_VA_DEBLOCK_REQUIRED_CONTEXT_OFFSET (0x0004)
++#define FW_VA_DEBLOCK_REQUIRED_CONTEXT_SHIFT (0)
+
-+#define MSVDX_FW_STATUS_HW_IDLE 0x00000001 /* There is no work currently underway on the hardware*/
++#define FW_VA_HW_PANIC_SIZE (12)
+
-+#define clk_enable_all MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_CORE_MAN_CLK_ENABLE_MASK | \
-+ MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDEB_PROCESS_MAN_CLK_ENABLE_MASK | \
-+ MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDEB_ACCESS_MAN_CLK_ENABLE_MASK | \
-+ MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDMC_MAN_CLK_ENABLE_MASK | \
-+ MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VEC_ENTDEC_MAN_CLK_ENABLE_MASK | \
-+ MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VEC_ITRANS_MAN_CLK_ENABLE_MASK | \
-+ MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_MTX_MAN_CLK_ENABLE_MASK
++// FW_VA_HW_PANIC FLAGS
++#define FW_VA_HW_PANIC_FLAGS_ALIGNMENT (2)
++#define FW_VA_HW_PANIC_FLAGS_TYPE uint16_t
++#define FW_VA_HW_PANIC_FLAGS_MASK (0xFFFF)
++#define FW_VA_HW_PANIC_FLAGS_LSBMASK (0xFFFF)
++#define FW_VA_HW_PANIC_FLAGS_OFFSET (0x0002)
++#define FW_VA_HW_PANIC_FLAGS_SHIFT (0)
+
-+#define clk_enable_minimal MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_CORE_MAN_CLK_ENABLE_MASK | \
-+ MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_MTX_MAN_CLK_ENABLE_MASK
++// FW_VA_HW_PANIC MSG_SIZE
++#define FW_VA_HW_PANIC_MSG_SIZE_ALIGNMENT (1)
++#define FW_VA_HW_PANIC_MSG_SIZE_TYPE uint8_t
++#define FW_VA_HW_PANIC_MSG_SIZE_MASK (0xFF)
++#define FW_VA_HW_PANIC_MSG_SIZE_LSBMASK (0xFF)
++#define FW_VA_HW_PANIC_MSG_SIZE_OFFSET (0x0000)
++#define FW_VA_HW_PANIC_MSG_SIZE_SHIFT (0)
+
-+#define clk_enable_auto MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDEB_PROCESS_AUTO_CLK_ENABLE_MASK | \
-+ MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDEB_ACCESS_AUTO_CLK_ENABLE_MASK | \
-+ MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDMC_AUTO_CLK_ENABLE_MASK | \
-+ MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VEC_ENTDEC_AUTO_CLK_ENABLE_MASK | \
-+ MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VEC_ITRANS_AUTO_CLK_ENABLE_MASK | \
-+ MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_CORE_MAN_CLK_ENABLE_MASK | \
-+ MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_MTX_MAN_CLK_ENABLE_MASK
++// FW_VA_HW_PANIC ID
++#define FW_VA_HW_PANIC_ID_ALIGNMENT (1)
++#define FW_VA_HW_PANIC_ID_TYPE uint8_t
++#define FW_VA_HW_PANIC_ID_MASK (0xFF)
++#define FW_VA_HW_PANIC_ID_LSBMASK (0xFF)
++#define FW_VA_HW_PANIC_ID_OFFSET (0x0001)
++#define FW_VA_HW_PANIC_ID_SHIFT (0)
+
-+#define msvdx_sw_reset_all MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_SOFT_RESET_MASK | \
-+ MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_FE_SOFT_RESET_MASK | \
-+ MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_BE_SOFT_RESET_MASK | \
-+ MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_VEC_MEMIF_SOFT_RESET_MASK | \
-+ MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_VEC_RENDEC_DEC_SOFT_RESET_MASK
++// FW_VA_HW_PANIC FENCE_VALUE
++#define FW_VA_HW_PANIC_FENCE_VALUE_ALIGNMENT (4)
++#define FW_VA_HW_PANIC_FENCE_VALUE_TYPE uint32_t
++#define FW_VA_HW_PANIC_FENCE_VALUE_MASK (0xFFFFFFFF)
++#define FW_VA_HW_PANIC_FENCE_VALUE_LSBMASK (0xFFFFFFFF)
++#define FW_VA_HW_PANIC_FENCE_VALUE_OFFSET (0x0004)
++#define FW_VA_HW_PANIC_FENCE_VALUE_SHIFT (0)
+
++// FW_VA_HW_PANIC IRQSTATUS
++#define FW_VA_HW_PANIC_IRQSTATUS_ALIGNMENT (4)
++#define FW_VA_HW_PANIC_IRQSTATUS_TYPE uint32_t
++#define FW_VA_HW_PANIC_IRQSTATUS_MASK (0xFFFFFFFF)
++#define FW_VA_HW_PANIC_IRQSTATUS_LSBMASK (0xFFFFFFFF)
++#define FW_VA_HW_PANIC_IRQSTATUS_OFFSET (0x0008)
++#define FW_VA_HW_PANIC_IRQSTATUS_SHIFT (0)
+
-+#define PCI_PORT5_REG80_FFUSE 0xD0058000
-+#define MTX_CODE_BASE (0x80900000)
-+#define MTX_DATA_BASE (0x82880000)
-+#define PC_START_ADDRESS (0x80900000)
++#endif
+Index: linux-2.6.28/drivers/gpu/drm/psb/psb_msvdxinit.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.28/drivers/gpu/drm/psb/psb_msvdxinit.c 2009-02-12 09:14:42.000000000 +0000
+@@ -0,0 +1,625 @@
++/**
++ * file psb_msvdxinit.c
++ * MSVDX initialization and mtx-firmware upload
++ *
++ */
+
-+#define MTX_CORE_CODE_MEM (0x10 )
-+#define MTX_CORE_DATA_MEM (0x18 )
++/**************************************************************************
++ *
++ * Copyright (c) 2007 Intel Corporation, Hillsboro, OR, USA
++ * Copyright (c) Imagination Technologies Limited, UK
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
++ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
++ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ **************************************************************************/
+
-+#define MTX_INTERNAL_REG( R_SPECIFIER , U_SPECIFIER ) ( ((R_SPECIFIER)<<4) | (U_SPECIFIER) )
-+#define MTX_PC MTX_INTERNAL_REG( 0 , 5 )
++#include "drmP.h"
++#include "drm.h"
++#include "psb_drv.h"
++#include "psb_msvdx.h"
++#include <linux/firmware.h>
+
-+#define RENDEC_A_SIZE ( 2 * 1024* 1024 )
-+#define RENDEC_B_SIZE ( RENDEC_A_SIZE / 4 )
++/*MSVDX FW header*/
++struct msvdx_fw
++{
++ uint32_t ver;
++ uint32_t text_size;
++ uint32_t data_size;
++ uint32_t data_location;
++};
+
-+#define MEMIO_READ_FIELD(vpMem, field) \
-+ ((uint32_t)(((*((field##_TYPE *)(((uint32_t)vpMem) + field##_OFFSET))) & field##_MASK) >> field##_SHIFT))
++int
++psb_wait_for_register (struct drm_psb_private *dev_priv,
++ uint32_t ui32Offset,
++ uint32_t ui32Value, uint32_t ui32Enable)
++{
++ uint32_t ui32Temp;
++ uint32_t ui32PollCount = 1000;
++ while (ui32PollCount)
++ {
++ ui32Temp = PSB_RMSVDX32 (ui32Offset);
++ if (ui32Value == (ui32Temp & ui32Enable)) /* All the bits are reset */
++ return 0; /* So exit */
+
-+#define MEMIO_WRITE_FIELD(vpMem, field, ui32Value) \
-+ (*((field##_TYPE *)(((uint32_t)vpMem) + field##_OFFSET))) = \
-+ ((*((field##_TYPE *)(((uint32_t)vpMem) + field##_OFFSET))) & (field##_TYPE)~field##_MASK) | \
-+ (field##_TYPE)(( (uint32_t) (ui32Value) << field##_SHIFT) & field##_MASK);
++ /* Wait a bit */
++ DRM_UDELAY (100);
++ ui32PollCount--;
++ }
++ PSB_DEBUG_GENERAL
++ ("MSVDX: Timeout while waiting for register %08x: expecting %08x (mask %08x), got %08x\n",
++ ui32Offset, ui32Value, ui32Enable, ui32Temp);
++ return 1;
++}
+
-+#define MEMIO_WRITE_FIELD_LITE(vpMem, field, ui32Value) \
-+ (*((field##_TYPE *)(((uint32_t)vpMem) + field##_OFFSET))) = \
-+ ((*((field##_TYPE *)(((uint32_t)vpMem) + field##_OFFSET))) | \
-+ (field##_TYPE) (( (uint32_t) (ui32Value) << field##_SHIFT)) );
++int
++psb_poll_mtx_irq (struct drm_psb_private *dev_priv)
++{
++ int ret = 0;
++ uint32_t MtxInt = 0;
++ REGIO_WRITE_FIELD_LITE (MtxInt, MSVDX_INTERRUPT_STATUS, CR_MTX_IRQ, 1);
+
-+#define REGIO_READ_FIELD(ui32RegValue, reg, field) \
-+ ((ui32RegValue & reg##_##field##_MASK) >> reg##_##field##_SHIFT)
++ ret = psb_wait_for_register (dev_priv, MSVDX_INTERRUPT_STATUS, MtxInt, /* Required value */
++ MtxInt /* Enabled bits */ );
++ if (ret)
++ {
++ PSB_DEBUG_GENERAL
++ ("MSVDX: Error Mtx did not return int within a resonable time\n");
+
-+#define REGIO_WRITE_FIELD(ui32RegValue, reg, field, ui32Value) \
-+ (ui32RegValue) = \
-+ ((ui32RegValue) & ~(reg##_##field##_MASK)) | \
-+ (((ui32Value) << (reg##_##field##_SHIFT)) & (reg##_##field##_MASK));
++ return ret;
++ }
+
-+#define REGIO_WRITE_FIELD_LITE(ui32RegValue, reg, field, ui32Value) \
-+ (ui32RegValue) = \
-+ ( (ui32RegValue) | ( (ui32Value) << (reg##_##field##_SHIFT) ) );
++ PSB_DEBUG_GENERAL ("MSVDX: Got MTX Int\n");
+
-+#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_CORE_MAN_CLK_ENABLE_MASK (0x00000001)
-+#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDEB_PROCESS_MAN_CLK_ENABLE_MASK (0x00000002)
-+#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDEB_ACCESS_MAN_CLK_ENABLE_MASK (0x00000004)
-+#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDMC_MAN_CLK_ENABLE_MASK (0x00000008)
-+#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VEC_ENTDEC_MAN_CLK_ENABLE_MASK (0x00000010)
-+#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VEC_ITRANS_MAN_CLK_ENABLE_MASK (0x00000020)
-+#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_MTX_MAN_CLK_ENABLE_MASK (0x00000040)
-+#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDEB_ACCESS_AUTO_CLK_ENABLE_MASK (0x00040000)
-+#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDMC_AUTO_CLK_ENABLE_MASK (0x00080000)
-+#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VEC_ENTDEC_AUTO_CLK_ENABLE_MASK (0x00100000)
-+#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VEC_ITRANS_AUTO_CLK_ENABLE_MASK (0x00200000)
-+#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_SOFT_RESET_MASK (0x00000100)
-+#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_FE_SOFT_RESET_MASK (0x00010000)
-+#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_BE_SOFT_RESET_MASK (0x00100000)
-+#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_VEC_MEMIF_SOFT_RESET_MASK (0x01000000)
-+#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_VEC_RENDEC_DEC_SOFT_RESET_MASK (0x10000000)
++ /* Got it so clear the bit */
++ PSB_WMSVDX32 (MtxInt, MSVDX_INTERRUPT_CLEAR);
+
-+/* MTX registers */
-+#define MSVDX_MTX_ENABLE (0x0000)
-+#define MSVDX_MTX_KICKI (0x0088)
-+#define MSVDX_MTX_REGISTER_READ_WRITE_REQUEST (0x00FC)
-+#define MSVDX_MTX_REGISTER_READ_WRITE_DATA (0x00F8)
-+#define MSVDX_MTX_RAM_ACCESS_DATA_TRANSFER (0x0104)
-+#define MSVDX_MTX_RAM_ACCESS_CONTROL (0x0108)
-+#define MSVDX_MTX_RAM_ACCESS_STATUS (0x010C)
-+#define MSVDX_MTX_SOFT_RESET (0x0200)
-+
-+/* MSVDX registers */
-+#define MSVDX_CONTROL (0x0600)
-+#define MSVDX_INTERRUPT_CLEAR (0x060C)
-+#define MSVDX_INTERRUPT_STATUS (0x0608)
-+#define MSVDX_HOST_INTERRUPT_ENABLE (0x0610)
-+#define MSVDX_MMU_CONTROL0 (0x0680)
-+#define MSVDX_MTX_RAM_BANK (0x06F0)
-+#define MSVDX_MAN_CLK_ENABLE (0x0620)
-+
-+/* RENDEC registers */
-+#define MSVDX_RENDEC_CONTROL0 (0x0868)
-+#define MSVDX_RENDEC_CONTROL1 (0x086C)
-+#define MSVDX_RENDEC_BUFFER_SIZE (0x0870)
-+#define MSVDX_RENDEC_BASE_ADDR0 (0x0874)
-+#define MSVDX_RENDEC_BASE_ADDR1 (0x0878)
-+#define MSVDX_RENDEC_READ_DATA (0x0898)
-+#define MSVDX_RENDEC_CONTEXT0 (0x0950)
-+#define MSVDX_RENDEC_CONTEXT1 (0x0954)
-+#define MSVDX_RENDEC_CONTEXT2 (0x0958)
-+#define MSVDX_RENDEC_CONTEXT3 (0x095C)
-+#define MSVDX_RENDEC_CONTEXT4 (0x0960)
-+#define MSVDX_RENDEC_CONTEXT5 (0x0964)
++ return ret;
++}
+
-+/*
-+ * This defines the MSVDX communication buffer
-+ */
-+#define MSVDX_COMMS_SIGNATURE_VALUE (0xA5A5A5A5) /*!< Signature value */
-+#define NUM_WORDS_HOST_BUF (100) /*!< Host buffer size (in 32-bit words) */
-+#define NUM_WORDS_MTX_BUF (100) /*!< MTX buffer size (in 32-bit words) */
++void
++psb_write_mtx_core_reg (struct drm_psb_private *dev_priv,
++ const uint32_t ui32CoreRegister,
++ const uint32_t ui32Val)
++{
++ uint32_t ui32Reg = 0;
+
-+#define MSVDX_COMMS_AREA_ADDR (0x02cc0)
++ /* Put data in MTX_RW_DATA */
++ PSB_WMSVDX32 (ui32Val, MSVDX_MTX_REGISTER_READ_WRITE_DATA);
+
-+#define MSVDX_COMMS_FW_STATUS (MSVDX_COMMS_AREA_ADDR - 0x10)
-+#define MSVDX_COMMS_SCRATCH (MSVDX_COMMS_AREA_ADDR - 0x08)
-+#define MSVDX_COMMS_MSG_COUNTER (MSVDX_COMMS_AREA_ADDR - 0x04)
-+#define MSVDX_COMMS_SIGNATURE (MSVDX_COMMS_AREA_ADDR + 0x00)
-+#define MSVDX_COMMS_TO_HOST_BUF_SIZE (MSVDX_COMMS_AREA_ADDR + 0x04)
-+#define MSVDX_COMMS_TO_HOST_RD_INDEX (MSVDX_COMMS_AREA_ADDR + 0x08)
-+#define MSVDX_COMMS_TO_HOST_WRT_INDEX (MSVDX_COMMS_AREA_ADDR + 0x0C)
-+#define MSVDX_COMMS_TO_MTX_BUF_SIZE (MSVDX_COMMS_AREA_ADDR + 0x10)
-+#define MSVDX_COMMS_TO_MTX_RD_INDEX (MSVDX_COMMS_AREA_ADDR + 0x14)
-+#define MSVDX_COMMS_OFFSET_FLAGS (MSVDX_COMMS_AREA_ADDR + 0x18)
-+#define MSVDX_COMMS_TO_MTX_WRT_INDEX (MSVDX_COMMS_AREA_ADDR + 0x1C)
-+#define MSVDX_COMMS_TO_HOST_BUF (MSVDX_COMMS_AREA_ADDR + 0x20)
-+#define MSVDX_COMMS_TO_MTX_BUF (MSVDX_COMMS_TO_HOST_BUF + (NUM_WORDS_HOST_BUF << 2))
++ /* DREADY is set to 0 and request a write */
++ ui32Reg = ui32CoreRegister;
++ REGIO_WRITE_FIELD_LITE (ui32Reg, MSVDX_MTX_REGISTER_READ_WRITE_REQUEST,
++ MTX_RNW, 0);
++ REGIO_WRITE_FIELD_LITE (ui32Reg, MSVDX_MTX_REGISTER_READ_WRITE_REQUEST,
++ MTX_DREADY, 0);
++ PSB_WMSVDX32 (ui32Reg, MSVDX_MTX_REGISTER_READ_WRITE_REQUEST);
+
-+#define MSVDX_COMMS_AREA_END (MSVDX_COMMS_TO_MTX_BUF + (NUM_WORDS_HOST_BUF << 2))
++ psb_wait_for_register (dev_priv, MSVDX_MTX_REGISTER_READ_WRITE_REQUEST, MSVDX_MTX_REGISTER_READ_WRITE_REQUEST_MTX_DREADY_MASK, /* Required Value */
++ MSVDX_MTX_REGISTER_READ_WRITE_REQUEST_MTX_DREADY_MASK);
++}
+
-+#if (MSVDX_COMMS_AREA_END != 0x03000)
-+#error
-+#endif
++void
++psb_upload_fw (struct drm_psb_private *dev_priv, const uint32_t ui32DataMem,
++ uint32_t ui32RamBankSize, uint32_t ui32Address,
++ const unsigned int uiWords, const uint32_t * const pui32Data)
++{
++ uint32_t ui32Loop, ui32Ctrl, ui32RamId, ui32Addr, ui32CurrBank =
++ (uint32_t) ~ 0;
++ uint32_t ui32AccessControl;
+
-+#define MSVDX_MTX_REGISTER_READ_WRITE_REQUEST_MTX_DREADY_MASK (0x80000000)
-+#define MSVDX_MTX_REGISTER_READ_WRITE_REQUEST_MTX_DREADY_SHIFT (31)
++ /* Save the access control register... */
++ ui32AccessControl = PSB_RMSVDX32 (MSVDX_MTX_RAM_ACCESS_CONTROL);
+
-+#define MSVDX_MTX_REGISTER_READ_WRITE_REQUEST_MTX_RNW_MASK (0x00010000)
-+#define MSVDX_MTX_REGISTER_READ_WRITE_REQUEST_MTX_RNW_SHIFT (16)
++ /* Wait for MCMSTAT to become be idle 1 */
++ psb_wait_for_register (dev_priv, MSVDX_MTX_RAM_ACCESS_STATUS, 1, /* Required Value */
++ 0xffffffff /* Enables */ );
+
-+#define MSVDX_MTX_RAM_ACCESS_CONTROL_MTX_MCMID_MASK (0x0FF00000)
-+#define MSVDX_MTX_RAM_ACCESS_CONTROL_MTX_MCMID_SHIFT (20)
++ for (ui32Loop = 0; ui32Loop < uiWords; ui32Loop++)
++ {
++ ui32RamId = ui32DataMem + (ui32Address / ui32RamBankSize);
+
-+#define MSVDX_MTX_RAM_ACCESS_CONTROL_MTX_MCM_ADDR_MASK (0x000FFFFC)
-+#define MSVDX_MTX_RAM_ACCESS_CONTROL_MTX_MCM_ADDR_SHIFT (2)
++ if (ui32RamId != ui32CurrBank)
++ {
++ ui32Addr = ui32Address >> 2;
+
-+#define MSVDX_MTX_RAM_ACCESS_CONTROL_MTX_MCMAI_MASK (0x00000002)
-+#define MSVDX_MTX_RAM_ACCESS_CONTROL_MTX_MCMAI_SHIFT (1)
++ ui32Ctrl = 0;
+
-+#define MSVDX_MTX_RAM_ACCESS_CONTROL_MTX_MCMR_MASK (0x00000001)
-+#define MSVDX_MTX_RAM_ACCESS_CONTROL_MTX_MCMR_SHIFT (0)
++ REGIO_WRITE_FIELD_LITE (ui32Ctrl,
++ MSVDX_MTX_RAM_ACCESS_CONTROL,
++ MTX_MCMID, ui32RamId);
++ REGIO_WRITE_FIELD_LITE (ui32Ctrl,
++ MSVDX_MTX_RAM_ACCESS_CONTROL,
++ MTX_MCM_ADDR, ui32Addr);
++ REGIO_WRITE_FIELD_LITE (ui32Ctrl,
++ MSVDX_MTX_RAM_ACCESS_CONTROL, MTX_MCMAI, 1);
+
-+#define MSVDX_MTX_SOFT_RESET_MTX_RESET_MASK (0x00000001)
-+#define MSVDX_MTX_SOFT_RESET_MTX_RESET_SHIFT (0)
++ PSB_WMSVDX32 (ui32Ctrl, MSVDX_MTX_RAM_ACCESS_CONTROL);
+
-+#define MSVDX_MTX_ENABLE_MTX_ENABLE_MASK (0x00000001)
-+#define MSVDX_MTX_ENABLE_MTX_ENABLE_SHIFT (0)
++ ui32CurrBank = ui32RamId;
++ }
++ ui32Address += 4;
+
-+#define MSVDX_CONTROL_CR_MSVDX_SOFT_RESET_MASK (0x00000100)
-+#define MSVDX_CONTROL_CR_MSVDX_SOFT_RESET_SHIFT (8)
++ PSB_WMSVDX32 (pui32Data[ui32Loop], MSVDX_MTX_RAM_ACCESS_DATA_TRANSFER);
+
-+#define MSVDX_INTERRUPT_STATUS_CR_MMU_FAULT_IRQ_MASK (0x00000F00)
-+#define MSVDX_INTERRUPT_STATUS_CR_MMU_FAULT_IRQ_SHIFT (8)
++ /* Wait for MCMSTAT to become be idle 1 */
++ psb_wait_for_register (dev_priv, MSVDX_MTX_RAM_ACCESS_STATUS, 1, /* Required Value */
++ 0xffffffff /* Enables */ );
++ }
++ PSB_DEBUG_GENERAL ("MSVDX: Upload done\n");
+
-+#define MSVDX_INTERRUPT_STATUS_CR_MTX_IRQ_MASK (0x00004000)
-+#define MSVDX_INTERRUPT_STATUS_CR_MTX_IRQ_SHIFT (14)
++ /* Restore the access control register... */
++ PSB_WMSVDX32 (ui32AccessControl, MSVDX_MTX_RAM_ACCESS_CONTROL);
++}
+
-+#define MSVDX_MMU_CONTROL0_CR_MMU_PAUSE_MASK (0x00000002)
-+#define MSVDX_MMU_CONTROL0_CR_MMU_PAUSE_SHIFT (1)
++static int
++psb_verify_fw (struct drm_psb_private *dev_priv,
++ const uint32_t ui32RamBankSize,
++ const uint32_t ui32DataMem, uint32_t ui32Address,
++ const uint32_t uiWords, const uint32_t * const pui32Data)
++{
++ uint32_t ui32Loop, ui32Ctrl, ui32RamId, ui32Addr, ui32CurrBank =
++ (uint32_t) ~ 0;
++ uint32_t ui32AccessControl;
++ int ret = 0;
+
-+#define MSVDX_MTX_RAM_BANK_CR_MTX_RAM_BANK_SIZE_MASK (0x000F0000)
-+#define MSVDX_MTX_RAM_BANK_CR_MTX_RAM_BANK_SIZE_SHIFT (16)
++ /* Save the access control register... */
++ ui32AccessControl = PSB_RMSVDX32 (MSVDX_MTX_RAM_ACCESS_CONTROL);
+
-+#define MSVDX_RENDEC_BUFFER_SIZE_RENDEC_BUFFER_SIZE0_MASK (0x0000FFFF)
-+#define MSVDX_RENDEC_BUFFER_SIZE_RENDEC_BUFFER_SIZE0_SHIFT (0)
++ /* Wait for MCMSTAT to become be idle 1 */
++ psb_wait_for_register (dev_priv, MSVDX_MTX_RAM_ACCESS_STATUS, 1, /* Required Value */
++ 0xffffffff /* Enables */ );
+
-+#define MSVDX_RENDEC_BUFFER_SIZE_RENDEC_BUFFER_SIZE1_MASK (0xFFFF0000)
-+#define MSVDX_RENDEC_BUFFER_SIZE_RENDEC_BUFFER_SIZE1_SHIFT (16)
++ for (ui32Loop = 0; ui32Loop < uiWords; ui32Loop++)
++ {
++ uint32_t ui32ReadBackVal;
++ ui32RamId = ui32DataMem + (ui32Address / ui32RamBankSize);
+
-+#define MSVDX_RENDEC_CONTROL1_RENDEC_DECODE_START_SIZE_MASK (0x000000FF)
-+#define MSVDX_RENDEC_CONTROL1_RENDEC_DECODE_START_SIZE_SHIFT (0)
++ if (ui32RamId != ui32CurrBank)
++ {
++ ui32Addr = ui32Address >> 2;
++ ui32Ctrl = 0;
++ REGIO_WRITE_FIELD_LITE (ui32Ctrl,
++ MSVDX_MTX_RAM_ACCESS_CONTROL,
++ MTX_MCMID, ui32RamId);
++ REGIO_WRITE_FIELD_LITE (ui32Ctrl,
++ MSVDX_MTX_RAM_ACCESS_CONTROL,
++ MTX_MCM_ADDR, ui32Addr);
++ REGIO_WRITE_FIELD_LITE (ui32Ctrl,
++ MSVDX_MTX_RAM_ACCESS_CONTROL, MTX_MCMAI, 1);
++ REGIO_WRITE_FIELD_LITE (ui32Ctrl,
++ MSVDX_MTX_RAM_ACCESS_CONTROL, MTX_MCMR, 1);
+
-+#define MSVDX_RENDEC_CONTROL1_RENDEC_BURST_SIZE_W_MASK (0x000C0000)
-+#define MSVDX_RENDEC_CONTROL1_RENDEC_BURST_SIZE_W_SHIFT (18)
++ PSB_WMSVDX32 (ui32Ctrl, MSVDX_MTX_RAM_ACCESS_CONTROL);
+
-+#define MSVDX_RENDEC_CONTROL1_RENDEC_BURST_SIZE_R_MASK (0x00030000)
-+#define MSVDX_RENDEC_CONTROL1_RENDEC_BURST_SIZE_R_SHIFT (16)
++ ui32CurrBank = ui32RamId;
++ }
++ ui32Address += 4;
+
-+#define MSVDX_RENDEC_CONTROL1_RENDEC_EXTERNAL_MEMORY_MASK (0x01000000)
-+#define MSVDX_RENDEC_CONTROL1_RENDEC_EXTERNAL_MEMORY_SHIFT (24)
++ /* Wait for MCMSTAT to become be idle 1 */
++ psb_wait_for_register (dev_priv, MSVDX_MTX_RAM_ACCESS_STATUS, 1, /* Required Value */
++ 0xffffffff /* Enables */ );
+
-+#define MSVDX_RENDEC_CONTROL0_RENDEC_INITIALISE_MASK (0x00000001)
-+#define MSVDX_RENDEC_CONTROL0_RENDEC_INITIALISE_SHIFT (0)
++ ui32ReadBackVal = PSB_RMSVDX32 (MSVDX_MTX_RAM_ACCESS_DATA_TRANSFER);
++ if (pui32Data[ui32Loop] != ui32ReadBackVal)
++ {
++ DRM_ERROR
++ ("psb: Firmware validation fails at index=%08x\n", ui32Loop);
++ ret = 1;
++ break;
++ }
++ }
+
-+#define FWRK_MSGID_START_PSR_HOSTMTX_MSG (0x80) /*!< Start of parser specific Host->MTX messages. */
-+#define FWRK_MSGID_START_PSR_MTXHOST_MSG (0xC0) /*!< Start of parser specific MTX->Host messages. */
-+#define FWRK_MSGID_PADDING ( 0 )
++ /* Restore the access control register... */
++ PSB_WMSVDX32 (ui32AccessControl, MSVDX_MTX_RAM_ACCESS_CONTROL);
+
-+#define FWRK_GENMSG_SIZE_TYPE uint8_t
-+#define FWRK_GENMSG_SIZE_MASK (0xFF)
-+#define FWRK_GENMSG_SIZE_SHIFT (0)
-+#define FWRK_GENMSG_SIZE_OFFSET (0x0000)
-+#define FWRK_GENMSG_ID_TYPE uint8_t
-+#define FWRK_GENMSG_ID_MASK (0xFF)
-+#define FWRK_GENMSG_ID_SHIFT (0)
-+#define FWRK_GENMSG_ID_OFFSET (0x0001)
-+#define FWRK_PADMSG_SIZE (2)
++ return ret;
++}
+
-+/*!
-+******************************************************************************
-+ This type defines the framework specified message ids
-+******************************************************************************/
-+enum
++static uint32_t *
++msvdx_get_fw (struct drm_device *dev,
++ const struct firmware **raw, uint8_t * name)
+{
-+ /*! Sent by the DXVA driver on the host to the mtx firmware.
-+ */
-+ VA_MSGID_INIT = FWRK_MSGID_START_PSR_HOSTMTX_MSG,
-+ VA_MSGID_RENDER,
-+ VA_MSGID_DEBLOCK,
-+ VA_MSGID_OOLD,
++ int rc;
++ int *ptr = NULL;
+
-+ /* Test Messages */
-+ VA_MSGID_TEST1,
-+ VA_MSGID_TEST2,
++ rc = request_firmware (raw, name, &dev->pdev->dev);
++ if (rc < 0)
++ {
++ DRM_ERROR ("MSVDX: %s request_firmware failed: Reason %d\n", name, rc);
++ return NULL;
++ }
+
-+ /*! Sent by the mtx firmware to itself.
-+ */
-+ VA_MSGID_RENDER_MC_INTERRUPT,
++ if ((*raw)->size < sizeof (struct msvdx_fw))
++ {
++ PSB_DEBUG_GENERAL ("MSVDX: %s is is not correct size(%zd)\n",
++ name, (*raw)->size);
++ return NULL;
++ }
+
-+ /*! Sent by the DXVA firmware on the MTX to the host.
-+ */
-+ VA_MSGID_CMD_COMPLETED = FWRK_MSGID_START_PSR_MTXHOST_MSG,
-+ VA_MSGID_CMD_COMPLETED_BATCH,
-+ VA_MSGID_DEBLOCK_REQUIRED,
-+ VA_MSGID_TEST_RESPONCE,
-+ VA_MSGID_ACK,
-+
-+ VA_MSGID_CMD_FAILED,
-+ VA_MSGID_CMD_UNSUPPORTED,
-+ VA_MSGID_CMD_HW_PANIC,
-+};
++ ptr = (int *) ((*raw))->data;
+
-+/* MSVDX Firmware interface */
++ if (!ptr)
++ {
++ PSB_DEBUG_GENERAL ("MSVDX: Failed to load %s\n", name);
++ return NULL;
++ }
++ /*another sanity check... */
++ if ((*raw)->size !=
++ (sizeof (struct msvdx_fw) +
++ sizeof (uint32_t) * ((struct msvdx_fw *) ptr)->text_size +
++ sizeof (uint32_t) * ((struct msvdx_fw *) ptr)->data_size))
++ {
++ PSB_DEBUG_GENERAL ("MSVDX: %s is is not correct size(%zd)\n",
++ name, (*raw)->size);
++ return NULL;
++ }
++ return ptr;
++}
+
-+#define FW_VA_RENDER_SIZE (32)
++static int
++psb_setup_fw (struct drm_device *dev)
++{
++ struct drm_psb_private *dev_priv = dev->dev_private;
++ int ret = 0;
+
-+// FW_VA_RENDER MSG_SIZE
-+#define FW_VA_RENDER_MSG_SIZE_ALIGNMENT (1)
-+#define FW_VA_RENDER_MSG_SIZE_TYPE uint8_t
-+#define FW_VA_RENDER_MSG_SIZE_MASK (0xFF)
-+#define FW_VA_RENDER_MSG_SIZE_LSBMASK (0xFF)
-+#define FW_VA_RENDER_MSG_SIZE_OFFSET (0x0000)
-+#define FW_VA_RENDER_MSG_SIZE_SHIFT (0)
++ uint32_t ram_bank_size;
++ struct msvdx_fw *fw;
++ uint32_t *fw_ptr = NULL;
++ uint32_t *text_ptr = NULL;
++ uint32_t *data_ptr = NULL;
++ const struct firmware *raw = NULL;
++ /* todo : Assert the clock is on - if not turn it on to upload code */
+
-+// FW_VA_RENDER ID
-+#define FW_VA_RENDER_ID_ALIGNMENT (1)
-+#define FW_VA_RENDER_ID_TYPE uint8_t
-+#define FW_VA_RENDER_ID_MASK (0xFF)
-+#define FW_VA_RENDER_ID_LSBMASK (0xFF)
-+#define FW_VA_RENDER_ID_OFFSET (0x0001)
-+#define FW_VA_RENDER_ID_SHIFT (0)
++ PSB_DEBUG_GENERAL ("MSVDX: psb_setup_fw\n");
+
-+// FW_VA_RENDER BUFFER_SIZE
-+#define FW_VA_RENDER_BUFFER_SIZE_ALIGNMENT (2)
-+#define FW_VA_RENDER_BUFFER_SIZE_TYPE uint16_t
-+#define FW_VA_RENDER_BUFFER_SIZE_MASK (0x0FFF)
-+#define FW_VA_RENDER_BUFFER_SIZE_LSBMASK (0x0FFF)
-+#define FW_VA_RENDER_BUFFER_SIZE_OFFSET (0x0002)
-+#define FW_VA_RENDER_BUFFER_SIZE_SHIFT (0)
++ /* Reset MTX */
++ PSB_WMSVDX32 (MSVDX_MTX_SOFT_RESET_MTX_RESET_MASK, MSVDX_MTX_SOFT_RESET);
+
-+// FW_VA_RENDER MMUPTD
-+#define FW_VA_RENDER_MMUPTD_ALIGNMENT (4)
-+#define FW_VA_RENDER_MMUPTD_TYPE uint32_t
-+#define FW_VA_RENDER_MMUPTD_MASK (0xFFFFFFFF)
-+#define FW_VA_RENDER_MMUPTD_LSBMASK (0xFFFFFFFF)
-+#define FW_VA_RENDER_MMUPTD_OFFSET (0x0004)
-+#define FW_VA_RENDER_MMUPTD_SHIFT (0)
++ /* Initialses Communication controll area to 0 */
++ if(dev_priv->psb_rev_id >= POULSBO_D1)
++ {
++ PSB_DEBUG_GENERAL("MSVDX: Detected Poulsbo D1 or later revision.\n");
++ PSB_WMSVDX32 (MSVDX_DEVICE_NODE_FLAGS_DEFAULT_D1, MSVDX_COMMS_OFFSET_FLAGS);
++ }
++ else
++ {
++ PSB_DEBUG_GENERAL("MSVDX: Detected Poulsbo D0 or earlier revision.\n");
++ PSB_WMSVDX32 (MSVDX_DEVICE_NODE_FLAGS_DEFAULT_D0, MSVDX_COMMS_OFFSET_FLAGS);
++ }
+
-+// FW_VA_RENDER LLDMA_ADDRESS
-+#define FW_VA_RENDER_LLDMA_ADDRESS_ALIGNMENT (4)
-+#define FW_VA_RENDER_LLDMA_ADDRESS_TYPE uint32_t
-+#define FW_VA_RENDER_LLDMA_ADDRESS_MASK (0xFFFFFFFF)
-+#define FW_VA_RENDER_LLDMA_ADDRESS_LSBMASK (0xFFFFFFFF)
-+#define FW_VA_RENDER_LLDMA_ADDRESS_OFFSET (0x0008)
-+#define FW_VA_RENDER_LLDMA_ADDRESS_SHIFT (0)
++ PSB_WMSVDX32 (0, MSVDX_COMMS_MSG_COUNTER);
++ PSB_WMSVDX32 (0, MSVDX_COMMS_SIGNATURE);
++ PSB_WMSVDX32 (0, MSVDX_COMMS_TO_HOST_RD_INDEX);
++ PSB_WMSVDX32 (0, MSVDX_COMMS_TO_HOST_WRT_INDEX);
++ PSB_WMSVDX32 (0, MSVDX_COMMS_TO_MTX_RD_INDEX);
++ PSB_WMSVDX32 (0, MSVDX_COMMS_TO_MTX_WRT_INDEX);
++ PSB_WMSVDX32 (0, MSVDX_COMMS_FW_STATUS);
+
-+// FW_VA_RENDER CONTEXT
-+#define FW_VA_RENDER_CONTEXT_ALIGNMENT (4)
-+#define FW_VA_RENDER_CONTEXT_TYPE uint32_t
-+#define FW_VA_RENDER_CONTEXT_MASK (0xFFFFFFFF)
-+#define FW_VA_RENDER_CONTEXT_LSBMASK (0xFFFFFFFF)
-+#define FW_VA_RENDER_CONTEXT_OFFSET (0x000C)
-+#define FW_VA_RENDER_CONTEXT_SHIFT (0)
++ /* read register bank size */
++ {
++ uint32_t ui32BankSize, ui32Reg;
++ ui32Reg = PSB_RMSVDX32 (MSVDX_MTX_RAM_BANK);
++ ui32BankSize =
++ REGIO_READ_FIELD (ui32Reg, MSVDX_MTX_RAM_BANK, CR_MTX_RAM_BANK_SIZE);
++ ram_bank_size = (uint32_t) (1 << (ui32BankSize + 2));
++ }
+
-+// FW_VA_RENDER FENCE_VALUE
-+#define FW_VA_RENDER_FENCE_VALUE_ALIGNMENT (4)
-+#define FW_VA_RENDER_FENCE_VALUE_TYPE uint32_t
-+#define FW_VA_RENDER_FENCE_VALUE_MASK (0xFFFFFFFF)
-+#define FW_VA_RENDER_FENCE_VALUE_LSBMASK (0xFFFFFFFF)
-+#define FW_VA_RENDER_FENCE_VALUE_OFFSET (0x0010)
-+#define FW_VA_RENDER_FENCE_VALUE_SHIFT (0)
++ PSB_DEBUG_GENERAL ("MSVDX: RAM bank size = %d bytes\n", ram_bank_size);
+
-+// FW_VA_RENDER OPERATING_MODE
-+#define FW_VA_RENDER_OPERATING_MODE_ALIGNMENT (4)
-+#define FW_VA_RENDER_OPERATING_MODE_TYPE uint32_t
-+#define FW_VA_RENDER_OPERATING_MODE_MASK (0xFFFFFFFF)
-+#define FW_VA_RENDER_OPERATING_MODE_LSBMASK (0xFFFFFFFF)
-+#define FW_VA_RENDER_OPERATING_MODE_OFFSET (0x0014)
-+#define FW_VA_RENDER_OPERATING_MODE_SHIFT (0)
++ fw_ptr = msvdx_get_fw (dev, &raw, "msvdx_fw.bin");
+
-+// FW_VA_RENDER FIRST_MB_IN_SLICE
-+#define FW_VA_RENDER_FIRST_MB_IN_SLICE_ALIGNMENT (2)
-+#define FW_VA_RENDER_FIRST_MB_IN_SLICE_TYPE uint16_t
-+#define FW_VA_RENDER_FIRST_MB_IN_SLICE_MASK (0xFFFF)
-+#define FW_VA_RENDER_FIRST_MB_IN_SLICE_LSBMASK (0xFFFF)
-+#define FW_VA_RENDER_FIRST_MB_IN_SLICE_OFFSET (0x0018)
-+#define FW_VA_RENDER_FIRST_MB_IN_SLICE_SHIFT (0)
++ if (!fw_ptr)
++ {
++ DRM_ERROR ("psb: No valid msvdx_fw.bin firmware found.\n");
++ ret = 1;
++ goto out;
++ }
+
-+// FW_VA_RENDER LAST_MB_IN_FRAME
-+#define FW_VA_RENDER_LAST_MB_IN_FRAME_ALIGNMENT (2)
-+#define FW_VA_RENDER_LAST_MB_IN_FRAME_TYPE uint16_t
-+#define FW_VA_RENDER_LAST_MB_IN_FRAME_MASK (0xFFFF)
-+#define FW_VA_RENDER_LAST_MB_IN_FRAME_LSBMASK (0xFFFF)
-+#define FW_VA_RENDER_LAST_MB_IN_FRAME_OFFSET (0x001A)
-+#define FW_VA_RENDER_LAST_MB_IN_FRAME_SHIFT (0)
++ fw = (struct msvdx_fw *) fw_ptr;
++ if (fw->ver != 0x02)
++ {
++ DRM_ERROR
++ ("psb: msvdx_fw.bin firmware version mismatch, got version=%02x expected version=%02x\n",
++ fw->ver, 0x02);
++ ret = 1;
++ goto out;
++ }
+
-+// FW_VA_RENDER FLAGS
-+#define FW_VA_RENDER_FLAGS_ALIGNMENT (4)
-+#define FW_VA_RENDER_FLAGS_TYPE uint32_t
-+#define FW_VA_RENDER_FLAGS_MASK (0xFFFFFFFF)
-+#define FW_VA_RENDER_FLAGS_LSBMASK (0xFFFFFFFF)
-+#define FW_VA_RENDER_FLAGS_OFFSET (0x001C)
-+#define FW_VA_RENDER_FLAGS_SHIFT (0)
++ text_ptr = (uint32_t *) ((uint8_t *) fw_ptr + sizeof (struct msvdx_fw));
++ data_ptr = text_ptr + fw->text_size;
+
-+#define FW_VA_CMD_COMPLETED_SIZE (12)
++ PSB_DEBUG_GENERAL ("MSVDX: Retrieved pointers for firmware\n");
++ PSB_DEBUG_GENERAL ("MSVDX: text_size: %d\n", fw->text_size);
++ PSB_DEBUG_GENERAL ("MSVDX: data_size: %d\n", fw->data_size);
++ PSB_DEBUG_GENERAL ("MSVDX: data_location: 0x%x\n", fw->data_location);
++ PSB_DEBUG_GENERAL ("MSVDX: First 4 bytes of text: 0x%x\n", *text_ptr);
++ PSB_DEBUG_GENERAL ("MSVDX: First 4 bytes of data: 0x%x\n", *data_ptr);
+
-+// FW_VA_CMD_COMPLETED MSG_SIZE
-+#define FW_VA_CMD_COMPLETED_MSG_SIZE_ALIGNMENT (1)
-+#define FW_VA_CMD_COMPLETED_MSG_SIZE_TYPE uint8_t
-+#define FW_VA_CMD_COMPLETED_MSG_SIZE_MASK (0xFF)
-+#define FW_VA_CMD_COMPLETED_MSG_SIZE_LSBMASK (0xFF)
-+#define FW_VA_CMD_COMPLETED_MSG_SIZE_OFFSET (0x0000)
-+#define FW_VA_CMD_COMPLETED_MSG_SIZE_SHIFT (0)
++ PSB_DEBUG_GENERAL ("MSVDX: Uploading firmware\n");
++ psb_upload_fw (dev_priv, MTX_CORE_CODE_MEM, ram_bank_size,
++ PC_START_ADDRESS - MTX_CODE_BASE, fw->text_size, text_ptr);
++ psb_upload_fw (dev_priv, MTX_CORE_DATA_MEM, ram_bank_size,
++ fw->data_location - MTX_DATA_BASE, fw->data_size, data_ptr);
+
-+// FW_VA_CMD_COMPLETED ID
-+#define FW_VA_CMD_COMPLETED_ID_ALIGNMENT (1)
-+#define FW_VA_CMD_COMPLETED_ID_TYPE uint8_t
-+#define FW_VA_CMD_COMPLETED_ID_MASK (0xFF)
-+#define FW_VA_CMD_COMPLETED_ID_LSBMASK (0xFF)
-+#define FW_VA_CMD_COMPLETED_ID_OFFSET (0x0001)
-+#define FW_VA_CMD_COMPLETED_ID_SHIFT (0)
++ /*todo : Verify code upload possibly only in debug */
++ if (psb_verify_fw
++ (dev_priv, ram_bank_size, MTX_CORE_CODE_MEM,
++ PC_START_ADDRESS - MTX_CODE_BASE, fw->text_size, text_ptr))
++ {
++ /* Firmware code upload failed */
++ ret = 1;
++ goto out;
++ }
++ if (psb_verify_fw
++ (dev_priv, ram_bank_size, MTX_CORE_DATA_MEM,
++ fw->data_location - MTX_DATA_BASE, fw->data_size, data_ptr))
++ {
++ /* Firmware data upload failed */
++ ret = 1;
++ goto out;
++ }
+
-+// FW_VA_CMD_COMPLETED FENCE_VALUE
-+#define FW_VA_CMD_COMPLETED_FENCE_VALUE_ALIGNMENT (4)
-+#define FW_VA_CMD_COMPLETED_FENCE_VALUE_TYPE uint32_t
-+#define FW_VA_CMD_COMPLETED_FENCE_VALUE_MASK (0xFFFFFFFF)
-+#define FW_VA_CMD_COMPLETED_FENCE_VALUE_LSBMASK (0xFFFFFFFF)
-+#define FW_VA_CMD_COMPLETED_FENCE_VALUE_OFFSET (0x0004)
-+#define FW_VA_CMD_COMPLETED_FENCE_VALUE_SHIFT (0)
++ /* -- Set starting PC address */
++ psb_write_mtx_core_reg (dev_priv, MTX_PC, PC_START_ADDRESS);
+
-+// FW_VA_CMD_COMPLETED FLAGS
-+#define FW_VA_CMD_COMPLETED_FLAGS_ALIGNMENT (4)
-+#define FW_VA_CMD_COMPLETED_FLAGS_TYPE uint32_t
-+#define FW_VA_CMD_COMPLETED_FLAGS_MASK (0xFFFFFFFF)
-+#define FW_VA_CMD_COMPLETED_FLAGS_LSBMASK (0xFFFFFFFF)
-+#define FW_VA_CMD_COMPLETED_FLAGS_OFFSET (0x0008)
-+#define FW_VA_CMD_COMPLETED_FLAGS_SHIFT (0)
++ /* -- Turn on the thread */
++ PSB_WMSVDX32 (MSVDX_MTX_ENABLE_MTX_ENABLE_MASK, MSVDX_MTX_ENABLE);
+
-+#define FW_VA_CMD_FAILED_SIZE (12)
++ /* Wait for the signature value to be written back */
++ ret = psb_wait_for_register (dev_priv, MSVDX_COMMS_SIGNATURE, MSVDX_COMMS_SIGNATURE_VALUE, /* Required value */
++ 0xffffffff /* Enabled bits */ );
++ if (ret)
++ {
++ DRM_ERROR ("psb: MSVDX firmware fails to initialize.\n");
++ goto out;
++ }
+
-+// FW_VA_CMD_FAILED MSG_SIZE
-+#define FW_VA_CMD_FAILED_MSG_SIZE_ALIGNMENT (1)
-+#define FW_VA_CMD_FAILED_MSG_SIZE_TYPE uint8_t
-+#define FW_VA_CMD_FAILED_MSG_SIZE_MASK (0xFF)
-+#define FW_VA_CMD_FAILED_MSG_SIZE_LSBMASK (0xFF)
-+#define FW_VA_CMD_FAILED_MSG_SIZE_OFFSET (0x0000)
-+#define FW_VA_CMD_FAILED_MSG_SIZE_SHIFT (0)
++ PSB_DEBUG_GENERAL ("MSVDX: MTX Initial indications OK\n");
++ PSB_DEBUG_GENERAL ("MSVDX: MSVDX_COMMS_AREA_ADDR = %08x\n",
++ MSVDX_COMMS_AREA_ADDR);
++out:
++ if (raw)
++ {
++ PSB_DEBUG_GENERAL ("MSVDX releasing firmware resouces....\n");
++ release_firmware (raw);
++ }
++ return ret;
++}
+
-+// FW_VA_CMD_FAILED ID
-+#define FW_VA_CMD_FAILED_ID_ALIGNMENT (1)
-+#define FW_VA_CMD_FAILED_ID_TYPE uint8_t
-+#define FW_VA_CMD_FAILED_ID_MASK (0xFF)
-+#define FW_VA_CMD_FAILED_ID_LSBMASK (0xFF)
-+#define FW_VA_CMD_FAILED_ID_OFFSET (0x0001)
-+#define FW_VA_CMD_FAILED_ID_SHIFT (0)
-+
-+// FW_VA_CMD_FAILED FLAGS
-+#define FW_VA_CMD_FAILED_FLAGS_ALIGNMENT (2)
-+#define FW_VA_CMD_FAILED_FLAGS_TYPE uint16_t
-+#define FW_VA_CMD_FAILED_FLAGS_MASK (0xFFFF)
-+#define FW_VA_CMD_FAILED_FLAGS_LSBMASK (0xFFFF)
-+#define FW_VA_CMD_FAILED_FLAGS_OFFSET (0x0002)
-+#define FW_VA_CMD_FAILED_FLAGS_SHIFT (0)
-+
-+// FW_VA_CMD_FAILED FENCE_VALUE
-+#define FW_VA_CMD_FAILED_FENCE_VALUE_ALIGNMENT (4)
-+#define FW_VA_CMD_FAILED_FENCE_VALUE_TYPE uint32_t
-+#define FW_VA_CMD_FAILED_FENCE_VALUE_MASK (0xFFFFFFFF)
-+#define FW_VA_CMD_FAILED_FENCE_VALUE_LSBMASK (0xFFFFFFFF)
-+#define FW_VA_CMD_FAILED_FENCE_VALUE_OFFSET (0x0004)
-+#define FW_VA_CMD_FAILED_FENCE_VALUE_SHIFT (0)
-+
-+// FW_VA_CMD_FAILED IRQSTATUS
-+#define FW_VA_CMD_FAILED_IRQSTATUS_ALIGNMENT (4)
-+#define FW_VA_CMD_FAILED_IRQSTATUS_TYPE uint32_t
-+#define FW_VA_CMD_FAILED_IRQSTATUS_MASK (0xFFFFFFFF)
-+#define FW_VA_CMD_FAILED_IRQSTATUS_LSBMASK (0xFFFFFFFF)
-+#define FW_VA_CMD_FAILED_IRQSTATUS_OFFSET (0x0008)
-+#define FW_VA_CMD_FAILED_IRQSTATUS_SHIFT (0)
++static void
++psb_free_ccb (struct drm_buffer_object **ccb)
++{
++ drm_bo_usage_deref_unlocked (ccb);
++ *ccb = NULL;
++}
+
-+#define FW_VA_DEBLOCK_REQUIRED_SIZE (8)
++/*******************************************************************************
+
-+// FW_VA_DEBLOCK_REQUIRED MSG_SIZE
-+#define FW_VA_DEBLOCK_REQUIRED_MSG_SIZE_ALIGNMENT (1)
-+#define FW_VA_DEBLOCK_REQUIRED_MSG_SIZE_TYPE uint8_t
-+#define FW_VA_DEBLOCK_REQUIRED_MSG_SIZE_MASK (0xFF)
-+#define FW_VA_DEBLOCK_REQUIRED_MSG_SIZE_LSBMASK (0xFF)
-+#define FW_VA_DEBLOCK_REQUIRED_MSG_SIZE_OFFSET (0x0000)
-+#define FW_VA_DEBLOCK_REQUIRED_MSG_SIZE_SHIFT (0)
++ @Function psb_msvdx_reset
+
-+// FW_VA_DEBLOCK_REQUIRED ID
-+#define FW_VA_DEBLOCK_REQUIRED_ID_ALIGNMENT (1)
-+#define FW_VA_DEBLOCK_REQUIRED_ID_TYPE uint8_t
-+#define FW_VA_DEBLOCK_REQUIRED_ID_MASK (0xFF)
-+#define FW_VA_DEBLOCK_REQUIRED_ID_LSBMASK (0xFF)
-+#define FW_VA_DEBLOCK_REQUIRED_ID_OFFSET (0x0001)
-+#define FW_VA_DEBLOCK_REQUIRED_ID_SHIFT (0)
++ @Description
+
-+// FW_VA_DEBLOCK_REQUIRED CONTEXT
-+#define FW_VA_DEBLOCK_REQUIRED_CONTEXT_ALIGNMENT (4)
-+#define FW_VA_DEBLOCK_REQUIRED_CONTEXT_TYPE uint32_t
-+#define FW_VA_DEBLOCK_REQUIRED_CONTEXT_MASK (0xFFFFFFFF)
-+#define FW_VA_DEBLOCK_REQUIRED_CONTEXT_LSBMASK (0xFFFFFFFF)
-+#define FW_VA_DEBLOCK_REQUIRED_CONTEXT_OFFSET (0x0004)
-+#define FW_VA_DEBLOCK_REQUIRED_CONTEXT_SHIFT (0)
++ Reset chip and disable interrupts.
+
-+#define FW_VA_HW_PANIC_SIZE (12)
++ @Input psDeviceNode - device info. structure
+
-+// FW_VA_HW_PANIC FLAGS
-+#define FW_VA_HW_PANIC_FLAGS_ALIGNMENT (2)
-+#define FW_VA_HW_PANIC_FLAGS_TYPE uint16_t
-+#define FW_VA_HW_PANIC_FLAGS_MASK (0xFFFF)
-+#define FW_VA_HW_PANIC_FLAGS_LSBMASK (0xFFFF)
-+#define FW_VA_HW_PANIC_FLAGS_OFFSET (0x0002)
-+#define FW_VA_HW_PANIC_FLAGS_SHIFT (0)
++ @Return 0 - Success
++ 1 - Failure
+
-+// FW_VA_HW_PANIC MSG_SIZE
-+#define FW_VA_HW_PANIC_MSG_SIZE_ALIGNMENT (1)
-+#define FW_VA_HW_PANIC_MSG_SIZE_TYPE uint8_t
-+#define FW_VA_HW_PANIC_MSG_SIZE_MASK (0xFF)
-+#define FW_VA_HW_PANIC_MSG_SIZE_LSBMASK (0xFF)
-+#define FW_VA_HW_PANIC_MSG_SIZE_OFFSET (0x0000)
-+#define FW_VA_HW_PANIC_MSG_SIZE_SHIFT (0)
++******************************************************************************/
++int
++psb_msvdx_reset (struct drm_psb_private *dev_priv)
++{
++ int ret = 0;
+
-+// FW_VA_HW_PANIC ID
-+#define FW_VA_HW_PANIC_ID_ALIGNMENT (1)
-+#define FW_VA_HW_PANIC_ID_TYPE uint8_t
-+#define FW_VA_HW_PANIC_ID_MASK (0xFF)
-+#define FW_VA_HW_PANIC_ID_LSBMASK (0xFF)
-+#define FW_VA_HW_PANIC_ID_OFFSET (0x0001)
-+#define FW_VA_HW_PANIC_ID_SHIFT (0)
++ /* Issue software reset */
++ PSB_WMSVDX32 (msvdx_sw_reset_all, MSVDX_CONTROL);
+
-+// FW_VA_HW_PANIC FENCE_VALUE
-+#define FW_VA_HW_PANIC_FENCE_VALUE_ALIGNMENT (4)
-+#define FW_VA_HW_PANIC_FENCE_VALUE_TYPE uint32_t
-+#define FW_VA_HW_PANIC_FENCE_VALUE_MASK (0xFFFFFFFF)
-+#define FW_VA_HW_PANIC_FENCE_VALUE_LSBMASK (0xFFFFFFFF)
-+#define FW_VA_HW_PANIC_FENCE_VALUE_OFFSET (0x0004)
-+#define FW_VA_HW_PANIC_FENCE_VALUE_SHIFT (0)
++ ret = psb_wait_for_register (dev_priv, MSVDX_CONTROL, 0, /* Required value */
++ MSVDX_CONTROL_CR_MSVDX_SOFT_RESET_MASK
++ /* Enabled bits */ );
+
-+// FW_VA_HW_PANIC IRQSTATUS
-+#define FW_VA_HW_PANIC_IRQSTATUS_ALIGNMENT (4)
-+#define FW_VA_HW_PANIC_IRQSTATUS_TYPE uint32_t
-+#define FW_VA_HW_PANIC_IRQSTATUS_MASK (0xFFFFFFFF)
-+#define FW_VA_HW_PANIC_IRQSTATUS_LSBMASK (0xFFFFFFFF)
-+#define FW_VA_HW_PANIC_IRQSTATUS_OFFSET (0x0008)
-+#define FW_VA_HW_PANIC_IRQSTATUS_SHIFT (0)
++ if (!ret)
++ {
++ /* Clear interrupt enabled flag */
++ PSB_WMSVDX32 (0, MSVDX_HOST_INTERRUPT_ENABLE);
+
-+#endif
-Index: linux-2.6.28/drivers/gpu/drm/psb/psb_msvdxinit.c
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/psb/psb_msvdxinit.c 2009-02-12 09:14:42.000000000 +0000
-@@ -0,0 +1,625 @@
-+/**
-+ * file psb_msvdxinit.c
-+ * MSVDX initialization and mtx-firmware upload
-+ *
-+ */
++ /* Clear any pending interrupt flags */
++ PSB_WMSVDX32 (0xFFFFFFFF, MSVDX_INTERRUPT_CLEAR);
++ }
+
-+/**************************************************************************
-+ *
-+ * Copyright (c) 2007 Intel Corporation, Hillsboro, OR, USA
-+ * Copyright (c) Imagination Technologies Limited, UK
-+ * All Rights Reserved.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the
-+ * "Software"), to deal in the Software without restriction, including
-+ * without limitation the rights to use, copy, modify, merge, publish,
-+ * distribute, sub license, and/or sell copies of the Software, and to
-+ * permit persons to whom the Software is furnished to do so, subject to
-+ * the following conditions:
-+ *
-+ * The above copyright notice and this permission notice (including the
-+ * next paragraph) shall be included in all copies or substantial portions
-+ * of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
-+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ **************************************************************************/
++ mutex_destroy (&dev_priv->msvdx_mutex);
+
-+#include "drmP.h"
-+#include "drm.h"
-+#include "psb_drv.h"
-+#include "psb_msvdx.h"
-+#include <linux/firmware.h>
++ return ret;
++}
+
-+/*MSVDX FW header*/
-+struct msvdx_fw
++static int
++psb_allocate_ccb (struct drm_device *dev,
++ struct drm_buffer_object **ccb,
++ uint32_t * base_addr, int size)
+{
-+ uint32_t ver;
-+ uint32_t text_size;
-+ uint32_t data_size;
-+ uint32_t data_location;
-+};
++ int ret;
++ struct drm_bo_kmap_obj tmp_kmap;
++ int is_iomem;
+
-+int
-+psb_wait_for_register (struct drm_psb_private *dev_priv,
-+ uint32_t ui32Offset,
-+ uint32_t ui32Value, uint32_t ui32Enable)
-+{
-+ uint32_t ui32Temp;
-+ uint32_t ui32PollCount = 1000;
-+ while (ui32PollCount)
++ ret = drm_buffer_object_create (dev, size,
++ drm_bo_type_kernel,
++ DRM_BO_FLAG_READ |
++ DRM_PSB_FLAG_MEM_KERNEL |
++ DRM_BO_FLAG_NO_EVICT,
++ DRM_BO_HINT_DONT_FENCE, 0, 0, ccb);
++ if (ret)
+ {
-+ ui32Temp = PSB_RMSVDX32 (ui32Offset);
-+ if (ui32Value == (ui32Temp & ui32Enable)) /* All the bits are reset */
-+ return 0; /* So exit */
-+
-+ /* Wait a bit */
-+ DRM_UDELAY (100);
-+ ui32PollCount--;
++ PSB_DEBUG_GENERAL ("Failed to allocate CCB.\n");
++ *ccb = NULL;
++ return 1;
+ }
-+ PSB_DEBUG_GENERAL
-+ ("MSVDX: Timeout while waiting for register %08x: expecting %08x (mask %08x), got %08x\n",
-+ ui32Offset, ui32Value, ui32Enable, ui32Temp);
-+ return 1;
-+}
-+
-+int
-+psb_poll_mtx_irq (struct drm_psb_private *dev_priv)
-+{
-+ int ret = 0;
-+ uint32_t MtxInt = 0;
-+ REGIO_WRITE_FIELD_LITE (MtxInt, MSVDX_INTERRUPT_STATUS, CR_MTX_IRQ, 1);
+
-+ ret = psb_wait_for_register (dev_priv, MSVDX_INTERRUPT_STATUS, MtxInt, /* Required value */
-+ MtxInt /* Enabled bits */ );
++ ret = drm_bo_kmap (*ccb, 0, (*ccb)->num_pages, &tmp_kmap);
+ if (ret)
+ {
-+ PSB_DEBUG_GENERAL
-+ ("MSVDX: Error Mtx did not return int within a resonable time\n");
-+
-+ return ret;
++ PSB_DEBUG_GENERAL ("drm_bo_kmap failed ret: %d\n", ret);
++ drm_bo_usage_deref_unlocked (ccb);
++ *ccb = NULL;
++ return 1;
+ }
+
-+ PSB_DEBUG_GENERAL ("MSVDX: Got MTX Int\n");
-+
-+ /* Got it so clear the bit */
-+ PSB_WMSVDX32 (MtxInt, MSVDX_INTERRUPT_CLEAR);
++ memset (drm_bmo_virtual (&tmp_kmap, &is_iomem), 0, size);
++ drm_bo_kunmap (&tmp_kmap);
+
-+ return ret;
++ *base_addr = (*ccb)->offset;
++ return 0;
+}
+
-+void
-+psb_write_mtx_core_reg (struct drm_psb_private *dev_priv,
-+ const uint32_t ui32CoreRegister,
-+ const uint32_t ui32Val)
++int
++psb_msvdx_init (struct drm_device *dev)
+{
-+ uint32_t ui32Reg = 0;
++ struct drm_psb_private *dev_priv = dev->dev_private;
++ uint32_t ui32Cmd;
++ int ret;
+
-+ /* Put data in MTX_RW_DATA */
-+ PSB_WMSVDX32 (ui32Val, MSVDX_MTX_REGISTER_READ_WRITE_DATA);
++ PSB_DEBUG_GENERAL ("MSVDX: psb_msvdx_init\n");
+
-+ /* DREADY is set to 0 and request a write */
-+ ui32Reg = ui32CoreRegister;
-+ REGIO_WRITE_FIELD_LITE (ui32Reg, MSVDX_MTX_REGISTER_READ_WRITE_REQUEST,
-+ MTX_RNW, 0);
-+ REGIO_WRITE_FIELD_LITE (ui32Reg, MSVDX_MTX_REGISTER_READ_WRITE_REQUEST,
-+ MTX_DREADY, 0);
-+ PSB_WMSVDX32 (ui32Reg, MSVDX_MTX_REGISTER_READ_WRITE_REQUEST);
-+
-+ psb_wait_for_register (dev_priv, MSVDX_MTX_REGISTER_READ_WRITE_REQUEST, MSVDX_MTX_REGISTER_READ_WRITE_REQUEST_MTX_DREADY_MASK, /* Required Value */
-+ MSVDX_MTX_REGISTER_READ_WRITE_REQUEST_MTX_DREADY_MASK);
-+}
++ /*Initialize command msvdx queueing */
++ INIT_LIST_HEAD (&dev_priv->msvdx_queue);
++ mutex_init (&dev_priv->msvdx_mutex);
++ spin_lock_init (&dev_priv->msvdx_lock);
++ dev_priv->msvdx_busy = 0;
+
-+void
-+psb_upload_fw (struct drm_psb_private *dev_priv, const uint32_t ui32DataMem,
-+ uint32_t ui32RamBankSize, uint32_t ui32Address,
-+ const unsigned int uiWords, const uint32_t * const pui32Data)
-+{
-+ uint32_t ui32Loop, ui32Ctrl, ui32RamId, ui32Addr, ui32CurrBank =
-+ (uint32_t) ~ 0;
-+ uint32_t ui32AccessControl;
++ /*figure out the stepping*/
++ pci_read_config_byte(dev->pdev, PSB_REVID_OFFSET, &dev_priv->psb_rev_id );
+
-+ /* Save the access control register... */
-+ ui32AccessControl = PSB_RMSVDX32 (MSVDX_MTX_RAM_ACCESS_CONTROL);
++ /* Enable Clocks */
++ PSB_DEBUG_GENERAL ("Enabling clocks\n");
++ PSB_WMSVDX32 (clk_enable_all, MSVDX_MAN_CLK_ENABLE);
+
-+ /* Wait for MCMSTAT to become be idle 1 */
-+ psb_wait_for_register (dev_priv, MSVDX_MTX_RAM_ACCESS_STATUS, 1, /* Required Value */
-+ 0xffffffff /* Enables */ );
++ /* Enable MMU by removing all bypass bits */
++ PSB_WMSVDX32 (0, MSVDX_MMU_CONTROL0);
+
-+ for (ui32Loop = 0; ui32Loop < uiWords; ui32Loop++)
++ PSB_DEBUG_GENERAL ("MSVDX: Setting up RENDEC\n");
++ /* Allocate device virtual memory as required by rendec.... */
++ if (!dev_priv->ccb0)
+ {
-+ ui32RamId = ui32DataMem + (ui32Address / ui32RamBankSize);
-+
-+ if (ui32RamId != ui32CurrBank)
-+ {
-+ ui32Addr = ui32Address >> 2;
-+
-+ ui32Ctrl = 0;
-+
-+ REGIO_WRITE_FIELD_LITE (ui32Ctrl,
-+ MSVDX_MTX_RAM_ACCESS_CONTROL,
-+ MTX_MCMID, ui32RamId);
-+ REGIO_WRITE_FIELD_LITE (ui32Ctrl,
-+ MSVDX_MTX_RAM_ACCESS_CONTROL,
-+ MTX_MCM_ADDR, ui32Addr);
-+ REGIO_WRITE_FIELD_LITE (ui32Ctrl,
-+ MSVDX_MTX_RAM_ACCESS_CONTROL, MTX_MCMAI, 1);
-+
-+ PSB_WMSVDX32 (ui32Ctrl, MSVDX_MTX_RAM_ACCESS_CONTROL);
-+
-+ ui32CurrBank = ui32RamId;
-+ }
-+ ui32Address += 4;
-+
-+ PSB_WMSVDX32 (pui32Data[ui32Loop], MSVDX_MTX_RAM_ACCESS_DATA_TRANSFER);
-+
-+ /* Wait for MCMSTAT to become be idle 1 */
-+ psb_wait_for_register (dev_priv, MSVDX_MTX_RAM_ACCESS_STATUS, 1, /* Required Value */
-+ 0xffffffff /* Enables */ );
++ ret =
++ psb_allocate_ccb (dev, &dev_priv->ccb0,
++ &dev_priv->base_addr0, RENDEC_A_SIZE);
++ if (ret)
++ goto err_exit;
+ }
-+ PSB_DEBUG_GENERAL ("MSVDX: Upload done\n");
+
-+ /* Restore the access control register... */
-+ PSB_WMSVDX32 (ui32AccessControl, MSVDX_MTX_RAM_ACCESS_CONTROL);
-+}
++ if (!dev_priv->ccb1)
++ {
++ ret =
++ psb_allocate_ccb (dev, &dev_priv->ccb1,
++ &dev_priv->base_addr1, RENDEC_B_SIZE);
++ if (ret)
++ goto err_exit;
++ }
+
-+static int
-+psb_verify_fw (struct drm_psb_private *dev_priv,
-+ const uint32_t ui32RamBankSize,
-+ const uint32_t ui32DataMem, uint32_t ui32Address,
-+ const uint32_t uiWords, const uint32_t * const pui32Data)
-+{
-+ uint32_t ui32Loop, ui32Ctrl, ui32RamId, ui32Addr, ui32CurrBank =
-+ (uint32_t) ~ 0;
-+ uint32_t ui32AccessControl;
-+ int ret = 0;
++ PSB_DEBUG_GENERAL ("MSVDX: RENDEC A: %08x RENDEC B: %08x\n",
++ dev_priv->base_addr0, dev_priv->base_addr1);
+
-+ /* Save the access control register... */
-+ ui32AccessControl = PSB_RMSVDX32 (MSVDX_MTX_RAM_ACCESS_CONTROL);
++ PSB_WMSVDX32 (dev_priv->base_addr0, MSVDX_RENDEC_BASE_ADDR0);
++ PSB_WMSVDX32 (dev_priv->base_addr1, MSVDX_RENDEC_BASE_ADDR1);
+
-+ /* Wait for MCMSTAT to become be idle 1 */
-+ psb_wait_for_register (dev_priv, MSVDX_MTX_RAM_ACCESS_STATUS, 1, /* Required Value */
-+ 0xffffffff /* Enables */ );
++ ui32Cmd = 0;
++ REGIO_WRITE_FIELD (ui32Cmd, MSVDX_RENDEC_BUFFER_SIZE,
++ RENDEC_BUFFER_SIZE0, RENDEC_A_SIZE / 4096);
++ REGIO_WRITE_FIELD (ui32Cmd, MSVDX_RENDEC_BUFFER_SIZE,
++ RENDEC_BUFFER_SIZE1, RENDEC_B_SIZE / 4096);
++ PSB_WMSVDX32 (ui32Cmd, MSVDX_RENDEC_BUFFER_SIZE);
+
-+ for (ui32Loop = 0; ui32Loop < uiWords; ui32Loop++)
-+ {
-+ uint32_t ui32ReadBackVal;
-+ ui32RamId = ui32DataMem + (ui32Address / ui32RamBankSize);
++ ui32Cmd = 0;
++ REGIO_WRITE_FIELD (ui32Cmd, MSVDX_RENDEC_CONTROL1,
++ RENDEC_DECODE_START_SIZE, 0);
++ REGIO_WRITE_FIELD (ui32Cmd, MSVDX_RENDEC_CONTROL1, RENDEC_BURST_SIZE_W, 1);
++ REGIO_WRITE_FIELD (ui32Cmd, MSVDX_RENDEC_CONTROL1, RENDEC_BURST_SIZE_R, 1);
++ REGIO_WRITE_FIELD (ui32Cmd, MSVDX_RENDEC_CONTROL1,
++ RENDEC_EXTERNAL_MEMORY, 1);
++ PSB_WMSVDX32 (ui32Cmd, MSVDX_RENDEC_CONTROL1);
+
-+ if (ui32RamId != ui32CurrBank)
-+ {
-+ ui32Addr = ui32Address >> 2;
-+ ui32Ctrl = 0;
-+ REGIO_WRITE_FIELD_LITE (ui32Ctrl,
-+ MSVDX_MTX_RAM_ACCESS_CONTROL,
-+ MTX_MCMID, ui32RamId);
-+ REGIO_WRITE_FIELD_LITE (ui32Ctrl,
-+ MSVDX_MTX_RAM_ACCESS_CONTROL,
-+ MTX_MCM_ADDR, ui32Addr);
-+ REGIO_WRITE_FIELD_LITE (ui32Ctrl,
-+ MSVDX_MTX_RAM_ACCESS_CONTROL, MTX_MCMAI, 1);
-+ REGIO_WRITE_FIELD_LITE (ui32Ctrl,
-+ MSVDX_MTX_RAM_ACCESS_CONTROL, MTX_MCMR, 1);
++ ui32Cmd = 0x00101010;
++ PSB_WMSVDX32 (ui32Cmd, MSVDX_RENDEC_CONTEXT0);
++ PSB_WMSVDX32 (ui32Cmd, MSVDX_RENDEC_CONTEXT1);
++ PSB_WMSVDX32 (ui32Cmd, MSVDX_RENDEC_CONTEXT2);
++ PSB_WMSVDX32 (ui32Cmd, MSVDX_RENDEC_CONTEXT3);
++ PSB_WMSVDX32 (ui32Cmd, MSVDX_RENDEC_CONTEXT4);
++ PSB_WMSVDX32 (ui32Cmd, MSVDX_RENDEC_CONTEXT5);
+
-+ PSB_WMSVDX32 (ui32Ctrl, MSVDX_MTX_RAM_ACCESS_CONTROL);
++ ui32Cmd = 0;
++ REGIO_WRITE_FIELD (ui32Cmd, MSVDX_RENDEC_CONTROL0, RENDEC_INITIALISE, 1);
++ PSB_WMSVDX32 (ui32Cmd, MSVDX_RENDEC_CONTROL0);
+
-+ ui32CurrBank = ui32RamId;
-+ }
-+ ui32Address += 4;
++ ret = psb_setup_fw (dev);
++ if (ret)
++ goto err_exit;
+
-+ /* Wait for MCMSTAT to become be idle 1 */
-+ psb_wait_for_register (dev_priv, MSVDX_MTX_RAM_ACCESS_STATUS, 1, /* Required Value */
-+ 0xffffffff /* Enables */ );
++ PSB_WMSVDX32 (clk_enable_minimal, MSVDX_MAN_CLK_ENABLE);
+
-+ ui32ReadBackVal = PSB_RMSVDX32 (MSVDX_MTX_RAM_ACCESS_DATA_TRANSFER);
-+ if (pui32Data[ui32Loop] != ui32ReadBackVal)
-+ {
-+ DRM_ERROR
-+ ("psb: Firmware validation fails at index=%08x\n", ui32Loop);
-+ ret = 1;
-+ break;
-+ }
-+ }
++ return 0;
+
-+ /* Restore the access control register... */
-+ PSB_WMSVDX32 (ui32AccessControl, MSVDX_MTX_RAM_ACCESS_CONTROL);
++err_exit:
++ if (dev_priv->ccb0)
++ psb_free_ccb (&dev_priv->ccb0);
++ if (dev_priv->ccb1)
++ psb_free_ccb (&dev_priv->ccb1);
+
-+ return ret;
++ return 1;
+}
+
-+static uint32_t *
-+msvdx_get_fw (struct drm_device *dev,
-+ const struct firmware **raw, uint8_t * name)
++int
++psb_msvdx_uninit (struct drm_device *dev)
+{
-+ int rc;
-+ int *ptr = NULL;
++ struct drm_psb_private *dev_priv = dev->dev_private;
+
-+ rc = request_firmware (raw, name, &dev->pdev->dev);
-+ if (rc < 0)
-+ {
-+ DRM_ERROR ("MSVDX: %s request_firmware failed: Reason %d\n", name, rc);
-+ return NULL;
-+ }
++ /*Reset MSVDX chip */
++ psb_msvdx_reset (dev_priv);
+
-+ if ((*raw)->size < sizeof (struct msvdx_fw))
-+ {
-+ PSB_DEBUG_GENERAL ("MSVDX: %s is is not correct size(%zd)\n",
-+ name, (*raw)->size);
-+ return NULL;
-+ }
++// PSB_WMSVDX32 (clk_enable_minimal, MSVDX_MAN_CLK_ENABLE);
++ printk("set the msvdx clock to 0 in the %s\n", __FUNCTION__);
++ PSB_WMSVDX32 (0, MSVDX_MAN_CLK_ENABLE);
+
-+ ptr = (int *) ((*raw))->data;
++ /*Clean up resources...*/
++ if (dev_priv->ccb0)
++ psb_free_ccb (&dev_priv->ccb0);
++ if (dev_priv->ccb1)
++ psb_free_ccb (&dev_priv->ccb1);
+
-+ if (!ptr)
-+ {
-+ PSB_DEBUG_GENERAL ("MSVDX: Failed to load %s\n", name);
-+ return NULL;
-+ }
-+ /*another sanity check... */
-+ if ((*raw)->size !=
-+ (sizeof (struct msvdx_fw) +
-+ sizeof (uint32_t) * ((struct msvdx_fw *) ptr)->text_size +
-+ sizeof (uint32_t) * ((struct msvdx_fw *) ptr)->data_size))
-+ {
-+ PSB_DEBUG_GENERAL ("MSVDX: %s is is not correct size(%zd)\n",
-+ name, (*raw)->size);
-+ return NULL;
-+ }
-+ return ptr;
++ return 0;
+}
+
-+static int
-+psb_setup_fw (struct drm_device *dev)
++int psb_hw_info_ioctl(struct drm_device *dev, void *data,
++ struct drm_file *file_priv)
+{
-+ struct drm_psb_private *dev_priv = dev->dev_private;
-+ int ret = 0;
-+
-+ uint32_t ram_bank_size;
-+ struct msvdx_fw *fw;
-+ uint32_t *fw_ptr = NULL;
-+ uint32_t *text_ptr = NULL;
-+ uint32_t *data_ptr = NULL;
-+ const struct firmware *raw = NULL;
-+ /* todo : Assert the clock is on - if not turn it on to upload code */
-+
-+ PSB_DEBUG_GENERAL ("MSVDX: psb_setup_fw\n");
++ struct drm_psb_private *dev_priv = dev->dev_private;
++ struct drm_psb_hw_info *hw_info = data;
++ struct pci_dev * pci_root = pci_get_bus_and_slot(0, 0);
+
-+ /* Reset MTX */
-+ PSB_WMSVDX32 (MSVDX_MTX_SOFT_RESET_MTX_RESET_MASK, MSVDX_MTX_SOFT_RESET);
++ hw_info->rev_id = dev_priv->psb_rev_id;
+
-+ /* Initialses Communication controll area to 0 */
-+ if(dev_priv->psb_rev_id >= POULSBO_D1)
-+ {
-+ PSB_DEBUG_GENERAL("MSVDX: Detected Poulsbo D1 or later revision.\n");
-+ PSB_WMSVDX32 (MSVDX_DEVICE_NODE_FLAGS_DEFAULT_D1, MSVDX_COMMS_OFFSET_FLAGS);
-+ }
-+ else
-+ {
-+ PSB_DEBUG_GENERAL("MSVDX: Detected Poulsbo D0 or earlier revision.\n");
-+ PSB_WMSVDX32 (MSVDX_DEVICE_NODE_FLAGS_DEFAULT_D0, MSVDX_COMMS_OFFSET_FLAGS);
-+ }
++ /*read the fuse info to determine the caps*/
++ pci_write_config_dword(pci_root, 0xD0, PCI_PORT5_REG80_FFUSE);
++ pci_read_config_dword(pci_root, 0xD4, &hw_info->caps);
+
-+ PSB_WMSVDX32 (0, MSVDX_COMMS_MSG_COUNTER);
-+ PSB_WMSVDX32 (0, MSVDX_COMMS_SIGNATURE);
-+ PSB_WMSVDX32 (0, MSVDX_COMMS_TO_HOST_RD_INDEX);
-+ PSB_WMSVDX32 (0, MSVDX_COMMS_TO_HOST_WRT_INDEX);
-+ PSB_WMSVDX32 (0, MSVDX_COMMS_TO_MTX_RD_INDEX);
-+ PSB_WMSVDX32 (0, MSVDX_COMMS_TO_MTX_WRT_INDEX);
-+ PSB_WMSVDX32 (0, MSVDX_COMMS_FW_STATUS);
++ PSB_DEBUG_GENERAL("MSVDX: PSB caps: 0x%x\n", hw_info->caps);
++ return 0;
++}
+Index: linux-2.6.28/drivers/gpu/drm/psb/psb_reg.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.28/drivers/gpu/drm/psb/psb_reg.h 2009-02-12 09:14:42.000000000 +0000
+@@ -0,0 +1,562 @@
++/**************************************************************************
++ *
++ * Copyright (c) (2005-2007) Imagination Technologies Limited.
++ * Copyright (c) 2007, Intel Corporation.
++ * All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
++ *
++ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
++ * develop this driver.
++ *
++ **************************************************************************/
++/*
++ */
++#ifndef _PSB_REG_H_
++#define _PSB_REG_H_
+
-+ /* read register bank size */
-+ {
-+ uint32_t ui32BankSize, ui32Reg;
-+ ui32Reg = PSB_RMSVDX32 (MSVDX_MTX_RAM_BANK);
-+ ui32BankSize =
-+ REGIO_READ_FIELD (ui32Reg, MSVDX_MTX_RAM_BANK, CR_MTX_RAM_BANK_SIZE);
-+ ram_bank_size = (uint32_t) (1 << (ui32BankSize + 2));
-+ }
++#define PSB_CR_CLKGATECTL 0x0000
++#define _PSB_C_CLKGATECTL_AUTO_MAN_REG (1 << 24)
++#define _PSB_C_CLKGATECTL_USE_CLKG_SHIFT (20)
++#define _PSB_C_CLKGATECTL_USE_CLKG_MASK (0x3 << 20)
++#define _PSB_C_CLKGATECTL_DPM_CLKG_SHIFT (16)
++#define _PSB_C_CLKGATECTL_DPM_CLKG_MASK (0x3 << 16)
++#define _PSB_C_CLKGATECTL_TA_CLKG_SHIFT (12)
++#define _PSB_C_CLKGATECTL_TA_CLKG_MASK (0x3 << 12)
++#define _PSB_C_CLKGATECTL_TSP_CLKG_SHIFT (8)
++#define _PSB_C_CLKGATECTL_TSP_CLKG_MASK (0x3 << 8)
++#define _PSB_C_CLKGATECTL_ISP_CLKG_SHIFT (4)
++#define _PSB_C_CLKGATECTL_ISP_CLKG_MASK (0x3 << 4)
++#define _PSB_C_CLKGATECTL_2D_CLKG_SHIFT (0)
++#define _PSB_C_CLKGATECTL_2D_CLKG_MASK (0x3 << 0)
++#define _PSB_C_CLKGATECTL_CLKG_ENABLED (0)
++#define _PSB_C_CLKGATECTL_CLKG_DISABLED (1)
++#define _PSB_C_CLKGATECTL_CLKG_AUTO (2)
+
-+ PSB_DEBUG_GENERAL ("MSVDX: RAM bank size = %d bytes\n", ram_bank_size);
++#define PSB_CR_CORE_ID 0x0010
++#define _PSB_CC_ID_ID_SHIFT (16)
++#define _PSB_CC_ID_ID_MASK (0xFFFF << 16)
++#define _PSB_CC_ID_CONFIG_SHIFT (0)
++#define _PSB_CC_ID_CONFIG_MASK (0xFFFF << 0)
+
-+ fw_ptr = msvdx_get_fw (dev, &raw, "msvdx_fw.bin");
++#define PSB_CR_CORE_REVISION 0x0014
++#define _PSB_CC_REVISION_DESIGNER_SHIFT (24)
++#define _PSB_CC_REVISION_DESIGNER_MASK (0xFF << 24)
++#define _PSB_CC_REVISION_MAJOR_SHIFT (16)
++#define _PSB_CC_REVISION_MAJOR_MASK (0xFF << 16)
++#define _PSB_CC_REVISION_MINOR_SHIFT (8)
++#define _PSB_CC_REVISION_MINOR_MASK (0xFF << 8)
++#define _PSB_CC_REVISION_MAINTENANCE_SHIFT (0)
++#define _PSB_CC_REVISION_MAINTENANCE_MASK (0xFF << 0)
+
-+ if (!fw_ptr)
-+ {
-+ DRM_ERROR ("psb: No valid msvdx_fw.bin firmware found.\n");
-+ ret = 1;
-+ goto out;
-+ }
++#define PSB_CR_DESIGNER_REV_FIELD1 0x0018
+
-+ fw = (struct msvdx_fw *) fw_ptr;
-+ if (fw->ver != 0x02)
-+ {
-+ DRM_ERROR
-+ ("psb: msvdx_fw.bin firmware version mismatch, got version=%02x expected version=%02x\n",
-+ fw->ver, 0x02);
-+ ret = 1;
-+ goto out;
-+ }
++#define PSB_CR_SOFT_RESET 0x0080
++#define _PSB_CS_RESET_TSP_RESET (1 << 6)
++#define _PSB_CS_RESET_ISP_RESET (1 << 5)
++#define _PSB_CS_RESET_USE_RESET (1 << 4)
++#define _PSB_CS_RESET_TA_RESET (1 << 3)
++#define _PSB_CS_RESET_DPM_RESET (1 << 2)
++#define _PSB_CS_RESET_TWOD_RESET (1 << 1)
++#define _PSB_CS_RESET_BIF_RESET (1 << 0)
+
-+ text_ptr = (uint32_t *) ((uint8_t *) fw_ptr + sizeof (struct msvdx_fw));
-+ data_ptr = text_ptr + fw->text_size;
++#define PSB_CR_DESIGNER_REV_FIELD2 0x001C
+
-+ PSB_DEBUG_GENERAL ("MSVDX: Retrieved pointers for firmware\n");
-+ PSB_DEBUG_GENERAL ("MSVDX: text_size: %d\n", fw->text_size);
-+ PSB_DEBUG_GENERAL ("MSVDX: data_size: %d\n", fw->data_size);
-+ PSB_DEBUG_GENERAL ("MSVDX: data_location: 0x%x\n", fw->data_location);
-+ PSB_DEBUG_GENERAL ("MSVDX: First 4 bytes of text: 0x%x\n", *text_ptr);
-+ PSB_DEBUG_GENERAL ("MSVDX: First 4 bytes of data: 0x%x\n", *data_ptr);
++#define PSB_CR_EVENT_HOST_ENABLE2 0x0110
+
-+ PSB_DEBUG_GENERAL ("MSVDX: Uploading firmware\n");
-+ psb_upload_fw (dev_priv, MTX_CORE_CODE_MEM, ram_bank_size,
-+ PC_START_ADDRESS - MTX_CODE_BASE, fw->text_size, text_ptr);
-+ psb_upload_fw (dev_priv, MTX_CORE_DATA_MEM, ram_bank_size,
-+ fw->data_location - MTX_DATA_BASE, fw->data_size, data_ptr);
++#define PSB_CR_EVENT_STATUS2 0x0118
+
-+ /*todo : Verify code upload possibly only in debug */
-+ if (psb_verify_fw
-+ (dev_priv, ram_bank_size, MTX_CORE_CODE_MEM,
-+ PC_START_ADDRESS - MTX_CODE_BASE, fw->text_size, text_ptr))
-+ {
-+ /* Firmware code upload failed */
-+ ret = 1;
-+ goto out;
-+ }
-+ if (psb_verify_fw
-+ (dev_priv, ram_bank_size, MTX_CORE_DATA_MEM,
-+ fw->data_location - MTX_DATA_BASE, fw->data_size, data_ptr))
-+ {
-+ /* Firmware data upload failed */
-+ ret = 1;
-+ goto out;
-+ }
++#define PSB_CR_EVENT_HOST_CLEAR2 0x0114
++#define _PSB_CE2_BIF_REQUESTER_FAULT (1 << 4)
+
-+ /* -- Set starting PC address */
-+ psb_write_mtx_core_reg (dev_priv, MTX_PC, PC_START_ADDRESS);
++#define PSB_CR_EVENT_STATUS 0x012C
+
-+ /* -- Turn on the thread */
-+ PSB_WMSVDX32 (MSVDX_MTX_ENABLE_MTX_ENABLE_MASK, MSVDX_MTX_ENABLE);
++#define PSB_CR_EVENT_HOST_ENABLE 0x0130
+
-+ /* Wait for the signature value to be written back */
-+ ret = psb_wait_for_register (dev_priv, MSVDX_COMMS_SIGNATURE, MSVDX_COMMS_SIGNATURE_VALUE, /* Required value */
-+ 0xffffffff /* Enabled bits */ );
-+ if (ret)
-+ {
-+ DRM_ERROR ("psb: MSVDX firmware fails to initialize.\n");
-+ goto out;
-+ }
++#define PSB_CR_EVENT_HOST_CLEAR 0x0134
++#define _PSB_CE_MASTER_INTERRUPT (1 << 31)
++#define _PSB_CE_TA_DPM_FAULT (1 << 28)
++#define _PSB_CE_TWOD_COMPLETE (1 << 27)
++#define _PSB_CE_DPM_OUT_OF_MEMORY_ZLS (1 << 25)
++#define _PSB_CE_DPM_TA_MEM_FREE (1 << 24)
++#define _PSB_CE_PIXELBE_END_RENDER (1 << 18)
++#define _PSB_CE_SW_EVENT (1 << 14)
++#define _PSB_CE_TA_FINISHED (1 << 13)
++#define _PSB_CE_TA_TERMINATE (1 << 12)
++#define _PSB_CE_DPM_REACHED_MEM_THRESH (1 << 3)
++#define _PSB_CE_DPM_OUT_OF_MEMORY_GBL (1 << 2)
++#define _PSB_CE_DPM_OUT_OF_MEMORY_MT (1 << 1)
++#define _PSB_CE_DPM_3D_MEM_FREE (1 << 0)
+
-+ PSB_DEBUG_GENERAL ("MSVDX: MTX Initial indications OK\n");
-+ PSB_DEBUG_GENERAL ("MSVDX: MSVDX_COMMS_AREA_ADDR = %08x\n",
-+ MSVDX_COMMS_AREA_ADDR);
-+out:
-+ if (raw)
-+ {
-+ PSB_DEBUG_GENERAL ("MSVDX releasing firmware resouces....\n");
-+ release_firmware (raw);
-+ }
-+ return ret;
-+}
+
-+static void
-+psb_free_ccb (struct drm_buffer_object **ccb)
-+{
-+ drm_bo_usage_deref_unlocked (ccb);
-+ *ccb = NULL;
-+}
++#define PSB_USE_OFFSET_MASK 0x0007FFFF
++#define PSB_USE_OFFSET_SIZE (PSB_USE_OFFSET_MASK + 1)
++#define PSB_CR_USE_CODE_BASE0 0x0A0C
++#define PSB_CR_USE_CODE_BASE1 0x0A10
++#define PSB_CR_USE_CODE_BASE2 0x0A14
++#define PSB_CR_USE_CODE_BASE3 0x0A18
++#define PSB_CR_USE_CODE_BASE4 0x0A1C
++#define PSB_CR_USE_CODE_BASE5 0x0A20
++#define PSB_CR_USE_CODE_BASE6 0x0A24
++#define PSB_CR_USE_CODE_BASE7 0x0A28
++#define PSB_CR_USE_CODE_BASE8 0x0A2C
++#define PSB_CR_USE_CODE_BASE9 0x0A30
++#define PSB_CR_USE_CODE_BASE10 0x0A34
++#define PSB_CR_USE_CODE_BASE11 0x0A38
++#define PSB_CR_USE_CODE_BASE12 0x0A3C
++#define PSB_CR_USE_CODE_BASE13 0x0A40
++#define PSB_CR_USE_CODE_BASE14 0x0A44
++#define PSB_CR_USE_CODE_BASE15 0x0A48
++#define PSB_CR_USE_CODE_BASE(_i) (0x0A0C + ((_i) << 2))
++#define _PSB_CUC_BASE_DM_SHIFT (25)
++#define _PSB_CUC_BASE_DM_MASK (0x3 << 25)
++#define _PSB_CUC_BASE_ADDR_SHIFT (0) // 1024-bit aligned address?
++#define _PSB_CUC_BASE_ADDR_ALIGNSHIFT (7)
++#define _PSB_CUC_BASE_ADDR_MASK (0x1FFFFFF << 0)
++#define _PSB_CUC_DM_VERTEX (0)
++#define _PSB_CUC_DM_PIXEL (1)
++#define _PSB_CUC_DM_RESERVED (2)
++#define _PSB_CUC_DM_EDM (3)
+
-+/*******************************************************************************
++#define PSB_CR_PDS_EXEC_BASE 0x0AB8
++#define _PSB_CR_PDS_EXEC_BASE_ADDR_SHIFT (20) // 1MB aligned address
++#define _PSB_CR_PDS_EXEC_BASE_ADDR_ALIGNSHIFT (20)
+
-+ @Function psb_msvdx_reset
++#define PSB_CR_EVENT_KICKER 0x0AC4
++#define _PSB_CE_KICKER_ADDRESS_SHIFT (4) // 128-bit aligned address
+
-+ @Description
++#define PSB_CR_EVENT_KICK 0x0AC8
++#define _PSB_CE_KICK_NOW (1 << 0)
+
-+ Reset chip and disable interrupts.
+
-+ @Input psDeviceNode - device info. structure
++#define PSB_CR_BIF_DIR_LIST_BASE1 0x0C38
+
-+ @Return 0 - Success
-+ 1 - Failure
++#define PSB_CR_BIF_CTRL 0x0C00
++#define _PSB_CB_CTRL_CLEAR_FAULT (1 << 4)
++#define _PSB_CB_CTRL_INVALDC (1 << 3)
++#define _PSB_CB_CTRL_FLUSH (1 << 2)
+
-+******************************************************************************/
-+int
-+psb_msvdx_reset (struct drm_psb_private *dev_priv)
-+{
-+ int ret = 0;
++#define PSB_CR_BIF_INT_STAT 0x0C04
+
-+ /* Issue software reset */
-+ PSB_WMSVDX32 (msvdx_sw_reset_all, MSVDX_CONTROL);
++#define PSB_CR_BIF_FAULT 0x0C08
++#define _PSB_CBI_STAT_PF_N_RW (1 << 14)
++#define _PSB_CBI_STAT_FAULT_SHIFT (0)
++#define _PSB_CBI_STAT_FAULT_MASK (0x3FFF << 0)
++#define _PSB_CBI_STAT_FAULT_CACHE (1 << 1)
++#define _PSB_CBI_STAT_FAULT_TA (1 << 2)
++#define _PSB_CBI_STAT_FAULT_VDM (1 << 3)
++#define _PSB_CBI_STAT_FAULT_2D (1 << 4)
++#define _PSB_CBI_STAT_FAULT_PBE (1 << 5)
++#define _PSB_CBI_STAT_FAULT_TSP (1 << 6)
++#define _PSB_CBI_STAT_FAULT_ISP (1 << 7)
++#define _PSB_CBI_STAT_FAULT_USSEPDS (1 << 8)
++#define _PSB_CBI_STAT_FAULT_HOST (1 << 9)
+
-+ ret = psb_wait_for_register (dev_priv, MSVDX_CONTROL, 0, /* Required value */
-+ MSVDX_CONTROL_CR_MSVDX_SOFT_RESET_MASK
-+ /* Enabled bits */ );
++#define PSB_CR_BIF_BANK0 0x0C78
+
-+ if (!ret)
-+ {
-+ /* Clear interrupt enabled flag */
-+ PSB_WMSVDX32 (0, MSVDX_HOST_INTERRUPT_ENABLE);
++#define PSB_CR_BIF_BANK1 0x0C7C
+
-+ /* Clear any pending interrupt flags */
-+ PSB_WMSVDX32 (0xFFFFFFFF, MSVDX_INTERRUPT_CLEAR);
-+ }
++#define PSB_CR_BIF_DIR_LIST_BASE0 0x0C84
+
-+ mutex_destroy (&dev_priv->msvdx_mutex);
++#define PSB_CR_BIF_TWOD_REQ_BASE 0x0C88
++#define PSB_CR_BIF_3D_REQ_BASE 0x0CAC
+
-+ return ret;
-+}
++#define PSB_CR_2D_SOCIF 0x0E18
++#define _PSB_C2_SOCIF_FREESPACE_SHIFT (0)
++#define _PSB_C2_SOCIF_FREESPACE_MASK (0xFF << 0)
++#define _PSB_C2_SOCIF_EMPTY (0x80 << 0)
+
-+static int
-+psb_allocate_ccb (struct drm_device *dev,
-+ struct drm_buffer_object **ccb,
-+ uint32_t * base_addr, int size)
-+{
-+ int ret;
-+ struct drm_bo_kmap_obj tmp_kmap;
-+ int is_iomem;
++#define PSB_CR_2D_BLIT_STATUS 0x0E04
++#define _PSB_C2B_STATUS_BUSY (1 << 24)
++#define _PSB_C2B_STATUS_COMPLETE_SHIFT (0)
++#define _PSB_C2B_STATUS_COMPLETE_MASK (0xFFFFFF << 0)
+
-+ ret = drm_buffer_object_create (dev, size,
-+ drm_bo_type_kernel,
-+ DRM_BO_FLAG_READ |
-+ DRM_PSB_FLAG_MEM_KERNEL |
-+ DRM_BO_FLAG_NO_EVICT,
-+ DRM_BO_HINT_DONT_FENCE, 0, 0, ccb);
-+ if (ret)
-+ {
-+ PSB_DEBUG_GENERAL ("Failed to allocate CCB.\n");
-+ *ccb = NULL;
-+ return 1;
-+ }
++/*
++ * 2D defs.
++ */
+
-+ ret = drm_bo_kmap (*ccb, 0, (*ccb)->num_pages, &tmp_kmap);
-+ if (ret)
-+ {
-+ PSB_DEBUG_GENERAL ("drm_bo_kmap failed ret: %d\n", ret);
-+ drm_bo_usage_deref_unlocked (ccb);
-+ *ccb = NULL;
-+ return 1;
-+ }
++/*
++ * 2D Slave Port Data : Block Header's Object Type
++ */
+
-+ memset (drm_bmo_virtual (&tmp_kmap, &is_iomem), 0, size);
-+ drm_bo_kunmap (&tmp_kmap);
++#define PSB_2D_CLIP_BH (0x00000000)
++#define PSB_2D_PAT_BH (0x10000000)
++#define PSB_2D_CTRL_BH (0x20000000)
++#define PSB_2D_SRC_OFF_BH (0x30000000)
++#define PSB_2D_MASK_OFF_BH (0x40000000)
++#define PSB_2D_RESERVED1_BH (0x50000000)
++#define PSB_2D_RESERVED2_BH (0x60000000)
++#define PSB_2D_FENCE_BH (0x70000000)
++#define PSB_2D_BLIT_BH (0x80000000)
++#define PSB_2D_SRC_SURF_BH (0x90000000)
++#define PSB_2D_DST_SURF_BH (0xA0000000)
++#define PSB_2D_PAT_SURF_BH (0xB0000000)
++#define PSB_2D_SRC_PAL_BH (0xC0000000)
++#define PSB_2D_PAT_PAL_BH (0xD0000000)
++#define PSB_2D_MASK_SURF_BH (0xE0000000)
++#define PSB_2D_FLUSH_BH (0xF0000000)
+
-+ *base_addr = (*ccb)->offset;
-+ return 0;
-+}
++/*
++ * Clip Definition block (PSB_2D_CLIP_BH)
++ */
++#define PSB_2D_CLIPCOUNT_MAX (1)
++#define PSB_2D_CLIPCOUNT_MASK (0x00000000)
++#define PSB_2D_CLIPCOUNT_CLRMASK (0xFFFFFFFF)
++#define PSB_2D_CLIPCOUNT_SHIFT (0)
++// clip rectangle min & max
++#define PSB_2D_CLIP_XMAX_MASK (0x00FFF000)
++#define PSB_2D_CLIP_XMAX_CLRMASK (0xFF000FFF)
++#define PSB_2D_CLIP_XMAX_SHIFT (12)
++#define PSB_2D_CLIP_XMIN_MASK (0x00000FFF)
++#define PSB_2D_CLIP_XMIN_CLRMASK (0x00FFF000)
++#define PSB_2D_CLIP_XMIN_SHIFT (0)
++// clip rectangle offset
++#define PSB_2D_CLIP_YMAX_MASK (0x00FFF000)
++#define PSB_2D_CLIP_YMAX_CLRMASK (0xFF000FFF)
++#define PSB_2D_CLIP_YMAX_SHIFT (12)
++#define PSB_2D_CLIP_YMIN_MASK (0x00000FFF)
++#define PSB_2D_CLIP_YMIN_CLRMASK (0x00FFF000)
++#define PSB_2D_CLIP_YMIN_SHIFT (0)
+
-+int
-+psb_msvdx_init (struct drm_device *dev)
-+{
-+ struct drm_psb_private *dev_priv = dev->dev_private;
-+ uint32_t ui32Cmd;
-+ int ret;
++/*
++ * Pattern Control (PSB_2D_PAT_BH)
++ */
++#define PSB_2D_PAT_HEIGHT_MASK (0x0000001F)
++#define PSB_2D_PAT_HEIGHT_SHIFT (0)
++#define PSB_2D_PAT_WIDTH_MASK (0x000003E0)
++#define PSB_2D_PAT_WIDTH_SHIFT (5)
++#define PSB_2D_PAT_YSTART_MASK (0x00007C00)
++#define PSB_2D_PAT_YSTART_SHIFT (10)
++#define PSB_2D_PAT_XSTART_MASK (0x000F8000)
++#define PSB_2D_PAT_XSTART_SHIFT (15)
+
-+ PSB_DEBUG_GENERAL ("MSVDX: psb_msvdx_init\n");
++/*
++ * 2D Control block (PSB_2D_CTRL_BH)
++ */
++// Present Flags
++#define PSB_2D_SRCCK_CTRL (0x00000001)
++#define PSB_2D_DSTCK_CTRL (0x00000002)
++#define PSB_2D_ALPHA_CTRL (0x00000004)
++// Colour Key Colour (SRC/DST)
++#define PSB_2D_CK_COL_MASK (0xFFFFFFFF)
++#define PSB_2D_CK_COL_CLRMASK (0x00000000)
++#define PSB_2D_CK_COL_SHIFT (0)
++// Colour Key Mask (SRC/DST)
++#define PSB_2D_CK_MASK_MASK (0xFFFFFFFF)
++#define PSB_2D_CK_MASK_CLRMASK (0x00000000)
++#define PSB_2D_CK_MASK_SHIFT (0)
++// Alpha Control (Alpha/RGB)
++#define PSB_2D_GBLALPHA_MASK (0x000FF000)
++#define PSB_2D_GBLALPHA_CLRMASK (0xFFF00FFF)
++#define PSB_2D_GBLALPHA_SHIFT (12)
++#define PSB_2D_SRCALPHA_OP_MASK (0x00700000)
++#define PSB_2D_SRCALPHA_OP_CLRMASK (0xFF8FFFFF)
++#define PSB_2D_SRCALPHA_OP_SHIFT (20)
++#define PSB_2D_SRCALPHA_OP_ONE (0x00000000)
++#define PSB_2D_SRCALPHA_OP_SRC (0x00100000)
++#define PSB_2D_SRCALPHA_OP_DST (0x00200000)
++#define PSB_2D_SRCALPHA_OP_SG (0x00300000)
++#define PSB_2D_SRCALPHA_OP_DG (0x00400000)
++#define PSB_2D_SRCALPHA_OP_GBL (0x00500000)
++#define PSB_2D_SRCALPHA_OP_ZERO (0x00600000)
++#define PSB_2D_SRCALPHA_INVERT (0x00800000)
++#define PSB_2D_SRCALPHA_INVERT_CLR (0xFF7FFFFF)
++#define PSB_2D_DSTALPHA_OP_MASK (0x07000000)
++#define PSB_2D_DSTALPHA_OP_CLRMASK (0xF8FFFFFF)
++#define PSB_2D_DSTALPHA_OP_SHIFT (24)
++#define PSB_2D_DSTALPHA_OP_ONE (0x00000000)
++#define PSB_2D_DSTALPHA_OP_SRC (0x01000000)
++#define PSB_2D_DSTALPHA_OP_DST (0x02000000)
++#define PSB_2D_DSTALPHA_OP_SG (0x03000000)
++#define PSB_2D_DSTALPHA_OP_DG (0x04000000)
++#define PSB_2D_DSTALPHA_OP_GBL (0x05000000)
++#define PSB_2D_DSTALPHA_OP_ZERO (0x06000000)
++#define PSB_2D_DSTALPHA_INVERT (0x08000000)
++#define PSB_2D_DSTALPHA_INVERT_CLR (0xF7FFFFFF)
+
-+ /*Initialize command msvdx queueing */
-+ INIT_LIST_HEAD (&dev_priv->msvdx_queue);
-+ mutex_init (&dev_priv->msvdx_mutex);
-+ spin_lock_init (&dev_priv->msvdx_lock);
-+ dev_priv->msvdx_busy = 0;
++#define PSB_2D_PRE_MULTIPLICATION_ENABLE (0x10000000)
++#define PSB_2D_PRE_MULTIPLICATION_CLRMASK (0xEFFFFFFF)
++#define PSB_2D_ZERO_SOURCE_ALPHA_ENABLE (0x20000000)
++#define PSB_2D_ZERO_SOURCE_ALPHA_CLRMASK (0xDFFFFFFF)
+
-+ /*figure out the stepping*/
-+ pci_read_config_byte(dev->pdev, PSB_REVID_OFFSET, &dev_priv->psb_rev_id );
++/*
++ *Source Offset (PSB_2D_SRC_OFF_BH)
++ */
++#define PSB_2D_SRCOFF_XSTART_MASK ((0x00000FFF) << 12)
++#define PSB_2D_SRCOFF_XSTART_SHIFT (12)
++#define PSB_2D_SRCOFF_YSTART_MASK (0x00000FFF)
++#define PSB_2D_SRCOFF_YSTART_SHIFT (0)
+
-+ /* Enable Clocks */
-+ PSB_DEBUG_GENERAL ("Enabling clocks\n");
-+ PSB_WMSVDX32 (clk_enable_all, MSVDX_MAN_CLK_ENABLE);
++/*
++ * Mask Offset (PSB_2D_MASK_OFF_BH)
++ */
++#define PSB_2D_MASKOFF_XSTART_MASK ((0x00000FFF) << 12)
++#define PSB_2D_MASKOFF_XSTART_SHIFT (12)
++#define PSB_2D_MASKOFF_YSTART_MASK (0x00000FFF)
++#define PSB_2D_MASKOFF_YSTART_SHIFT (0)
+
-+ /* Enable MMU by removing all bypass bits */
-+ PSB_WMSVDX32 (0, MSVDX_MMU_CONTROL0);
++/*
++ * 2D Fence (see PSB_2D_FENCE_BH): bits 0:27 are ignored
++ */
+
-+ PSB_DEBUG_GENERAL ("MSVDX: Setting up RENDEC\n");
-+ /* Allocate device virtual memory as required by rendec.... */
-+ if (!dev_priv->ccb0)
-+ {
-+ ret =
-+ psb_allocate_ccb (dev, &dev_priv->ccb0,
-+ &dev_priv->base_addr0, RENDEC_A_SIZE);
-+ if (ret)
-+ goto err_exit;
-+ }
++/*
++ *Blit Rectangle (PSB_2D_BLIT_BH)
++ */
+
-+ if (!dev_priv->ccb1)
-+ {
-+ ret =
-+ psb_allocate_ccb (dev, &dev_priv->ccb1,
-+ &dev_priv->base_addr1, RENDEC_B_SIZE);
-+ if (ret)
-+ goto err_exit;
-+ }
++#define PSB_2D_ROT_MASK (3<<25)
++#define PSB_2D_ROT_CLRMASK (~PSB_2D_ROT_MASK)
++#define PSB_2D_ROT_NONE (0<<25)
++#define PSB_2D_ROT_90DEGS (1<<25)
++#define PSB_2D_ROT_180DEGS (2<<25)
++#define PSB_2D_ROT_270DEGS (3<<25)
+
-+ PSB_DEBUG_GENERAL ("MSVDX: RENDEC A: %08x RENDEC B: %08x\n",
-+ dev_priv->base_addr0, dev_priv->base_addr1);
++#define PSB_2D_COPYORDER_MASK (3<<23)
++#define PSB_2D_COPYORDER_CLRMASK (~PSB_2D_COPYORDER_MASK)
++#define PSB_2D_COPYORDER_TL2BR (0<<23)
++#define PSB_2D_COPYORDER_BR2TL (1<<23)
++#define PSB_2D_COPYORDER_TR2BL (2<<23)
++#define PSB_2D_COPYORDER_BL2TR (3<<23)
+
-+ PSB_WMSVDX32 (dev_priv->base_addr0, MSVDX_RENDEC_BASE_ADDR0);
-+ PSB_WMSVDX32 (dev_priv->base_addr1, MSVDX_RENDEC_BASE_ADDR1);
++#define PSB_2D_DSTCK_CLRMASK (0xFF9FFFFF)
++#define PSB_2D_DSTCK_DISABLE (0x00000000)
++#define PSB_2D_DSTCK_PASS (0x00200000)
++#define PSB_2D_DSTCK_REJECT (0x00400000)
+
-+ ui32Cmd = 0;
-+ REGIO_WRITE_FIELD (ui32Cmd, MSVDX_RENDEC_BUFFER_SIZE,
-+ RENDEC_BUFFER_SIZE0, RENDEC_A_SIZE / 4096);
-+ REGIO_WRITE_FIELD (ui32Cmd, MSVDX_RENDEC_BUFFER_SIZE,
-+ RENDEC_BUFFER_SIZE1, RENDEC_B_SIZE / 4096);
-+ PSB_WMSVDX32 (ui32Cmd, MSVDX_RENDEC_BUFFER_SIZE);
++#define PSB_2D_SRCCK_CLRMASK (0xFFE7FFFF)
++#define PSB_2D_SRCCK_DISABLE (0x00000000)
++#define PSB_2D_SRCCK_PASS (0x00080000)
++#define PSB_2D_SRCCK_REJECT (0x00100000)
+
-+ ui32Cmd = 0;
-+ REGIO_WRITE_FIELD (ui32Cmd, MSVDX_RENDEC_CONTROL1,
-+ RENDEC_DECODE_START_SIZE, 0);
-+ REGIO_WRITE_FIELD (ui32Cmd, MSVDX_RENDEC_CONTROL1, RENDEC_BURST_SIZE_W, 1);
-+ REGIO_WRITE_FIELD (ui32Cmd, MSVDX_RENDEC_CONTROL1, RENDEC_BURST_SIZE_R, 1);
-+ REGIO_WRITE_FIELD (ui32Cmd, MSVDX_RENDEC_CONTROL1,
-+ RENDEC_EXTERNAL_MEMORY, 1);
-+ PSB_WMSVDX32 (ui32Cmd, MSVDX_RENDEC_CONTROL1);
++#define PSB_2D_CLIP_ENABLE (0x00040000)
+
-+ ui32Cmd = 0x00101010;
-+ PSB_WMSVDX32 (ui32Cmd, MSVDX_RENDEC_CONTEXT0);
-+ PSB_WMSVDX32 (ui32Cmd, MSVDX_RENDEC_CONTEXT1);
-+ PSB_WMSVDX32 (ui32Cmd, MSVDX_RENDEC_CONTEXT2);
-+ PSB_WMSVDX32 (ui32Cmd, MSVDX_RENDEC_CONTEXT3);
-+ PSB_WMSVDX32 (ui32Cmd, MSVDX_RENDEC_CONTEXT4);
-+ PSB_WMSVDX32 (ui32Cmd, MSVDX_RENDEC_CONTEXT5);
-+
-+ ui32Cmd = 0;
-+ REGIO_WRITE_FIELD (ui32Cmd, MSVDX_RENDEC_CONTROL0, RENDEC_INITIALISE, 1);
-+ PSB_WMSVDX32 (ui32Cmd, MSVDX_RENDEC_CONTROL0);
++#define PSB_2D_ALPHA_ENABLE (0x00020000)
+
-+ ret = psb_setup_fw (dev);
-+ if (ret)
-+ goto err_exit;
++#define PSB_2D_PAT_CLRMASK (0xFFFEFFFF)
++#define PSB_2D_PAT_MASK (0x00010000)
++#define PSB_2D_USE_PAT (0x00010000)
++#define PSB_2D_USE_FILL (0x00000000)
++/*
++ * Tungsten Graphics note on rop codes: If rop A and rop B are
++ * identical, the mask surface will not be read and need not be
++ * set up.
++ */
+
-+ PSB_WMSVDX32 (clk_enable_minimal, MSVDX_MAN_CLK_ENABLE);
++#define PSB_2D_ROP3B_MASK (0x0000FF00)
++#define PSB_2D_ROP3B_CLRMASK (0xFFFF00FF)
++#define PSB_2D_ROP3B_SHIFT (8)
++// rop code A
++#define PSB_2D_ROP3A_MASK (0x000000FF)
++#define PSB_2D_ROP3A_CLRMASK (0xFFFFFF00)
++#define PSB_2D_ROP3A_SHIFT (0)
+
-+ return 0;
++#define PSB_2D_ROP4_MASK (0x0000FFFF)
++/*
++ * DWORD0: (Only pass if Pattern control == Use Fill Colour)
++ * Fill Colour RGBA8888
++ */
++#define PSB_2D_FILLCOLOUR_MASK (0xFFFFFFFF)
++#define PSB_2D_FILLCOLOUR_SHIFT (0)
++/*
++ * DWORD1: (Always Present)
++ * X Start (Dest)
++ * Y Start (Dest)
++ */
++#define PSB_2D_DST_XSTART_MASK (0x00FFF000)
++#define PSB_2D_DST_XSTART_CLRMASK (0xFF000FFF)
++#define PSB_2D_DST_XSTART_SHIFT (12)
++#define PSB_2D_DST_YSTART_MASK (0x00000FFF)
++#define PSB_2D_DST_YSTART_CLRMASK (0xFFFFF000)
++#define PSB_2D_DST_YSTART_SHIFT (0)
++/*
++ * DWORD2: (Always Present)
++ * X Size (Dest)
++ * Y Size (Dest)
++ */
++#define PSB_2D_DST_XSIZE_MASK (0x00FFF000)
++#define PSB_2D_DST_XSIZE_CLRMASK (0xFF000FFF)
++#define PSB_2D_DST_XSIZE_SHIFT (12)
++#define PSB_2D_DST_YSIZE_MASK (0x00000FFF)
++#define PSB_2D_DST_YSIZE_CLRMASK (0xFFFFF000)
++#define PSB_2D_DST_YSIZE_SHIFT (0)
+
-+err_exit:
-+ if (dev_priv->ccb0)
-+ psb_free_ccb (&dev_priv->ccb0);
-+ if (dev_priv->ccb1)
-+ psb_free_ccb (&dev_priv->ccb1);
++/*
++ * Source Surface (PSB_2D_SRC_SURF_BH)
++ */
++/*
++ * WORD 0
++ */
+
-+ return 1;
-+}
++#define PSB_2D_SRC_FORMAT_MASK (0x00078000)
++#define PSB_2D_SRC_1_PAL (0x00000000)
++#define PSB_2D_SRC_2_PAL (0x00008000)
++#define PSB_2D_SRC_4_PAL (0x00010000)
++#define PSB_2D_SRC_8_PAL (0x00018000)
++#define PSB_2D_SRC_8_ALPHA (0x00020000)
++#define PSB_2D_SRC_4_ALPHA (0x00028000)
++#define PSB_2D_SRC_332RGB (0x00030000)
++#define PSB_2D_SRC_4444ARGB (0x00038000)
++#define PSB_2D_SRC_555RGB (0x00040000)
++#define PSB_2D_SRC_1555ARGB (0x00048000)
++#define PSB_2D_SRC_565RGB (0x00050000)
++#define PSB_2D_SRC_0888ARGB (0x00058000)
++#define PSB_2D_SRC_8888ARGB (0x00060000)
++#define PSB_2D_SRC_8888UYVY (0x00068000)
++#define PSB_2D_SRC_RESERVED (0x00070000)
++#define PSB_2D_SRC_1555ARGB_LOOKUP (0x00078000)
+
-+int
-+psb_msvdx_uninit (struct drm_device *dev)
-+{
-+ struct drm_psb_private *dev_priv = dev->dev_private;
+
-+ /*Reset MSVDX chip */
-+ psb_msvdx_reset (dev_priv);
++#define PSB_2D_SRC_STRIDE_MASK (0x00007FFF)
++#define PSB_2D_SRC_STRIDE_CLRMASK (0xFFFF8000)
++#define PSB_2D_SRC_STRIDE_SHIFT (0)
++/*
++ * WORD 1 - Base Address
++ */
++#define PSB_2D_SRC_ADDR_MASK (0x0FFFFFFC)
++#define PSB_2D_SRC_ADDR_CLRMASK (0x00000003)
++#define PSB_2D_SRC_ADDR_SHIFT (2)
++#define PSB_2D_SRC_ADDR_ALIGNSHIFT (2)
+
-+// PSB_WMSVDX32 (clk_enable_minimal, MSVDX_MAN_CLK_ENABLE);
-+ printk("set the msvdx clock to 0 in the %s\n", __FUNCTION__);
-+ PSB_WMSVDX32 (0, MSVDX_MAN_CLK_ENABLE);
++/*
++ * Pattern Surface (PSB_2D_PAT_SURF_BH)
++ */
++/*
++ * WORD 0
++ */
+
-+ /*Clean up resources...*/
-+ if (dev_priv->ccb0)
-+ psb_free_ccb (&dev_priv->ccb0);
-+ if (dev_priv->ccb1)
-+ psb_free_ccb (&dev_priv->ccb1);
++#define PSB_2D_PAT_FORMAT_MASK (0x00078000)
++#define PSB_2D_PAT_1_PAL (0x00000000)
++#define PSB_2D_PAT_2_PAL (0x00008000)
++#define PSB_2D_PAT_4_PAL (0x00010000)
++#define PSB_2D_PAT_8_PAL (0x00018000)
++#define PSB_2D_PAT_8_ALPHA (0x00020000)
++#define PSB_2D_PAT_4_ALPHA (0x00028000)
++#define PSB_2D_PAT_332RGB (0x00030000)
++#define PSB_2D_PAT_4444ARGB (0x00038000)
++#define PSB_2D_PAT_555RGB (0x00040000)
++#define PSB_2D_PAT_1555ARGB (0x00048000)
++#define PSB_2D_PAT_565RGB (0x00050000)
++#define PSB_2D_PAT_0888ARGB (0x00058000)
++#define PSB_2D_PAT_8888ARGB (0x00060000)
+
-+ return 0;
-+}
++#define PSB_2D_PAT_STRIDE_MASK (0x00007FFF)
++#define PSB_2D_PAT_STRIDE_CLRMASK (0xFFFF8000)
++#define PSB_2D_PAT_STRIDE_SHIFT (0)
++/*
++ * WORD 1 - Base Address
++ */
++#define PSB_2D_PAT_ADDR_MASK (0x0FFFFFFC)
++#define PSB_2D_PAT_ADDR_CLRMASK (0x00000003)
++#define PSB_2D_PAT_ADDR_SHIFT (2)
++#define PSB_2D_PAT_ADDR_ALIGNSHIFT (2)
+
-+int psb_hw_info_ioctl(struct drm_device *dev, void *data,
-+ struct drm_file *file_priv)
-+{
-+ struct drm_psb_private *dev_priv = dev->dev_private;
-+ struct drm_psb_hw_info *hw_info = data;
-+ struct pci_dev * pci_root = pci_get_bus_and_slot(0, 0);
++/*
++ * Destination Surface (PSB_2D_DST_SURF_BH)
++ */
++/*
++ * WORD 0
++ */
+
-+ hw_info->rev_id = dev_priv->psb_rev_id;
++#define PSB_2D_DST_FORMAT_MASK (0x00078000)
++#define PSB_2D_DST_332RGB (0x00030000)
++#define PSB_2D_DST_4444ARGB (0x00038000)
++#define PSB_2D_DST_555RGB (0x00040000)
++#define PSB_2D_DST_1555ARGB (0x00048000)
++#define PSB_2D_DST_565RGB (0x00050000)
++#define PSB_2D_DST_0888ARGB (0x00058000)
++#define PSB_2D_DST_8888ARGB (0x00060000)
++#define PSB_2D_DST_8888AYUV (0x00070000)
+
-+ /*read the fuse info to determine the caps*/
-+ pci_write_config_dword(pci_root, 0xD0, PCI_PORT5_REG80_FFUSE);
-+ pci_read_config_dword(pci_root, 0xD4, &hw_info->caps);
++#define PSB_2D_DST_STRIDE_MASK (0x00007FFF)
++#define PSB_2D_DST_STRIDE_CLRMASK (0xFFFF8000)
++#define PSB_2D_DST_STRIDE_SHIFT (0)
++/*
++ * WORD 1 - Base Address
++ */
++#define PSB_2D_DST_ADDR_MASK (0x0FFFFFFC)
++#define PSB_2D_DST_ADDR_CLRMASK (0x00000003)
++#define PSB_2D_DST_ADDR_SHIFT (2)
++#define PSB_2D_DST_ADDR_ALIGNSHIFT (2)
+
-+ PSB_DEBUG_GENERAL("MSVDX: PSB caps: 0x%x\n", hw_info->caps);
-+ return 0;
-+}
-Index: linux-2.6.28/drivers/gpu/drm/psb/psb_reg.h
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/psb/psb_reg.h 2009-02-12 09:14:42.000000000 +0000
-@@ -0,0 +1,562 @@
-+/**************************************************************************
-+ *
-+ * Copyright (c) (2005-2007) Imagination Technologies Limited.
-+ * Copyright (c) 2007, Intel Corporation.
-+ * All Rights Reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms and conditions of the GNU General Public License,
-+ * version 2, as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
-+ *
-+ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
-+ * develop this driver.
-+ *
-+ **************************************************************************/
+/*
++ * Mask Surface (PSB_2D_MASK_SURF_BH)
+ */
-+#ifndef _PSB_REG_H_
-+#define _PSB_REG_H_
++/*
++ * WORD 0
++ */
++#define PSB_2D_MASK_STRIDE_MASK (0x00007FFF)
++#define PSB_2D_MASK_STRIDE_CLRMASK (0xFFFF8000)
++#define PSB_2D_MASK_STRIDE_SHIFT (0)
++/*
++ * WORD 1 - Base Address
++ */
++#define PSB_2D_MASK_ADDR_MASK (0x0FFFFFFC)
++#define PSB_2D_MASK_ADDR_CLRMASK (0x00000003)
++#define PSB_2D_MASK_ADDR_SHIFT (2)
++#define PSB_2D_MASK_ADDR_ALIGNSHIFT (2)
+
-+#define PSB_CR_CLKGATECTL 0x0000
-+#define _PSB_C_CLKGATECTL_AUTO_MAN_REG (1 << 24)
-+#define _PSB_C_CLKGATECTL_USE_CLKG_SHIFT (20)
-+#define _PSB_C_CLKGATECTL_USE_CLKG_MASK (0x3 << 20)
-+#define _PSB_C_CLKGATECTL_DPM_CLKG_SHIFT (16)
-+#define _PSB_C_CLKGATECTL_DPM_CLKG_MASK (0x3 << 16)
-+#define _PSB_C_CLKGATECTL_TA_CLKG_SHIFT (12)
-+#define _PSB_C_CLKGATECTL_TA_CLKG_MASK (0x3 << 12)
-+#define _PSB_C_CLKGATECTL_TSP_CLKG_SHIFT (8)
-+#define _PSB_C_CLKGATECTL_TSP_CLKG_MASK (0x3 << 8)
-+#define _PSB_C_CLKGATECTL_ISP_CLKG_SHIFT (4)
-+#define _PSB_C_CLKGATECTL_ISP_CLKG_MASK (0x3 << 4)
-+#define _PSB_C_CLKGATECTL_2D_CLKG_SHIFT (0)
-+#define _PSB_C_CLKGATECTL_2D_CLKG_MASK (0x3 << 0)
-+#define _PSB_C_CLKGATECTL_CLKG_ENABLED (0)
-+#define _PSB_C_CLKGATECTL_CLKG_DISABLED (1)
-+#define _PSB_C_CLKGATECTL_CLKG_AUTO (2)
++/*
++ * Source Palette (PSB_2D_SRC_PAL_BH)
++ */
+
-+#define PSB_CR_CORE_ID 0x0010
-+#define _PSB_CC_ID_ID_SHIFT (16)
-+#define _PSB_CC_ID_ID_MASK (0xFFFF << 16)
-+#define _PSB_CC_ID_CONFIG_SHIFT (0)
-+#define _PSB_CC_ID_CONFIG_MASK (0xFFFF << 0)
++#define PSB_2D_SRCPAL_ADDR_SHIFT (0)
++#define PSB_2D_SRCPAL_ADDR_CLRMASK (0xF0000007)
++#define PSB_2D_SRCPAL_ADDR_MASK (0x0FFFFFF8)
++#define PSB_2D_SRCPAL_BYTEALIGN (1024)
+
-+#define PSB_CR_CORE_REVISION 0x0014
-+#define _PSB_CC_REVISION_DESIGNER_SHIFT (24)
-+#define _PSB_CC_REVISION_DESIGNER_MASK (0xFF << 24)
-+#define _PSB_CC_REVISION_MAJOR_SHIFT (16)
-+#define _PSB_CC_REVISION_MAJOR_MASK (0xFF << 16)
-+#define _PSB_CC_REVISION_MINOR_SHIFT (8)
-+#define _PSB_CC_REVISION_MINOR_MASK (0xFF << 8)
-+#define _PSB_CC_REVISION_MAINTENANCE_SHIFT (0)
-+#define _PSB_CC_REVISION_MAINTENANCE_MASK (0xFF << 0)
++/*
++ * Pattern Palette (PSB_2D_PAT_PAL_BH)
++ */
+
-+#define PSB_CR_DESIGNER_REV_FIELD1 0x0018
++#define PSB_2D_PATPAL_ADDR_SHIFT (0)
++#define PSB_2D_PATPAL_ADDR_CLRMASK (0xF0000007)
++#define PSB_2D_PATPAL_ADDR_MASK (0x0FFFFFF8)
++#define PSB_2D_PATPAL_BYTEALIGN (1024)
+
-+#define PSB_CR_SOFT_RESET 0x0080
-+#define _PSB_CS_RESET_TSP_RESET (1 << 6)
-+#define _PSB_CS_RESET_ISP_RESET (1 << 5)
-+#define _PSB_CS_RESET_USE_RESET (1 << 4)
-+#define _PSB_CS_RESET_TA_RESET (1 << 3)
-+#define _PSB_CS_RESET_DPM_RESET (1 << 2)
-+#define _PSB_CS_RESET_TWOD_RESET (1 << 1)
-+#define _PSB_CS_RESET_BIF_RESET (1 << 0)
++/*
++ * Rop3 Codes (2 LS bytes)
++ */
+
-+#define PSB_CR_DESIGNER_REV_FIELD2 0x001C
++#define PSB_2D_ROP3_SRCCOPY (0xCCCC)
++#define PSB_2D_ROP3_PATCOPY (0xF0F0)
++#define PSB_2D_ROP3_WHITENESS (0xFFFF)
++#define PSB_2D_ROP3_BLACKNESS (0x0000)
++#define PSB_2D_ROP3_SRC (0xCC)
++#define PSB_2D_ROP3_PAT (0xF0)
++#define PSB_2D_ROP3_DST (0xAA)
+
-+#define PSB_CR_EVENT_HOST_ENABLE2 0x0110
+
-+#define PSB_CR_EVENT_STATUS2 0x0118
++/*
++ * Sizes.
++ */
+
-+#define PSB_CR_EVENT_HOST_CLEAR2 0x0114
-+#define _PSB_CE2_BIF_REQUESTER_FAULT (1 << 4)
++#define PSB_SCENE_HW_COOKIE_SIZE 16
++#define PSB_TA_MEM_HW_COOKIE_SIZE 16
+
-+#define PSB_CR_EVENT_STATUS 0x012C
++/*
++ * Scene stuff.
++ */
+
-+#define PSB_CR_EVENT_HOST_ENABLE 0x0130
++#define PSB_NUM_HW_SCENES 2
+
-+#define PSB_CR_EVENT_HOST_CLEAR 0x0134
-+#define _PSB_CE_MASTER_INTERRUPT (1 << 31)
-+#define _PSB_CE_TA_DPM_FAULT (1 << 28)
-+#define _PSB_CE_TWOD_COMPLETE (1 << 27)
-+#define _PSB_CE_DPM_OUT_OF_MEMORY_ZLS (1 << 25)
-+#define _PSB_CE_DPM_TA_MEM_FREE (1 << 24)
-+#define _PSB_CE_PIXELBE_END_RENDER (1 << 18)
-+#define _PSB_CE_SW_EVENT (1 << 14)
-+#define _PSB_CE_TA_FINISHED (1 << 13)
-+#define _PSB_CE_TA_TERMINATE (1 << 12)
-+#define _PSB_CE_DPM_REACHED_MEM_THRESH (1 << 3)
-+#define _PSB_CE_DPM_OUT_OF_MEMORY_GBL (1 << 2)
-+#define _PSB_CE_DPM_OUT_OF_MEMORY_MT (1 << 1)
-+#define _PSB_CE_DPM_3D_MEM_FREE (1 << 0)
++/*
++ * Scheduler completion actions.
++ */
+
++#define PSB_RASTER_BLOCK 0
++#define PSB_RASTER 1
++#define PSB_RETURN 2
++#define PSB_TA 3
+
-+#define PSB_USE_OFFSET_MASK 0x0007FFFF
-+#define PSB_USE_OFFSET_SIZE (PSB_USE_OFFSET_MASK + 1)
-+#define PSB_CR_USE_CODE_BASE0 0x0A0C
-+#define PSB_CR_USE_CODE_BASE1 0x0A10
-+#define PSB_CR_USE_CODE_BASE2 0x0A14
-+#define PSB_CR_USE_CODE_BASE3 0x0A18
-+#define PSB_CR_USE_CODE_BASE4 0x0A1C
-+#define PSB_CR_USE_CODE_BASE5 0x0A20
-+#define PSB_CR_USE_CODE_BASE6 0x0A24
-+#define PSB_CR_USE_CODE_BASE7 0x0A28
-+#define PSB_CR_USE_CODE_BASE8 0x0A2C
-+#define PSB_CR_USE_CODE_BASE9 0x0A30
-+#define PSB_CR_USE_CODE_BASE10 0x0A34
-+#define PSB_CR_USE_CODE_BASE11 0x0A38
-+#define PSB_CR_USE_CODE_BASE12 0x0A3C
-+#define PSB_CR_USE_CODE_BASE13 0x0A40
-+#define PSB_CR_USE_CODE_BASE14 0x0A44
-+#define PSB_CR_USE_CODE_BASE15 0x0A48
-+#define PSB_CR_USE_CODE_BASE(_i) (0x0A0C + ((_i) << 2))
-+#define _PSB_CUC_BASE_DM_SHIFT (25)
-+#define _PSB_CUC_BASE_DM_MASK (0x3 << 25)
-+#define _PSB_CUC_BASE_ADDR_SHIFT (0) // 1024-bit aligned address?
-+#define _PSB_CUC_BASE_ADDR_ALIGNSHIFT (7)
-+#define _PSB_CUC_BASE_ADDR_MASK (0x1FFFFFF << 0)
-+#define _PSB_CUC_DM_VERTEX (0)
-+#define _PSB_CUC_DM_PIXEL (1)
-+#define _PSB_CUC_DM_RESERVED (2)
-+#define _PSB_CUC_DM_EDM (3)
+
-+#define PSB_CR_PDS_EXEC_BASE 0x0AB8
-+#define _PSB_CR_PDS_EXEC_BASE_ADDR_SHIFT (20) // 1MB aligned address
-+#define _PSB_CR_PDS_EXEC_BASE_ADDR_ALIGNSHIFT (20)
++#endif
+Index: linux-2.6.28/drivers/gpu/drm/psb/psb_regman.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.28/drivers/gpu/drm/psb/psb_regman.c 2009-02-12 09:14:42.000000000 +0000
+@@ -0,0 +1,175 @@
++/**************************************************************************
++ * Copyright (c) 2007, Intel Corporation.
++ * All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
++ *
++ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
++ * develop this driver.
++ *
++ **************************************************************************/
++/*
++ */
+
-+#define PSB_CR_EVENT_KICKER 0x0AC4
-+#define _PSB_CE_KICKER_ADDRESS_SHIFT (4) // 128-bit aligned address
++#include "drmP.h"
++#include "psb_drv.h"
+
-+#define PSB_CR_EVENT_KICK 0x0AC8
-+#define _PSB_CE_KICK_NOW (1 << 0)
++struct psb_use_reg {
++ struct drm_reg reg;
++ struct drm_psb_private *dev_priv;
++ uint32_t reg_seq;
++ uint32_t base;
++ uint32_t data_master;
++};
+
++struct psb_use_reg_data {
++ uint32_t base;
++ uint32_t size;
++ uint32_t data_master;
++};
+
-+#define PSB_CR_BIF_DIR_LIST_BASE1 0x0C38
++static int psb_use_reg_reusable(const struct drm_reg *reg, const void *data)
++{
++ struct psb_use_reg *use_reg =
++ container_of(reg, struct psb_use_reg, reg);
++ struct psb_use_reg_data *use_data = (struct psb_use_reg_data *)data;
+
-+#define PSB_CR_BIF_CTRL 0x0C00
-+#define _PSB_CB_CTRL_CLEAR_FAULT (1 << 4)
-+#define _PSB_CB_CTRL_INVALDC (1 << 3)
-+#define _PSB_CB_CTRL_FLUSH (1 << 2)
++ return ((use_reg->base <= use_data->base) &&
++ (use_reg->base + PSB_USE_OFFSET_SIZE >
++ use_data->base + use_data->size) &&
++ use_reg->data_master == use_data->data_master);
++}
+
-+#define PSB_CR_BIF_INT_STAT 0x0C04
++static int psb_use_reg_set(struct psb_use_reg *use_reg,
++ const struct psb_use_reg_data *use_data)
++{
++ struct drm_psb_private *dev_priv = use_reg->dev_priv;
+
-+#define PSB_CR_BIF_FAULT 0x0C08
-+#define _PSB_CBI_STAT_PF_N_RW (1 << 14)
-+#define _PSB_CBI_STAT_FAULT_SHIFT (0)
-+#define _PSB_CBI_STAT_FAULT_MASK (0x3FFF << 0)
-+#define _PSB_CBI_STAT_FAULT_CACHE (1 << 1)
-+#define _PSB_CBI_STAT_FAULT_TA (1 << 2)
-+#define _PSB_CBI_STAT_FAULT_VDM (1 << 3)
-+#define _PSB_CBI_STAT_FAULT_2D (1 << 4)
-+#define _PSB_CBI_STAT_FAULT_PBE (1 << 5)
-+#define _PSB_CBI_STAT_FAULT_TSP (1 << 6)
-+#define _PSB_CBI_STAT_FAULT_ISP (1 << 7)
-+#define _PSB_CBI_STAT_FAULT_USSEPDS (1 << 8)
-+#define _PSB_CBI_STAT_FAULT_HOST (1 << 9)
++ if (use_reg->reg.fence == NULL)
++ use_reg->data_master = use_data->data_master;
+
-+#define PSB_CR_BIF_BANK0 0x0C78
++ if (use_reg->reg.fence == NULL &&
++ !psb_use_reg_reusable(&use_reg->reg, (const void *)use_data)) {
+
-+#define PSB_CR_BIF_BANK1 0x0C7C
++ use_reg->base = use_data->base & ~PSB_USE_OFFSET_MASK;
++ use_reg->data_master = use_data->data_master;
+
-+#define PSB_CR_BIF_DIR_LIST_BASE0 0x0C84
++ if (!psb_use_reg_reusable(&use_reg->reg,
++ (const void *)use_data)) {
++ DRM_ERROR("USE base mechanism didn't support "
++ "buffer size or alignment\n");
++ return -EINVAL;
++ }
+
-+#define PSB_CR_BIF_TWOD_REQ_BASE 0x0C88
-+#define PSB_CR_BIF_3D_REQ_BASE 0x0CAC
++ PSB_WSGX32(PSB_ALPL(use_reg->base, _PSB_CUC_BASE_ADDR) |
++ (use_reg->data_master << _PSB_CUC_BASE_DM_SHIFT),
++ PSB_CR_USE_CODE_BASE(use_reg->reg_seq));
++ }
++ return 0;
+
-+#define PSB_CR_2D_SOCIF 0x0E18
-+#define _PSB_C2_SOCIF_FREESPACE_SHIFT (0)
-+#define _PSB_C2_SOCIF_FREESPACE_MASK (0xFF << 0)
-+#define _PSB_C2_SOCIF_EMPTY (0x80 << 0)
++}
+
-+#define PSB_CR_2D_BLIT_STATUS 0x0E04
-+#define _PSB_C2B_STATUS_BUSY (1 << 24)
-+#define _PSB_C2B_STATUS_COMPLETE_SHIFT (0)
-+#define _PSB_C2B_STATUS_COMPLETE_MASK (0xFFFFFF << 0)
++int psb_grab_use_base(struct drm_psb_private *dev_priv,
++ unsigned long base,
++ unsigned long size,
++ unsigned int data_master,
++ uint32_t fence_class,
++ uint32_t fence_type,
++ int no_wait,
++ int interruptible, int *r_reg, uint32_t * r_offset)
++{
++ struct psb_use_reg_data use_data = {
++ .base = base,
++ .size = size,
++ .data_master = data_master
++ };
++ int ret;
+
-+/*
-+ * 2D defs.
-+ */
++ struct drm_reg *reg;
++ struct psb_use_reg *use_reg;
+
-+/*
-+ * 2D Slave Port Data : Block Header's Object Type
-+ */
++ ret = drm_regs_alloc(&dev_priv->use_manager,
++ (const void *)&use_data,
++ fence_class,
++ fence_type, interruptible, no_wait, ®);
++ if (ret)
++ return ret;
+
-+#define PSB_2D_CLIP_BH (0x00000000)
-+#define PSB_2D_PAT_BH (0x10000000)
-+#define PSB_2D_CTRL_BH (0x20000000)
-+#define PSB_2D_SRC_OFF_BH (0x30000000)
-+#define PSB_2D_MASK_OFF_BH (0x40000000)
-+#define PSB_2D_RESERVED1_BH (0x50000000)
-+#define PSB_2D_RESERVED2_BH (0x60000000)
-+#define PSB_2D_FENCE_BH (0x70000000)
-+#define PSB_2D_BLIT_BH (0x80000000)
-+#define PSB_2D_SRC_SURF_BH (0x90000000)
-+#define PSB_2D_DST_SURF_BH (0xA0000000)
-+#define PSB_2D_PAT_SURF_BH (0xB0000000)
-+#define PSB_2D_SRC_PAL_BH (0xC0000000)
-+#define PSB_2D_PAT_PAL_BH (0xD0000000)
-+#define PSB_2D_MASK_SURF_BH (0xE0000000)
-+#define PSB_2D_FLUSH_BH (0xF0000000)
++ use_reg = container_of(reg, struct psb_use_reg, reg);
++ ret = psb_use_reg_set(use_reg, &use_data);
+
-+/*
-+ * Clip Definition block (PSB_2D_CLIP_BH)
-+ */
-+#define PSB_2D_CLIPCOUNT_MAX (1)
-+#define PSB_2D_CLIPCOUNT_MASK (0x00000000)
-+#define PSB_2D_CLIPCOUNT_CLRMASK (0xFFFFFFFF)
-+#define PSB_2D_CLIPCOUNT_SHIFT (0)
-+// clip rectangle min & max
-+#define PSB_2D_CLIP_XMAX_MASK (0x00FFF000)
-+#define PSB_2D_CLIP_XMAX_CLRMASK (0xFF000FFF)
-+#define PSB_2D_CLIP_XMAX_SHIFT (12)
-+#define PSB_2D_CLIP_XMIN_MASK (0x00000FFF)
-+#define PSB_2D_CLIP_XMIN_CLRMASK (0x00FFF000)
-+#define PSB_2D_CLIP_XMIN_SHIFT (0)
-+// clip rectangle offset
-+#define PSB_2D_CLIP_YMAX_MASK (0x00FFF000)
-+#define PSB_2D_CLIP_YMAX_CLRMASK (0xFF000FFF)
-+#define PSB_2D_CLIP_YMAX_SHIFT (12)
-+#define PSB_2D_CLIP_YMIN_MASK (0x00000FFF)
-+#define PSB_2D_CLIP_YMIN_CLRMASK (0x00FFF000)
-+#define PSB_2D_CLIP_YMIN_SHIFT (0)
++ if (ret)
++ return ret;
+
-+/*
-+ * Pattern Control (PSB_2D_PAT_BH)
-+ */
-+#define PSB_2D_PAT_HEIGHT_MASK (0x0000001F)
-+#define PSB_2D_PAT_HEIGHT_SHIFT (0)
-+#define PSB_2D_PAT_WIDTH_MASK (0x000003E0)
-+#define PSB_2D_PAT_WIDTH_SHIFT (5)
-+#define PSB_2D_PAT_YSTART_MASK (0x00007C00)
-+#define PSB_2D_PAT_YSTART_SHIFT (10)
-+#define PSB_2D_PAT_XSTART_MASK (0x000F8000)
-+#define PSB_2D_PAT_XSTART_SHIFT (15)
++ *r_reg = use_reg->reg_seq;
++ *r_offset = base - use_reg->base;
+
-+/*
-+ * 2D Control block (PSB_2D_CTRL_BH)
-+ */
-+// Present Flags
-+#define PSB_2D_SRCCK_CTRL (0x00000001)
-+#define PSB_2D_DSTCK_CTRL (0x00000002)
-+#define PSB_2D_ALPHA_CTRL (0x00000004)
-+// Colour Key Colour (SRC/DST)
-+#define PSB_2D_CK_COL_MASK (0xFFFFFFFF)
-+#define PSB_2D_CK_COL_CLRMASK (0x00000000)
-+#define PSB_2D_CK_COL_SHIFT (0)
-+// Colour Key Mask (SRC/DST)
-+#define PSB_2D_CK_MASK_MASK (0xFFFFFFFF)
-+#define PSB_2D_CK_MASK_CLRMASK (0x00000000)
-+#define PSB_2D_CK_MASK_SHIFT (0)
-+// Alpha Control (Alpha/RGB)
-+#define PSB_2D_GBLALPHA_MASK (0x000FF000)
-+#define PSB_2D_GBLALPHA_CLRMASK (0xFFF00FFF)
-+#define PSB_2D_GBLALPHA_SHIFT (12)
-+#define PSB_2D_SRCALPHA_OP_MASK (0x00700000)
-+#define PSB_2D_SRCALPHA_OP_CLRMASK (0xFF8FFFFF)
-+#define PSB_2D_SRCALPHA_OP_SHIFT (20)
-+#define PSB_2D_SRCALPHA_OP_ONE (0x00000000)
-+#define PSB_2D_SRCALPHA_OP_SRC (0x00100000)
-+#define PSB_2D_SRCALPHA_OP_DST (0x00200000)
-+#define PSB_2D_SRCALPHA_OP_SG (0x00300000)
-+#define PSB_2D_SRCALPHA_OP_DG (0x00400000)
-+#define PSB_2D_SRCALPHA_OP_GBL (0x00500000)
-+#define PSB_2D_SRCALPHA_OP_ZERO (0x00600000)
-+#define PSB_2D_SRCALPHA_INVERT (0x00800000)
-+#define PSB_2D_SRCALPHA_INVERT_CLR (0xFF7FFFFF)
-+#define PSB_2D_DSTALPHA_OP_MASK (0x07000000)
-+#define PSB_2D_DSTALPHA_OP_CLRMASK (0xF8FFFFFF)
-+#define PSB_2D_DSTALPHA_OP_SHIFT (24)
-+#define PSB_2D_DSTALPHA_OP_ONE (0x00000000)
-+#define PSB_2D_DSTALPHA_OP_SRC (0x01000000)
-+#define PSB_2D_DSTALPHA_OP_DST (0x02000000)
-+#define PSB_2D_DSTALPHA_OP_SG (0x03000000)
-+#define PSB_2D_DSTALPHA_OP_DG (0x04000000)
-+#define PSB_2D_DSTALPHA_OP_GBL (0x05000000)
-+#define PSB_2D_DSTALPHA_OP_ZERO (0x06000000)
-+#define PSB_2D_DSTALPHA_INVERT (0x08000000)
-+#define PSB_2D_DSTALPHA_INVERT_CLR (0xF7FFFFFF)
++ return 0;
++};
+
-+#define PSB_2D_PRE_MULTIPLICATION_ENABLE (0x10000000)
-+#define PSB_2D_PRE_MULTIPLICATION_CLRMASK (0xEFFFFFFF)
-+#define PSB_2D_ZERO_SOURCE_ALPHA_ENABLE (0x20000000)
-+#define PSB_2D_ZERO_SOURCE_ALPHA_CLRMASK (0xDFFFFFFF)
++static void psb_use_reg_destroy(struct drm_reg *reg)
++{
++ struct psb_use_reg *use_reg =
++ container_of(reg, struct psb_use_reg, reg);
++ struct drm_psb_private *dev_priv = use_reg->dev_priv;
+
-+/*
-+ *Source Offset (PSB_2D_SRC_OFF_BH)
-+ */
-+#define PSB_2D_SRCOFF_XSTART_MASK ((0x00000FFF) << 12)
-+#define PSB_2D_SRCOFF_XSTART_SHIFT (12)
-+#define PSB_2D_SRCOFF_YSTART_MASK (0x00000FFF)
-+#define PSB_2D_SRCOFF_YSTART_SHIFT (0)
++ PSB_WSGX32(PSB_ALPL(0, _PSB_CUC_BASE_ADDR),
++ PSB_CR_USE_CODE_BASE(use_reg->reg_seq));
+
-+/*
-+ * Mask Offset (PSB_2D_MASK_OFF_BH)
-+ */
-+#define PSB_2D_MASKOFF_XSTART_MASK ((0x00000FFF) << 12)
-+#define PSB_2D_MASKOFF_XSTART_SHIFT (12)
-+#define PSB_2D_MASKOFF_YSTART_MASK (0x00000FFF)
-+#define PSB_2D_MASKOFF_YSTART_SHIFT (0)
++ drm_free(use_reg, sizeof(*use_reg), DRM_MEM_DRIVER);
++}
+
-+/*
-+ * 2D Fence (see PSB_2D_FENCE_BH): bits 0:27 are ignored
-+ */
++int psb_init_use_base(struct drm_psb_private *dev_priv,
++ unsigned int reg_start, unsigned int reg_num)
++{
++ struct psb_use_reg *use_reg;
++ int i;
++ int ret = 0;
+
-+/*
-+ *Blit Rectangle (PSB_2D_BLIT_BH)
-+ */
++ mutex_lock(&dev_priv->cmdbuf_mutex);
+
-+#define PSB_2D_ROT_MASK (3<<25)
-+#define PSB_2D_ROT_CLRMASK (~PSB_2D_ROT_MASK)
-+#define PSB_2D_ROT_NONE (0<<25)
-+#define PSB_2D_ROT_90DEGS (1<<25)
-+#define PSB_2D_ROT_180DEGS (2<<25)
-+#define PSB_2D_ROT_270DEGS (3<<25)
++ drm_regs_init(&dev_priv->use_manager,
++ &psb_use_reg_reusable, &psb_use_reg_destroy);
+
-+#define PSB_2D_COPYORDER_MASK (3<<23)
-+#define PSB_2D_COPYORDER_CLRMASK (~PSB_2D_COPYORDER_MASK)
-+#define PSB_2D_COPYORDER_TL2BR (0<<23)
-+#define PSB_2D_COPYORDER_BR2TL (1<<23)
-+#define PSB_2D_COPYORDER_TR2BL (2<<23)
-+#define PSB_2D_COPYORDER_BL2TR (3<<23)
++ for (i = reg_start; i < reg_start + reg_num; ++i) {
++ use_reg = drm_calloc(1, sizeof(*use_reg), DRM_MEM_DRIVER);
++ if (!use_reg) {
++ ret = -ENOMEM;
++ goto out;
++ }
+
-+#define PSB_2D_DSTCK_CLRMASK (0xFF9FFFFF)
-+#define PSB_2D_DSTCK_DISABLE (0x00000000)
-+#define PSB_2D_DSTCK_PASS (0x00200000)
-+#define PSB_2D_DSTCK_REJECT (0x00400000)
++ use_reg->dev_priv = dev_priv;
++ use_reg->reg_seq = i;
++ use_reg->base = 0;
++ use_reg->data_master = _PSB_CUC_DM_PIXEL;
+
-+#define PSB_2D_SRCCK_CLRMASK (0xFFE7FFFF)
-+#define PSB_2D_SRCCK_DISABLE (0x00000000)
-+#define PSB_2D_SRCCK_PASS (0x00080000)
-+#define PSB_2D_SRCCK_REJECT (0x00100000)
++ PSB_WSGX32(PSB_ALPL(use_reg->base, _PSB_CUC_BASE_ADDR) |
++ (use_reg->data_master << _PSB_CUC_BASE_DM_SHIFT),
++ PSB_CR_USE_CODE_BASE(use_reg->reg_seq));
+
-+#define PSB_2D_CLIP_ENABLE (0x00040000)
++ drm_regs_add(&dev_priv->use_manager, &use_reg->reg);
++ }
++ out:
++ mutex_unlock(&dev_priv->cmdbuf_mutex);
+
-+#define PSB_2D_ALPHA_ENABLE (0x00020000)
++ return ret;
+
-+#define PSB_2D_PAT_CLRMASK (0xFFFEFFFF)
-+#define PSB_2D_PAT_MASK (0x00010000)
-+#define PSB_2D_USE_PAT (0x00010000)
-+#define PSB_2D_USE_FILL (0x00000000)
++}
++
++void psb_takedown_use_base(struct drm_psb_private *dev_priv)
++{
++ mutex_lock(&dev_priv->cmdbuf_mutex);
++ drm_regs_free(&dev_priv->use_manager);
++ mutex_unlock(&dev_priv->cmdbuf_mutex);
++}
+Index: linux-2.6.28/drivers/gpu/drm/psb/psb_reset.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.28/drivers/gpu/drm/psb/psb_reset.c 2009-02-12 09:14:42.000000000 +0000
+@@ -0,0 +1,374 @@
++/**************************************************************************
++ * Copyright (c) 2007, Intel Corporation.
++ * All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
++ *
++ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
++ * develop this driver.
++ *
++ **************************************************************************/
+/*
-+ * Tungsten Graphics note on rop codes: If rop A and rop B are
-+ * identical, the mask surface will not be read and need not be
-+ * set up.
++ * Authors:
++ * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
+ */
+
-+#define PSB_2D_ROP3B_MASK (0x0000FF00)
-+#define PSB_2D_ROP3B_CLRMASK (0xFFFF00FF)
-+#define PSB_2D_ROP3B_SHIFT (8)
-+// rop code A
-+#define PSB_2D_ROP3A_MASK (0x000000FF)
-+#define PSB_2D_ROP3A_CLRMASK (0xFFFFFF00)
-+#define PSB_2D_ROP3A_SHIFT (0)
++#include "drmP.h"
++#include "psb_drv.h"
++#include "psb_reg.h"
++#include "psb_scene.h"
++#include "psb_msvdx.h"
+
-+#define PSB_2D_ROP4_MASK (0x0000FFFF)
-+/*
-+ * DWORD0: (Only pass if Pattern control == Use Fill Colour)
-+ * Fill Colour RGBA8888
-+ */
-+#define PSB_2D_FILLCOLOUR_MASK (0xFFFFFFFF)
-+#define PSB_2D_FILLCOLOUR_SHIFT (0)
-+/*
-+ * DWORD1: (Always Present)
-+ * X Start (Dest)
-+ * Y Start (Dest)
-+ */
-+#define PSB_2D_DST_XSTART_MASK (0x00FFF000)
-+#define PSB_2D_DST_XSTART_CLRMASK (0xFF000FFF)
-+#define PSB_2D_DST_XSTART_SHIFT (12)
-+#define PSB_2D_DST_YSTART_MASK (0x00000FFF)
-+#define PSB_2D_DST_YSTART_CLRMASK (0xFFFFF000)
-+#define PSB_2D_DST_YSTART_SHIFT (0)
-+/*
-+ * DWORD2: (Always Present)
-+ * X Size (Dest)
-+ * Y Size (Dest)
-+ */
-+#define PSB_2D_DST_XSIZE_MASK (0x00FFF000)
-+#define PSB_2D_DST_XSIZE_CLRMASK (0xFF000FFF)
-+#define PSB_2D_DST_XSIZE_SHIFT (12)
-+#define PSB_2D_DST_YSIZE_MASK (0x00000FFF)
-+#define PSB_2D_DST_YSIZE_CLRMASK (0xFFFFF000)
-+#define PSB_2D_DST_YSIZE_SHIFT (0)
++#define PSB_2D_TIMEOUT_MSEC 100
+
-+/*
-+ * Source Surface (PSB_2D_SRC_SURF_BH)
-+ */
-+/*
-+ * WORD 0
-+ */
-+
-+#define PSB_2D_SRC_FORMAT_MASK (0x00078000)
-+#define PSB_2D_SRC_1_PAL (0x00000000)
-+#define PSB_2D_SRC_2_PAL (0x00008000)
-+#define PSB_2D_SRC_4_PAL (0x00010000)
-+#define PSB_2D_SRC_8_PAL (0x00018000)
-+#define PSB_2D_SRC_8_ALPHA (0x00020000)
-+#define PSB_2D_SRC_4_ALPHA (0x00028000)
-+#define PSB_2D_SRC_332RGB (0x00030000)
-+#define PSB_2D_SRC_4444ARGB (0x00038000)
-+#define PSB_2D_SRC_555RGB (0x00040000)
-+#define PSB_2D_SRC_1555ARGB (0x00048000)
-+#define PSB_2D_SRC_565RGB (0x00050000)
-+#define PSB_2D_SRC_0888ARGB (0x00058000)
-+#define PSB_2D_SRC_8888ARGB (0x00060000)
-+#define PSB_2D_SRC_8888UYVY (0x00068000)
-+#define PSB_2D_SRC_RESERVED (0x00070000)
-+#define PSB_2D_SRC_1555ARGB_LOOKUP (0x00078000)
-+
-+
-+#define PSB_2D_SRC_STRIDE_MASK (0x00007FFF)
-+#define PSB_2D_SRC_STRIDE_CLRMASK (0xFFFF8000)
-+#define PSB_2D_SRC_STRIDE_SHIFT (0)
-+/*
-+ * WORD 1 - Base Address
-+ */
-+#define PSB_2D_SRC_ADDR_MASK (0x0FFFFFFC)
-+#define PSB_2D_SRC_ADDR_CLRMASK (0x00000003)
-+#define PSB_2D_SRC_ADDR_SHIFT (2)
-+#define PSB_2D_SRC_ADDR_ALIGNSHIFT (2)
-+
-+/*
-+ * Pattern Surface (PSB_2D_PAT_SURF_BH)
-+ */
-+/*
-+ * WORD 0
-+ */
-+
-+#define PSB_2D_PAT_FORMAT_MASK (0x00078000)
-+#define PSB_2D_PAT_1_PAL (0x00000000)
-+#define PSB_2D_PAT_2_PAL (0x00008000)
-+#define PSB_2D_PAT_4_PAL (0x00010000)
-+#define PSB_2D_PAT_8_PAL (0x00018000)
-+#define PSB_2D_PAT_8_ALPHA (0x00020000)
-+#define PSB_2D_PAT_4_ALPHA (0x00028000)
-+#define PSB_2D_PAT_332RGB (0x00030000)
-+#define PSB_2D_PAT_4444ARGB (0x00038000)
-+#define PSB_2D_PAT_555RGB (0x00040000)
-+#define PSB_2D_PAT_1555ARGB (0x00048000)
-+#define PSB_2D_PAT_565RGB (0x00050000)
-+#define PSB_2D_PAT_0888ARGB (0x00058000)
-+#define PSB_2D_PAT_8888ARGB (0x00060000)
++void psb_reset(struct drm_psb_private *dev_priv, int reset_2d)
++{
++ uint32_t val;
+
-+#define PSB_2D_PAT_STRIDE_MASK (0x00007FFF)
-+#define PSB_2D_PAT_STRIDE_CLRMASK (0xFFFF8000)
-+#define PSB_2D_PAT_STRIDE_SHIFT (0)
-+/*
-+ * WORD 1 - Base Address
-+ */
-+#define PSB_2D_PAT_ADDR_MASK (0x0FFFFFFC)
-+#define PSB_2D_PAT_ADDR_CLRMASK (0x00000003)
-+#define PSB_2D_PAT_ADDR_SHIFT (2)
-+#define PSB_2D_PAT_ADDR_ALIGNSHIFT (2)
++ val = _PSB_CS_RESET_BIF_RESET |
++ _PSB_CS_RESET_DPM_RESET |
++ _PSB_CS_RESET_TA_RESET |
++ _PSB_CS_RESET_USE_RESET |
++ _PSB_CS_RESET_ISP_RESET | _PSB_CS_RESET_TSP_RESET;
+
-+/*
-+ * Destination Surface (PSB_2D_DST_SURF_BH)
-+ */
-+/*
-+ * WORD 0
-+ */
++ if (reset_2d)
++ val |= _PSB_CS_RESET_TWOD_RESET;
+
-+#define PSB_2D_DST_FORMAT_MASK (0x00078000)
-+#define PSB_2D_DST_332RGB (0x00030000)
-+#define PSB_2D_DST_4444ARGB (0x00038000)
-+#define PSB_2D_DST_555RGB (0x00040000)
-+#define PSB_2D_DST_1555ARGB (0x00048000)
-+#define PSB_2D_DST_565RGB (0x00050000)
-+#define PSB_2D_DST_0888ARGB (0x00058000)
-+#define PSB_2D_DST_8888ARGB (0x00060000)
-+#define PSB_2D_DST_8888AYUV (0x00070000)
++ PSB_WSGX32(val, PSB_CR_SOFT_RESET);
++ (void)PSB_RSGX32(PSB_CR_SOFT_RESET);
+
-+#define PSB_2D_DST_STRIDE_MASK (0x00007FFF)
-+#define PSB_2D_DST_STRIDE_CLRMASK (0xFFFF8000)
-+#define PSB_2D_DST_STRIDE_SHIFT (0)
-+/*
-+ * WORD 1 - Base Address
-+ */
-+#define PSB_2D_DST_ADDR_MASK (0x0FFFFFFC)
-+#define PSB_2D_DST_ADDR_CLRMASK (0x00000003)
-+#define PSB_2D_DST_ADDR_SHIFT (2)
-+#define PSB_2D_DST_ADDR_ALIGNSHIFT (2)
++ msleep(1);
+
-+/*
-+ * Mask Surface (PSB_2D_MASK_SURF_BH)
-+ */
-+/*
-+ * WORD 0
-+ */
-+#define PSB_2D_MASK_STRIDE_MASK (0x00007FFF)
-+#define PSB_2D_MASK_STRIDE_CLRMASK (0xFFFF8000)
-+#define PSB_2D_MASK_STRIDE_SHIFT (0)
-+/*
-+ * WORD 1 - Base Address
-+ */
-+#define PSB_2D_MASK_ADDR_MASK (0x0FFFFFFC)
-+#define PSB_2D_MASK_ADDR_CLRMASK (0x00000003)
-+#define PSB_2D_MASK_ADDR_SHIFT (2)
-+#define PSB_2D_MASK_ADDR_ALIGNSHIFT (2)
++ PSB_WSGX32(0, PSB_CR_SOFT_RESET);
++ wmb();
++ PSB_WSGX32(PSB_RSGX32(PSB_CR_BIF_CTRL) | _PSB_CB_CTRL_CLEAR_FAULT,
++ PSB_CR_BIF_CTRL);
++ wmb();
++ (void)PSB_RSGX32(PSB_CR_BIF_CTRL);
+
-+/*
-+ * Source Palette (PSB_2D_SRC_PAL_BH)
-+ */
++ msleep(1);
++ PSB_WSGX32(PSB_RSGX32(PSB_CR_BIF_CTRL) & ~_PSB_CB_CTRL_CLEAR_FAULT,
++ PSB_CR_BIF_CTRL);
++ (void)PSB_RSGX32(PSB_CR_BIF_CTRL);
++}
+
-+#define PSB_2D_SRCPAL_ADDR_SHIFT (0)
-+#define PSB_2D_SRCPAL_ADDR_CLRMASK (0xF0000007)
-+#define PSB_2D_SRCPAL_ADDR_MASK (0x0FFFFFF8)
-+#define PSB_2D_SRCPAL_BYTEALIGN (1024)
++void psb_print_pagefault(struct drm_psb_private *dev_priv)
++{
++ uint32_t val;
++ uint32_t addr;
+
-+/*
-+ * Pattern Palette (PSB_2D_PAT_PAL_BH)
-+ */
++ val = PSB_RSGX32(PSB_CR_BIF_INT_STAT);
++ addr = PSB_RSGX32(PSB_CR_BIF_FAULT);
+
-+#define PSB_2D_PATPAL_ADDR_SHIFT (0)
-+#define PSB_2D_PATPAL_ADDR_CLRMASK (0xF0000007)
-+#define PSB_2D_PATPAL_ADDR_MASK (0x0FFFFFF8)
-+#define PSB_2D_PATPAL_BYTEALIGN (1024)
++ if (val) {
++ if (val & _PSB_CBI_STAT_PF_N_RW)
++ DRM_ERROR("Poulsbo MMU page fault:\n");
++ else
++ DRM_ERROR("Poulsbo MMU read / write "
++ "protection fault:\n");
+
-+/*
-+ * Rop3 Codes (2 LS bytes)
-+ */
++ if (val & _PSB_CBI_STAT_FAULT_CACHE)
++ DRM_ERROR("\tCache requestor.\n");
++ if (val & _PSB_CBI_STAT_FAULT_TA)
++ DRM_ERROR("\tTA requestor.\n");
++ if (val & _PSB_CBI_STAT_FAULT_VDM)
++ DRM_ERROR("\tVDM requestor.\n");
++ if (val & _PSB_CBI_STAT_FAULT_2D)
++ DRM_ERROR("\t2D requestor.\n");
++ if (val & _PSB_CBI_STAT_FAULT_PBE)
++ DRM_ERROR("\tPBE requestor.\n");
++ if (val & _PSB_CBI_STAT_FAULT_TSP)
++ DRM_ERROR("\tTSP requestor.\n");
++ if (val & _PSB_CBI_STAT_FAULT_ISP)
++ DRM_ERROR("\tISP requestor.\n");
++ if (val & _PSB_CBI_STAT_FAULT_USSEPDS)
++ DRM_ERROR("\tUSSEPDS requestor.\n");
++ if (val & _PSB_CBI_STAT_FAULT_HOST)
++ DRM_ERROR("\tHost requestor.\n");
+
-+#define PSB_2D_ROP3_SRCCOPY (0xCCCC)
-+#define PSB_2D_ROP3_PATCOPY (0xF0F0)
-+#define PSB_2D_ROP3_WHITENESS (0xFFFF)
-+#define PSB_2D_ROP3_BLACKNESS (0x0000)
-+#define PSB_2D_ROP3_SRC (0xCC)
-+#define PSB_2D_ROP3_PAT (0xF0)
-+#define PSB_2D_ROP3_DST (0xAA)
++ DRM_ERROR("\tMMU failing address is 0x%08x.\n", (unsigned)addr);
++ }
++}
+
++void psb_schedule_watchdog(struct drm_psb_private *dev_priv)
++{
++ struct timer_list *wt = &dev_priv->watchdog_timer;
++ unsigned long irq_flags;
+
-+/*
-+ * Sizes.
-+ */
++ spin_lock_irqsave(&dev_priv->watchdog_lock, irq_flags);
++ if (dev_priv->timer_available && !timer_pending(wt)) {
++ wt->expires = jiffies + PSB_WATCHDOG_DELAY;
++ add_timer(wt);
++ }
++ spin_unlock_irqrestore(&dev_priv->watchdog_lock, irq_flags);
++}
+
-+#define PSB_SCENE_HW_COOKIE_SIZE 16
-+#define PSB_TA_MEM_HW_COOKIE_SIZE 16
++#if 0
++static void psb_seq_lockup_idle(struct drm_psb_private *dev_priv,
++ unsigned int engine, int *lockup, int *idle)
++{
++ uint32_t received_seq;
+
-+/*
-+ * Scene stuff.
-+ */
++ received_seq = dev_priv->comm[engine << 4];
++ spin_lock(&dev_priv->sequence_lock);
++ *idle = (received_seq == dev_priv->sequence[engine]);
++ spin_unlock(&dev_priv->sequence_lock);
+
-+#define PSB_NUM_HW_SCENES 2
++ if (*idle) {
++ dev_priv->idle[engine] = 1;
++ *lockup = 0;
++ return;
++ }
+
-+/*
-+ * Scheduler completion actions.
-+ */
++ if (dev_priv->idle[engine]) {
++ dev_priv->idle[engine] = 0;
++ dev_priv->last_sequence[engine] = received_seq;
++ *lockup = 0;
++ return;
++ }
+
-+#define PSB_RASTER_BLOCK 0
-+#define PSB_RASTER 1
-+#define PSB_RETURN 2
-+#define PSB_TA 3
++ *lockup = (dev_priv->last_sequence[engine] == received_seq);
++}
+
++#endif
++static void psb_watchdog_func(unsigned long data)
++{
++ struct drm_psb_private *dev_priv = (struct drm_psb_private *)data;
++ int lockup;
++ int msvdx_lockup;
++ int msvdx_idle;
++ int lockup_2d;
++ int idle_2d;
++ int idle;
++ unsigned long irq_flags;
+
++ psb_scheduler_lockup(dev_priv, &lockup, &idle);
++ psb_msvdx_lockup(dev_priv, &msvdx_lockup, &msvdx_idle);
++#if 0
++ psb_seq_lockup_idle(dev_priv, PSB_ENGINE_2D, &lockup_2d, &idle_2d);
++#else
++ lockup_2d = 0;
++ idle_2d = 1;
+#endif
-Index: linux-2.6.28/drivers/gpu/drm/psb/psb_regman.c
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/psb/psb_regman.c 2009-02-12 09:14:42.000000000 +0000
-@@ -0,0 +1,175 @@
++ if (lockup || msvdx_lockup || lockup_2d) {
++ spin_lock_irqsave(&dev_priv->watchdog_lock, irq_flags);
++ dev_priv->timer_available = 0;
++ spin_unlock_irqrestore(&dev_priv->watchdog_lock, irq_flags);
++ if (lockup) {
++ psb_print_pagefault(dev_priv);
++ schedule_work(&dev_priv->watchdog_wq);
++ }
++ if (msvdx_lockup)
++ schedule_work(&dev_priv->msvdx_watchdog_wq);
++ }
++ if (!idle || !msvdx_idle || !idle_2d)
++ psb_schedule_watchdog(dev_priv);
++}
++
++void psb_msvdx_flush_cmd_queue(struct drm_device *dev)
++{
++ struct drm_psb_private *dev_priv = dev->dev_private;
++ struct psb_msvdx_cmd_queue *msvdx_cmd;
++ struct list_head *list, *next;
++ /*Flush the msvdx cmd queue and signal all fences in the queue */
++ list_for_each_safe(list, next, &dev_priv->msvdx_queue) {
++ msvdx_cmd = list_entry(list, struct psb_msvdx_cmd_queue, head);
++ PSB_DEBUG_GENERAL("MSVDXQUE: flushing sequence:%d\n",
++ msvdx_cmd->sequence);
++ dev_priv->msvdx_current_sequence = msvdx_cmd->sequence;
++ psb_fence_error(dev, PSB_ENGINE_VIDEO,
++ dev_priv->msvdx_current_sequence,
++ DRM_FENCE_TYPE_EXE, DRM_CMD_HANG);
++ list_del(list);
++ kfree(msvdx_cmd->cmd);
++ drm_free(msvdx_cmd, sizeof(struct psb_msvdx_cmd_queue),
++ DRM_MEM_DRIVER);
++ }
++}
++
++static void psb_msvdx_reset_wq(struct work_struct *work)
++{
++ struct drm_psb_private *dev_priv =
++ container_of(work, struct drm_psb_private, msvdx_watchdog_wq);
++
++ struct psb_scheduler *scheduler = &dev_priv->scheduler;
++ unsigned long irq_flags;
++
++ mutex_lock(&dev_priv->msvdx_mutex);
++ dev_priv->msvdx_needs_reset = 1;
++ dev_priv->msvdx_current_sequence++;
++ PSB_DEBUG_GENERAL
++ ("MSVDXFENCE: incremented msvdx_current_sequence to :%d\n",
++ dev_priv->msvdx_current_sequence);
++
++ psb_fence_error(scheduler->dev, PSB_ENGINE_VIDEO,
++ dev_priv->msvdx_current_sequence, DRM_FENCE_TYPE_EXE,
++ DRM_CMD_HANG);
++
++ spin_lock_irqsave(&dev_priv->watchdog_lock, irq_flags);
++ dev_priv->timer_available = 1;
++ spin_unlock_irqrestore(&dev_priv->watchdog_lock, irq_flags);
++
++ spin_lock_irqsave(&dev_priv->msvdx_lock, irq_flags);
++ psb_msvdx_flush_cmd_queue(scheduler->dev);
++ spin_unlock_irqrestore(&dev_priv->msvdx_lock, irq_flags);
++
++ psb_schedule_watchdog(dev_priv);
++ mutex_unlock(&dev_priv->msvdx_mutex);
++}
++
++static int psb_xhw_mmu_reset(struct drm_psb_private *dev_priv)
++{
++ struct psb_xhw_buf buf;
++ uint32_t bif_ctrl;
++
++ INIT_LIST_HEAD(&buf.head);
++ psb_mmu_set_pd_context(psb_mmu_get_default_pd(dev_priv->mmu), 0);
++ bif_ctrl = PSB_RSGX32(PSB_CR_BIF_CTRL);
++ PSB_WSGX32(bif_ctrl |
++ _PSB_CB_CTRL_CLEAR_FAULT |
++ _PSB_CB_CTRL_INVALDC, PSB_CR_BIF_CTRL);
++ (void)PSB_RSGX32(PSB_CR_BIF_CTRL);
++ msleep(1);
++ PSB_WSGX32(bif_ctrl, PSB_CR_BIF_CTRL);
++ (void)PSB_RSGX32(PSB_CR_BIF_CTRL);
++ return psb_xhw_reset_dpm(dev_priv, &buf);
++}
++
++/*
++ * Block command submission and reset hardware and schedulers.
++ */
++
++static void psb_reset_wq(struct work_struct *work)
++{
++ struct drm_psb_private *dev_priv =
++ container_of(work, struct drm_psb_private, watchdog_wq);
++ int lockup_2d;
++ int idle_2d;
++ unsigned long irq_flags;
++ int ret;
++ int reset_count = 0;
++ struct psb_xhw_buf buf;
++ uint32_t xhw_lockup;
++
++ /*
++ * Block command submission.
++ */
++
++ mutex_lock(&dev_priv->reset_mutex);
++
++ INIT_LIST_HEAD(&buf.head);
++ if (psb_xhw_check_lockup(dev_priv, &buf, &xhw_lockup) == 0) {
++ if (xhw_lockup == 0 && psb_extend_raster_timeout(dev_priv) == 0) {
++ /*
++ * no lockup, just re-schedule
++ */
++ spin_lock_irqsave(&dev_priv->watchdog_lock, irq_flags);
++ dev_priv->timer_available = 1;
++ spin_unlock_irqrestore(&dev_priv->watchdog_lock,
++ irq_flags);
++ psb_schedule_watchdog(dev_priv);
++ mutex_unlock(&dev_priv->reset_mutex);
++ return;
++ }
++ }
++#if 0
++ msleep(PSB_2D_TIMEOUT_MSEC);
++
++ psb_seq_lockup_idle(dev_priv, PSB_ENGINE_2D, &lockup_2d, &idle_2d);
++
++ if (lockup_2d) {
++ uint32_t seq_2d;
++ spin_lock(&dev_priv->sequence_lock);
++ seq_2d = dev_priv->sequence[PSB_ENGINE_2D];
++ spin_unlock(&dev_priv->sequence_lock);
++ psb_fence_error(dev_priv->scheduler.dev,
++ PSB_ENGINE_2D,
++ seq_2d, DRM_FENCE_TYPE_EXE, -EBUSY);
++ DRM_INFO("Resetting 2D engine.\n");
++ }
++
++ psb_reset(dev_priv, lockup_2d);
++#else
++ (void)lockup_2d;
++ (void)idle_2d;
++ psb_reset(dev_priv, 0);
++#endif
++ (void)psb_xhw_mmu_reset(dev_priv);
++ DRM_INFO("Resetting scheduler.\n");
++ psb_scheduler_pause(dev_priv);
++ psb_scheduler_reset(dev_priv, -EBUSY);
++ psb_scheduler_ta_mem_check(dev_priv);
++
++ while (dev_priv->ta_mem &&
++ !dev_priv->force_ta_mem_load && ++reset_count < 10) {
++
++ /*
++ * TA memory is currently fenced so offsets
++ * are valid. Reload offsets into the dpm now.
++ */
++
++ struct psb_xhw_buf buf;
++ INIT_LIST_HEAD(&buf.head);
++
++ msleep(100);
++ DRM_INFO("Trying to reload TA memory.\n");
++ ret = psb_xhw_ta_mem_load(dev_priv, &buf,
++ PSB_TA_MEM_FLAG_TA |
++ PSB_TA_MEM_FLAG_RASTER |
++ PSB_TA_MEM_FLAG_HOSTA |
++ PSB_TA_MEM_FLAG_HOSTD |
++ PSB_TA_MEM_FLAG_INIT,
++ dev_priv->ta_mem->ta_memory->offset,
++ dev_priv->ta_mem->hw_data->offset,
++ dev_priv->ta_mem->hw_cookie);
++ if (!ret)
++ break;
++
++ psb_reset(dev_priv, 0);
++ (void)psb_xhw_mmu_reset(dev_priv);
++ }
++
++ psb_scheduler_restart(dev_priv);
++ spin_lock_irqsave(&dev_priv->watchdog_lock, irq_flags);
++ dev_priv->timer_available = 1;
++ spin_unlock_irqrestore(&dev_priv->watchdog_lock, irq_flags);
++ mutex_unlock(&dev_priv->reset_mutex);
++}
++
++void psb_watchdog_init(struct drm_psb_private *dev_priv)
++{
++ struct timer_list *wt = &dev_priv->watchdog_timer;
++ unsigned long irq_flags;
++
++ dev_priv->watchdog_lock = SPIN_LOCK_UNLOCKED;
++ spin_lock_irqsave(&dev_priv->watchdog_lock, irq_flags);
++ init_timer(wt);
++ INIT_WORK(&dev_priv->watchdog_wq, &psb_reset_wq);
++ INIT_WORK(&dev_priv->msvdx_watchdog_wq, &psb_msvdx_reset_wq);
++ wt->data = (unsigned long)dev_priv;
++ wt->function = &psb_watchdog_func;
++ dev_priv->timer_available = 1;
++ spin_unlock_irqrestore(&dev_priv->watchdog_lock, irq_flags);
++}
++
++void psb_watchdog_takedown(struct drm_psb_private *dev_priv)
++{
++ unsigned long irq_flags;
++
++ spin_lock_irqsave(&dev_priv->watchdog_lock, irq_flags);
++ dev_priv->timer_available = 0;
++ spin_unlock_irqrestore(&dev_priv->watchdog_lock, irq_flags);
++ (void)del_timer_sync(&dev_priv->watchdog_timer);
++}
+Index: linux-2.6.28/drivers/gpu/drm/psb/psb_scene.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.28/drivers/gpu/drm/psb/psb_scene.c 2009-02-12 09:14:42.000000000 +0000
+@@ -0,0 +1,531 @@
+/**************************************************************************
+ * Copyright (c) 2007, Intel Corporation.
+ * All Rights Reserved.
+ *
+ **************************************************************************/
+/*
++ * Authors: Thomas Hellstrom <thomas-at-tungstengraphics.com>
+ */
+
+#include "drmP.h"
+#include "psb_drv.h"
++#include "psb_scene.h"
+
-+struct psb_use_reg {
-+ struct drm_reg reg;
-+ struct drm_psb_private *dev_priv;
-+ uint32_t reg_seq;
-+ uint32_t base;
-+ uint32_t data_master;
-+};
-+
-+struct psb_use_reg_data {
-+ uint32_t base;
-+ uint32_t size;
-+ uint32_t data_master;
-+};
-+
-+static int psb_use_reg_reusable(const struct drm_reg *reg, const void *data)
++void psb_clear_scene_atomic(struct psb_scene *scene)
+{
-+ struct psb_use_reg *use_reg =
-+ container_of(reg, struct psb_use_reg, reg);
-+ struct psb_use_reg_data *use_data = (struct psb_use_reg_data *)data;
++ int i;
++ struct page *page;
++ void *v;
+
-+ return ((use_reg->base <= use_data->base) &&
-+ (use_reg->base + PSB_USE_OFFSET_SIZE >
-+ use_data->base + use_data->size) &&
-+ use_reg->data_master == use_data->data_master);
-+}
++ for (i = 0; i < scene->clear_num_pages; ++i) {
++ page = drm_ttm_get_page(scene->hw_data->ttm,
++ scene->clear_p_start + i);
++ if (in_irq())
++ v = kmap_atomic(page, KM_IRQ0);
++ else
++ v = kmap_atomic(page, KM_USER0);
+
-+static int psb_use_reg_set(struct psb_use_reg *use_reg,
-+ const struct psb_use_reg_data *use_data)
-+{
-+ struct drm_psb_private *dev_priv = use_reg->dev_priv;
-+
-+ if (use_reg->reg.fence == NULL)
-+ use_reg->data_master = use_data->data_master;
-+
-+ if (use_reg->reg.fence == NULL &&
-+ !psb_use_reg_reusable(&use_reg->reg, (const void *)use_data)) {
-+
-+ use_reg->base = use_data->base & ~PSB_USE_OFFSET_MASK;
-+ use_reg->data_master = use_data->data_master;
-+
-+ if (!psb_use_reg_reusable(&use_reg->reg,
-+ (const void *)use_data)) {
-+ DRM_ERROR("USE base mechanism didn't support "
-+ "buffer size or alignment\n");
-+ return -EINVAL;
-+ }
++ memset(v, 0, PAGE_SIZE);
+
-+ PSB_WSGX32(PSB_ALPL(use_reg->base, _PSB_CUC_BASE_ADDR) |
-+ (use_reg->data_master << _PSB_CUC_BASE_DM_SHIFT),
-+ PSB_CR_USE_CODE_BASE(use_reg->reg_seq));
++ if (in_irq())
++ kunmap_atomic(v, KM_IRQ0);
++ else
++ kunmap_atomic(v, KM_USER0);
+ }
-+ return 0;
-+
+}
+
-+int psb_grab_use_base(struct drm_psb_private *dev_priv,
-+ unsigned long base,
-+ unsigned long size,
-+ unsigned int data_master,
-+ uint32_t fence_class,
-+ uint32_t fence_type,
-+ int no_wait,
-+ int interruptible, int *r_reg, uint32_t * r_offset)
++int psb_clear_scene(struct psb_scene *scene)
+{
-+ struct psb_use_reg_data use_data = {
-+ .base = base,
-+ .size = size,
-+ .data_master = data_master
-+ };
-+ int ret;
-+
-+ struct drm_reg *reg;
-+ struct psb_use_reg *use_reg;
-+
-+ ret = drm_regs_alloc(&dev_priv->use_manager,
-+ (const void *)&use_data,
-+ fence_class,
-+ fence_type, interruptible, no_wait, ®);
-+ if (ret)
-+ return ret;
++ struct drm_bo_kmap_obj bmo;
++ int is_iomem;
++ void *addr;
+
-+ use_reg = container_of(reg, struct psb_use_reg, reg);
-+ ret = psb_use_reg_set(use_reg, &use_data);
++ int ret = drm_bo_kmap(scene->hw_data, scene->clear_p_start,
++ scene->clear_num_pages, &bmo);
+
++ PSB_DEBUG_RENDER("Scene clear\n");
+ if (ret)
+ return ret;
+
-+ *r_reg = use_reg->reg_seq;
-+ *r_offset = base - use_reg->base;
++ addr = drm_bmo_virtual(&bmo, &is_iomem);
++ BUG_ON(is_iomem);
++ memset(addr, 0, scene->clear_num_pages << PAGE_SHIFT);
++ drm_bo_kunmap(&bmo);
+
+ return 0;
-+};
++}
+
-+static void psb_use_reg_destroy(struct drm_reg *reg)
++static void psb_destroy_scene_devlocked(struct psb_scene *scene)
+{
-+ struct psb_use_reg *use_reg =
-+ container_of(reg, struct psb_use_reg, reg);
-+ struct drm_psb_private *dev_priv = use_reg->dev_priv;
-+
-+ PSB_WSGX32(PSB_ALPL(0, _PSB_CUC_BASE_ADDR),
-+ PSB_CR_USE_CODE_BASE(use_reg->reg_seq));
++ if (!scene)
++ return;
+
-+ drm_free(use_reg, sizeof(*use_reg), DRM_MEM_DRIVER);
++ PSB_DEBUG_RENDER("Scene destroy\n");
++ drm_bo_usage_deref_locked(&scene->hw_data);
++ drm_free(scene, sizeof(*scene), DRM_MEM_DRIVER);
+}
+
-+int psb_init_use_base(struct drm_psb_private *dev_priv,
-+ unsigned int reg_start, unsigned int reg_num)
++void psb_scene_unref_devlocked(struct psb_scene **scene)
+{
-+ struct psb_use_reg *use_reg;
-+ int i;
-+ int ret = 0;
-+
-+ mutex_lock(&dev_priv->cmdbuf_mutex);
-+
-+ drm_regs_init(&dev_priv->use_manager,
-+ &psb_use_reg_reusable, &psb_use_reg_destroy);
-+
-+ for (i = reg_start; i < reg_start + reg_num; ++i) {
-+ use_reg = drm_calloc(1, sizeof(*use_reg), DRM_MEM_DRIVER);
-+ if (!use_reg) {
-+ ret = -ENOMEM;
-+ goto out;
-+ }
-+
-+ use_reg->dev_priv = dev_priv;
-+ use_reg->reg_seq = i;
-+ use_reg->base = 0;
-+ use_reg->data_master = _PSB_CUC_DM_PIXEL;
-+
-+ PSB_WSGX32(PSB_ALPL(use_reg->base, _PSB_CUC_BASE_ADDR) |
-+ (use_reg->data_master << _PSB_CUC_BASE_DM_SHIFT),
-+ PSB_CR_USE_CODE_BASE(use_reg->reg_seq));
++ struct psb_scene *tmp_scene = *scene;
+
-+ drm_regs_add(&dev_priv->use_manager, &use_reg->reg);
++ PSB_DEBUG_RENDER("Scene unref\n");
++ *scene = NULL;
++ if (atomic_dec_and_test(&tmp_scene->ref_count)) {
++ psb_scheduler_remove_scene_refs(tmp_scene);
++ psb_destroy_scene_devlocked(tmp_scene);
+ }
-+ out:
-+ mutex_unlock(&dev_priv->cmdbuf_mutex);
-+
-+ return ret;
-+
+}
+
-+void psb_takedown_use_base(struct drm_psb_private *dev_priv)
++struct psb_scene *psb_scene_ref(struct psb_scene *src)
+{
-+ mutex_lock(&dev_priv->cmdbuf_mutex);
-+ drm_regs_free(&dev_priv->use_manager);
-+ mutex_unlock(&dev_priv->cmdbuf_mutex);
++ PSB_DEBUG_RENDER("Scene ref\n");
++ atomic_inc(&src->ref_count);
++ return src;
+}
-Index: linux-2.6.28/drivers/gpu/drm/psb/psb_reset.c
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/psb/psb_reset.c 2009-02-12 09:14:42.000000000 +0000
-@@ -0,0 +1,374 @@
-+/**************************************************************************
-+ * Copyright (c) 2007, Intel Corporation.
-+ * All Rights Reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms and conditions of the GNU General Public License,
-+ * version 2, as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
-+ *
-+ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
-+ * develop this driver.
-+ *
-+ **************************************************************************/
-+/*
-+ * Authors:
-+ * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
-+ */
+
-+#include "drmP.h"
-+#include "psb_drv.h"
-+#include "psb_reg.h"
-+#include "psb_scene.h"
-+#include "psb_msvdx.h"
-+
-+#define PSB_2D_TIMEOUT_MSEC 100
-+
-+void psb_reset(struct drm_psb_private *dev_priv, int reset_2d)
++static struct psb_scene *psb_alloc_scene(struct drm_device *dev,
++ uint32_t w, uint32_t h)
+{
-+ uint32_t val;
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
++ int ret = -EINVAL;
++ struct psb_scene *scene;
++ uint32_t bo_size;
++ struct psb_xhw_buf buf;
+
-+ val = _PSB_CS_RESET_BIF_RESET |
-+ _PSB_CS_RESET_DPM_RESET |
-+ _PSB_CS_RESET_TA_RESET |
-+ _PSB_CS_RESET_USE_RESET |
-+ _PSB_CS_RESET_ISP_RESET | _PSB_CS_RESET_TSP_RESET;
++ PSB_DEBUG_RENDER("Alloc scene w %u h %u\n", w, h);
+
-+ if (reset_2d)
-+ val |= _PSB_CS_RESET_TWOD_RESET;
++ scene = drm_calloc(1, sizeof(*scene), DRM_MEM_DRIVER);
+
-+ PSB_WSGX32(val, PSB_CR_SOFT_RESET);
-+ (void)PSB_RSGX32(PSB_CR_SOFT_RESET);
++ if (!scene) {
++ DRM_ERROR("Out of memory allocating scene object.\n");
++ return NULL;
++ }
+
-+ msleep(1);
++ scene->dev = dev;
++ scene->w = w;
++ scene->h = h;
++ scene->hw_scene = NULL;
++ atomic_set(&scene->ref_count, 1);
+
-+ PSB_WSGX32(0, PSB_CR_SOFT_RESET);
-+ wmb();
-+ PSB_WSGX32(PSB_RSGX32(PSB_CR_BIF_CTRL) | _PSB_CB_CTRL_CLEAR_FAULT,
-+ PSB_CR_BIF_CTRL);
-+ wmb();
-+ (void)PSB_RSGX32(PSB_CR_BIF_CTRL);
++ INIT_LIST_HEAD(&buf.head);
++ ret = psb_xhw_scene_info(dev_priv, &buf, scene->w, scene->h,
++ scene->hw_cookie, &bo_size,
++ &scene->clear_p_start,
++ &scene->clear_num_pages);
++ if (ret)
++ goto out_err;
+
-+ msleep(1);
-+ PSB_WSGX32(PSB_RSGX32(PSB_CR_BIF_CTRL) & ~_PSB_CB_CTRL_CLEAR_FAULT,
-+ PSB_CR_BIF_CTRL);
-+ (void)PSB_RSGX32(PSB_CR_BIF_CTRL);
++ ret = drm_buffer_object_create(dev, bo_size, drm_bo_type_kernel,
++ DRM_PSB_FLAG_MEM_MMU |
++ DRM_BO_FLAG_READ |
++ DRM_BO_FLAG_CACHED |
++ PSB_BO_FLAG_SCENE |
++ DRM_BO_FLAG_WRITE,
++ DRM_BO_HINT_DONT_FENCE,
++ 0, 0, &scene->hw_data);
++ if (ret)
++ goto out_err;
++
++ return scene;
++ out_err:
++ drm_free(scene, sizeof(*scene), DRM_MEM_DRIVER);
++ return NULL;
+}
+
-+void psb_print_pagefault(struct drm_psb_private *dev_priv)
++int psb_validate_scene_pool(struct psb_scene_pool *pool, uint64_t flags,
++ uint64_t mask,
++ uint32_t hint,
++ uint32_t w,
++ uint32_t h,
++ int final_pass, struct psb_scene **scene_p)
+{
-+ uint32_t val;
-+ uint32_t addr;
++ struct drm_device *dev = pool->dev;
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
++ struct psb_scene *scene = pool->scenes[pool->cur_scene];
++ int ret;
++ unsigned long irq_flags;
++ struct psb_scheduler *scheduler = &dev_priv->scheduler;
++ uint32_t bin_pt_offset;
++ uint32_t bin_param_offset;
+
-+ val = PSB_RSGX32(PSB_CR_BIF_INT_STAT);
-+ addr = PSB_RSGX32(PSB_CR_BIF_FAULT);
++ PSB_DEBUG_RENDER("Validate scene pool. Scene %u\n", pool->cur_scene);
+
-+ if (val) {
-+ if (val & _PSB_CBI_STAT_PF_N_RW)
-+ DRM_ERROR("Poulsbo MMU page fault:\n");
-+ else
-+ DRM_ERROR("Poulsbo MMU read / write "
-+ "protection fault:\n");
++ if (unlikely(!dev_priv->ta_mem)) {
++ dev_priv->ta_mem =
++ psb_alloc_ta_mem(dev, dev_priv->ta_mem_pages);
++ if (!dev_priv->ta_mem)
++ return -ENOMEM;
+
-+ if (val & _PSB_CBI_STAT_FAULT_CACHE)
-+ DRM_ERROR("\tCache requestor.\n");
-+ if (val & _PSB_CBI_STAT_FAULT_TA)
-+ DRM_ERROR("\tTA requestor.\n");
-+ if (val & _PSB_CBI_STAT_FAULT_VDM)
-+ DRM_ERROR("\tVDM requestor.\n");
-+ if (val & _PSB_CBI_STAT_FAULT_2D)
-+ DRM_ERROR("\t2D requestor.\n");
-+ if (val & _PSB_CBI_STAT_FAULT_PBE)
-+ DRM_ERROR("\tPBE requestor.\n");
-+ if (val & _PSB_CBI_STAT_FAULT_TSP)
-+ DRM_ERROR("\tTSP requestor.\n");
-+ if (val & _PSB_CBI_STAT_FAULT_ISP)
-+ DRM_ERROR("\tISP requestor.\n");
-+ if (val & _PSB_CBI_STAT_FAULT_USSEPDS)
-+ DRM_ERROR("\tUSSEPDS requestor.\n");
-+ if (val & _PSB_CBI_STAT_FAULT_HOST)
-+ DRM_ERROR("\tHost requestor.\n");
++ bin_pt_offset = ~0;
++ bin_param_offset = ~0;
++ } else {
++ bin_pt_offset = dev_priv->ta_mem->hw_data->offset;
++ bin_param_offset = dev_priv->ta_mem->ta_memory->offset;
++ }
+
-+ DRM_ERROR("\tMMU failing address is 0x%08x.\n", (unsigned)addr);
++ pool->w = w;
++ pool->h = h;
++ if (scene && (scene->w != pool->w || scene->h != pool->h)) {
++ spin_lock_irqsave(&scheduler->lock, irq_flags);
++ if (scene->flags & PSB_SCENE_FLAG_DIRTY) {
++ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
++ DRM_ERROR("Trying to resize a dirty scene.\n");
++ return -EINVAL;
++ }
++ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
++ mutex_lock(&dev->struct_mutex);
++ psb_scene_unref_devlocked(&pool->scenes[pool->cur_scene]);
++ mutex_unlock(&dev->struct_mutex);
++ scene = NULL;
+ }
-+}
+
-+void psb_schedule_watchdog(struct drm_psb_private *dev_priv)
-+{
-+ struct timer_list *wt = &dev_priv->watchdog_timer;
-+ unsigned long irq_flags;
++ if (!scene) {
++ pool->scenes[pool->cur_scene] = scene =
++ psb_alloc_scene(pool->dev, pool->w, pool->h);
+
-+ spin_lock_irqsave(&dev_priv->watchdog_lock, irq_flags);
-+ if (dev_priv->timer_available && !timer_pending(wt)) {
-+ wt->expires = jiffies + PSB_WATCHDOG_DELAY;
-+ add_timer(wt);
++ if (!scene)
++ return -ENOMEM;
++
++ scene->flags = PSB_SCENE_FLAG_CLEARED;
+ }
-+ spin_unlock_irqrestore(&dev_priv->watchdog_lock, irq_flags);
-+}
+
-+#if 0
-+static void psb_seq_lockup_idle(struct drm_psb_private *dev_priv,
-+ unsigned int engine, int *lockup, int *idle)
-+{
-+ uint32_t received_seq;
++ /*
++ * FIXME: We need atomic bit manipulation here for the
++ * scheduler. For now use the spinlock.
++ */
+
-+ received_seq = dev_priv->comm[engine << 4];
-+ spin_lock(&dev_priv->sequence_lock);
-+ *idle = (received_seq == dev_priv->sequence[engine]);
-+ spin_unlock(&dev_priv->sequence_lock);
++ spin_lock_irqsave(&scheduler->lock, irq_flags);
++ if (!(scene->flags & PSB_SCENE_FLAG_CLEARED)) {
++ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
++ PSB_DEBUG_RENDER("Waiting to clear scene memory.\n");
++ mutex_lock(&scene->hw_data->mutex);
++ ret = drm_bo_wait(scene->hw_data, 0, 0, 0);
++ mutex_unlock(&scene->hw_data->mutex);
++ if (ret)
++ return ret;
+
-+ if (*idle) {
-+ dev_priv->idle[engine] = 1;
-+ *lockup = 0;
-+ return;
++ ret = psb_clear_scene(scene);
++
++ if (ret)
++ return ret;
++ spin_lock_irqsave(&scheduler->lock, irq_flags);
++ scene->flags |= PSB_SCENE_FLAG_CLEARED;
+ }
++ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
+
-+ if (dev_priv->idle[engine]) {
-+ dev_priv->idle[engine] = 0;
-+ dev_priv->last_sequence[engine] = received_seq;
-+ *lockup = 0;
-+ return;
++ ret = drm_bo_do_validate(scene->hw_data, flags, mask, hint,
++ PSB_ENGINE_TA, 0, NULL);
++ if (ret)
++ return ret;
++ ret = drm_bo_do_validate(dev_priv->ta_mem->hw_data, 0, 0, 0,
++ PSB_ENGINE_TA, 0, NULL);
++ if (ret)
++ return ret;
++ ret = drm_bo_do_validate(dev_priv->ta_mem->ta_memory, 0, 0, 0,
++ PSB_ENGINE_TA, 0, NULL);
++ if (ret)
++ return ret;
++
++ if (unlikely(bin_param_offset !=
++ dev_priv->ta_mem->ta_memory->offset ||
++ bin_pt_offset !=
++ dev_priv->ta_mem->hw_data->offset ||
++ dev_priv->force_ta_mem_load)) {
++
++ struct psb_xhw_buf buf;
++
++ INIT_LIST_HEAD(&buf.head);
++ ret = psb_xhw_ta_mem_load(dev_priv, &buf,
++ PSB_TA_MEM_FLAG_TA |
++ PSB_TA_MEM_FLAG_RASTER |
++ PSB_TA_MEM_FLAG_HOSTA |
++ PSB_TA_MEM_FLAG_HOSTD |
++ PSB_TA_MEM_FLAG_INIT,
++ dev_priv->ta_mem->ta_memory->offset,
++ dev_priv->ta_mem->hw_data->offset,
++ dev_priv->ta_mem->hw_cookie);
++ if (ret)
++ return ret;
++
++ dev_priv->force_ta_mem_load = 0;
+ }
+
-+ *lockup = (dev_priv->last_sequence[engine] == received_seq);
-+}
++ if (final_pass) {
+
-+#endif
-+static void psb_watchdog_func(unsigned long data)
-+{
-+ struct drm_psb_private *dev_priv = (struct drm_psb_private *)data;
-+ int lockup;
-+ int msvdx_lockup;
-+ int msvdx_idle;
-+ int lockup_2d;
-+ int idle_2d;
-+ int idle;
-+ unsigned long irq_flags;
++ /*
++ * Clear the scene on next use. Advance the scene counter.
++ */
+
-+ psb_scheduler_lockup(dev_priv, &lockup, &idle);
-+ psb_msvdx_lockup(dev_priv, &msvdx_lockup, &msvdx_idle);
-+#if 0
-+ psb_seq_lockup_idle(dev_priv, PSB_ENGINE_2D, &lockup_2d, &idle_2d);
-+#else
-+ lockup_2d = 0;
-+ idle_2d = 1;
-+#endif
-+ if (lockup || msvdx_lockup || lockup_2d) {
-+ spin_lock_irqsave(&dev_priv->watchdog_lock, irq_flags);
-+ dev_priv->timer_available = 0;
-+ spin_unlock_irqrestore(&dev_priv->watchdog_lock, irq_flags);
-+ if (lockup) {
-+ psb_print_pagefault(dev_priv);
-+ schedule_work(&dev_priv->watchdog_wq);
-+ }
-+ if (msvdx_lockup)
-+ schedule_work(&dev_priv->msvdx_watchdog_wq);
++ spin_lock_irqsave(&scheduler->lock, irq_flags);
++ scene->flags &= ~PSB_SCENE_FLAG_CLEARED;
++ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
++ pool->cur_scene = (pool->cur_scene + 1) % pool->num_scenes;
+ }
-+ if (!idle || !msvdx_idle || !idle_2d)
-+ psb_schedule_watchdog(dev_priv);
++
++ *scene_p = psb_scene_ref(scene);
++ return 0;
+}
+
-+void psb_msvdx_flush_cmd_queue(struct drm_device *dev)
++static void psb_scene_pool_destroy_devlocked(struct psb_scene_pool *pool)
+{
-+ struct drm_psb_private *dev_priv = dev->dev_private;
-+ struct psb_msvdx_cmd_queue *msvdx_cmd;
-+ struct list_head *list, *next;
-+ /*Flush the msvdx cmd queue and signal all fences in the queue */
-+ list_for_each_safe(list, next, &dev_priv->msvdx_queue) {
-+ msvdx_cmd = list_entry(list, struct psb_msvdx_cmd_queue, head);
-+ PSB_DEBUG_GENERAL("MSVDXQUE: flushing sequence:%d\n",
-+ msvdx_cmd->sequence);
-+ dev_priv->msvdx_current_sequence = msvdx_cmd->sequence;
-+ psb_fence_error(dev, PSB_ENGINE_VIDEO,
-+ dev_priv->msvdx_current_sequence,
-+ DRM_FENCE_TYPE_EXE, DRM_CMD_HANG);
-+ list_del(list);
-+ kfree(msvdx_cmd->cmd);
-+ drm_free(msvdx_cmd, sizeof(struct psb_msvdx_cmd_queue),
-+ DRM_MEM_DRIVER);
++ int i;
++
++ if (!pool)
++ return;
++
++ PSB_DEBUG_RENDER("Scene pool destroy.\n");
++ for (i = 0; i < pool->num_scenes; ++i) {
++ PSB_DEBUG_RENDER("scenes %d is 0x%08lx\n", i,
++ (unsigned long)pool->scenes[i]);
++ if (pool->scenes[i])
++ psb_scene_unref_devlocked(&pool->scenes[i]);
+ }
++ drm_free(pool, sizeof(*pool), DRM_MEM_DRIVER);
+}
+
-+static void psb_msvdx_reset_wq(struct work_struct *work)
++void psb_scene_pool_unref_devlocked(struct psb_scene_pool **pool)
+{
-+ struct drm_psb_private *dev_priv =
-+ container_of(work, struct drm_psb_private, msvdx_watchdog_wq);
++ struct psb_scene_pool *tmp_pool = *pool;
++ struct drm_device *dev = tmp_pool->dev;
+
-+ struct psb_scheduler *scheduler = &dev_priv->scheduler;
-+ unsigned long irq_flags;
++ PSB_DEBUG_RENDER("Scene pool unref\n");
++ (void)dev;
++ DRM_ASSERT_LOCKED(&dev->struct_mutex);
++ *pool = NULL;
++ if (--tmp_pool->ref_count == 0)
++ psb_scene_pool_destroy_devlocked(tmp_pool);
++}
+
-+ mutex_lock(&dev_priv->msvdx_mutex);
-+ dev_priv->msvdx_needs_reset = 1;
-+ dev_priv->msvdx_current_sequence++;
-+ PSB_DEBUG_GENERAL
-+ ("MSVDXFENCE: incremented msvdx_current_sequence to :%d\n",
-+ dev_priv->msvdx_current_sequence);
++struct psb_scene_pool *psb_scene_pool_ref_devlocked(struct psb_scene_pool *src)
++{
++ ++src->ref_count;
++ return src;
++}
+
-+ psb_fence_error(scheduler->dev, PSB_ENGINE_VIDEO,
-+ dev_priv->msvdx_current_sequence, DRM_FENCE_TYPE_EXE,
-+ DRM_CMD_HANG);
++/*
++ * Callback for user object manager.
++ */
+
-+ spin_lock_irqsave(&dev_priv->watchdog_lock, irq_flags);
-+ dev_priv->timer_available = 1;
-+ spin_unlock_irqrestore(&dev_priv->watchdog_lock, irq_flags);
++static void psb_scene_pool_destroy(struct drm_file *priv,
++ struct drm_user_object *base)
++{
++ struct psb_scene_pool *pool =
++ drm_user_object_entry(base, struct psb_scene_pool, user);
+
-+ spin_lock_irqsave(&dev_priv->msvdx_lock, irq_flags);
-+ psb_msvdx_flush_cmd_queue(scheduler->dev);
-+ spin_unlock_irqrestore(&dev_priv->msvdx_lock, irq_flags);
++ psb_scene_pool_unref_devlocked(&pool);
++}
+
-+ psb_schedule_watchdog(dev_priv);
-+ mutex_unlock(&dev_priv->msvdx_mutex);
++struct psb_scene_pool *psb_scene_pool_lookup_devlocked(struct drm_file *priv,
++ uint32_t handle,
++ int check_owner)
++{
++ struct drm_user_object *uo;
++ struct psb_scene_pool *pool;
++
++ uo = drm_lookup_user_object(priv, handle);
++ if (!uo || (uo->type != PSB_USER_OBJECT_SCENE_POOL)) {
++ DRM_ERROR("Could not find scene pool object 0x%08x\n", handle);
++ return NULL;
++ }
++
++ if (check_owner && priv != uo->owner) {
++ if (!drm_lookup_ref_object(priv, uo, _DRM_REF_USE))
++ return NULL;
++ }
++
++ pool = drm_user_object_entry(uo, struct psb_scene_pool, user);
++ return psb_scene_pool_ref_devlocked(pool);
+}
+
-+static int psb_xhw_mmu_reset(struct drm_psb_private *dev_priv)
++struct psb_scene_pool *psb_scene_pool_alloc(struct drm_file *priv,
++ int shareable,
++ uint32_t num_scenes,
++ uint32_t w, uint32_t h)
+{
-+ struct psb_xhw_buf buf;
-+ uint32_t bif_ctrl;
++ struct drm_device *dev = priv->minor->dev;
++ struct psb_scene_pool *pool;
++ int ret;
+
-+ INIT_LIST_HEAD(&buf.head);
-+ psb_mmu_set_pd_context(psb_mmu_get_default_pd(dev_priv->mmu), 0);
-+ bif_ctrl = PSB_RSGX32(PSB_CR_BIF_CTRL);
-+ PSB_WSGX32(bif_ctrl |
-+ _PSB_CB_CTRL_CLEAR_FAULT |
-+ _PSB_CB_CTRL_INVALDC, PSB_CR_BIF_CTRL);
-+ (void)PSB_RSGX32(PSB_CR_BIF_CTRL);
-+ msleep(1);
-+ PSB_WSGX32(bif_ctrl, PSB_CR_BIF_CTRL);
-+ (void)PSB_RSGX32(PSB_CR_BIF_CTRL);
-+ return psb_xhw_reset_dpm(dev_priv, &buf);
++ PSB_DEBUG_RENDER("Scene pool alloc\n");
++ pool = drm_calloc(1, sizeof(*pool), DRM_MEM_DRIVER);
++ if (!pool) {
++ DRM_ERROR("Out of memory allocating scene pool object.\n");
++ return NULL;
++ }
++ pool->w = w;
++ pool->h = h;
++ pool->dev = dev;
++ pool->num_scenes = num_scenes;
++
++ mutex_lock(&dev->struct_mutex);
++ ret = drm_add_user_object(priv, &pool->user, shareable);
++ if (ret)
++ goto out_err;
++
++ pool->user.type = PSB_USER_OBJECT_SCENE_POOL;
++ pool->user.remove = &psb_scene_pool_destroy;
++ pool->ref_count = 2;
++ mutex_unlock(&dev->struct_mutex);
++ return pool;
++ out_err:
++ drm_free(pool, sizeof(*pool), DRM_MEM_DRIVER);
++ return NULL;
+}
+
+/*
-+ * Block command submission and reset hardware and schedulers.
++ * Code to support multiple ta memory buffers.
+ */
+
-+static void psb_reset_wq(struct work_struct *work)
++static void psb_destroy_ta_mem_devlocked(struct psb_ta_mem *ta_mem)
+{
-+ struct drm_psb_private *dev_priv =
-+ container_of(work, struct drm_psb_private, watchdog_wq);
-+ int lockup_2d;
-+ int idle_2d;
-+ unsigned long irq_flags;
-+ int ret;
-+ int reset_count = 0;
-+ struct psb_xhw_buf buf;
-+ uint32_t xhw_lockup;
-+
-+ /*
-+ * Block command submission.
-+ */
++ if (!ta_mem)
++ return;
+
-+ mutex_lock(&dev_priv->reset_mutex);
++ drm_bo_usage_deref_locked(&ta_mem->hw_data);
++ drm_bo_usage_deref_locked(&ta_mem->ta_memory);
++ drm_free(ta_mem, sizeof(*ta_mem), DRM_MEM_DRIVER);
++}
+
-+ INIT_LIST_HEAD(&buf.head);
-+ if (psb_xhw_check_lockup(dev_priv, &buf, &xhw_lockup) == 0) {
-+ if (xhw_lockup == 0 && psb_extend_raster_timeout(dev_priv) == 0) {
-+ /*
-+ * no lockup, just re-schedule
-+ */
-+ spin_lock_irqsave(&dev_priv->watchdog_lock, irq_flags);
-+ dev_priv->timer_available = 1;
-+ spin_unlock_irqrestore(&dev_priv->watchdog_lock,
-+ irq_flags);
-+ psb_schedule_watchdog(dev_priv);
-+ mutex_unlock(&dev_priv->reset_mutex);
-+ return;
-+ }
-+ }
-+#if 0
-+ msleep(PSB_2D_TIMEOUT_MSEC);
++void psb_ta_mem_unref_devlocked(struct psb_ta_mem **ta_mem)
++{
++ struct psb_ta_mem *tmp_ta_mem = *ta_mem;
++ struct drm_device *dev = tmp_ta_mem->dev;
+
-+ psb_seq_lockup_idle(dev_priv, PSB_ENGINE_2D, &lockup_2d, &idle_2d);
++ (void)dev;
++ DRM_ASSERT_LOCKED(&dev->struct_mutex);
++ *ta_mem = NULL;
++ if (--tmp_ta_mem->ref_count == 0)
++ psb_destroy_ta_mem_devlocked(tmp_ta_mem);
++}
+
-+ if (lockup_2d) {
-+ uint32_t seq_2d;
-+ spin_lock(&dev_priv->sequence_lock);
-+ seq_2d = dev_priv->sequence[PSB_ENGINE_2D];
-+ spin_unlock(&dev_priv->sequence_lock);
-+ psb_fence_error(dev_priv->scheduler.dev,
-+ PSB_ENGINE_2D,
-+ seq_2d, DRM_FENCE_TYPE_EXE, -EBUSY);
-+ DRM_INFO("Resetting 2D engine.\n");
-+ }
++void psb_ta_mem_ref_devlocked(struct psb_ta_mem **dst, struct psb_ta_mem *src)
++{
++ struct drm_device *dev = src->dev;
+
-+ psb_reset(dev_priv, lockup_2d);
-+#else
-+ (void)lockup_2d;
-+ (void)idle_2d;
-+ psb_reset(dev_priv, 0);
-+#endif
-+ (void)psb_xhw_mmu_reset(dev_priv);
-+ DRM_INFO("Resetting scheduler.\n");
-+ psb_scheduler_pause(dev_priv);
-+ psb_scheduler_reset(dev_priv, -EBUSY);
-+ psb_scheduler_ta_mem_check(dev_priv);
++ (void)dev;
++ DRM_ASSERT_LOCKED(&dev->struct_mutex);
++ *dst = src;
++ ++src->ref_count;
++}
+
-+ while (dev_priv->ta_mem &&
-+ !dev_priv->force_ta_mem_load && ++reset_count < 10) {
++struct psb_ta_mem *psb_alloc_ta_mem(struct drm_device *dev, uint32_t pages)
++{
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
++ int ret = -EINVAL;
++ struct psb_ta_mem *ta_mem;
++ uint32_t bo_size;
++ struct psb_xhw_buf buf;
+
-+ /*
-+ * TA memory is currently fenced so offsets
-+ * are valid. Reload offsets into the dpm now.
-+ */
++ INIT_LIST_HEAD(&buf.head);
+
-+ struct psb_xhw_buf buf;
-+ INIT_LIST_HEAD(&buf.head);
++ ta_mem = drm_calloc(1, sizeof(*ta_mem), DRM_MEM_DRIVER);
+
-+ msleep(100);
-+ DRM_INFO("Trying to reload TA memory.\n");
-+ ret = psb_xhw_ta_mem_load(dev_priv, &buf,
-+ PSB_TA_MEM_FLAG_TA |
-+ PSB_TA_MEM_FLAG_RASTER |
-+ PSB_TA_MEM_FLAG_HOSTA |
-+ PSB_TA_MEM_FLAG_HOSTD |
-+ PSB_TA_MEM_FLAG_INIT,
-+ dev_priv->ta_mem->ta_memory->offset,
-+ dev_priv->ta_mem->hw_data->offset,
-+ dev_priv->ta_mem->hw_cookie);
-+ if (!ret)
-+ break;
++ if (!ta_mem) {
++ DRM_ERROR("Out of memory allocating parameter memory.\n");
++ return NULL;
++ }
+
-+ psb_reset(dev_priv, 0);
-+ (void)psb_xhw_mmu_reset(dev_priv);
++ ret = psb_xhw_ta_mem_info(dev_priv, &buf, pages,
++ ta_mem->hw_cookie, &bo_size);
++ if (ret == -ENOMEM) {
++ DRM_ERROR("Parameter memory size is too small.\n");
++ DRM_INFO("Attempted to use %u kiB of parameter memory.\n",
++ (unsigned int)(pages * (PAGE_SIZE / 1024)));
++ DRM_INFO("The Xpsb driver thinks this is too small and\n");
++ DRM_INFO("suggests %u kiB. Check the psb DRM\n",
++ (unsigned int)(bo_size / 1024));
++ DRM_INFO("\"ta_mem_size\" parameter!\n");
+ }
++ if (ret)
++ goto out_err0;
+
-+ psb_scheduler_restart(dev_priv);
-+ spin_lock_irqsave(&dev_priv->watchdog_lock, irq_flags);
-+ dev_priv->timer_available = 1;
-+ spin_unlock_irqrestore(&dev_priv->watchdog_lock, irq_flags);
-+ mutex_unlock(&dev_priv->reset_mutex);
-+}
++ bo_size = pages * PAGE_SIZE;
++ ta_mem->dev = dev;
++ ret = drm_buffer_object_create(dev, bo_size, drm_bo_type_kernel,
++ DRM_PSB_FLAG_MEM_MMU | DRM_BO_FLAG_READ |
++ DRM_BO_FLAG_WRITE |
++ PSB_BO_FLAG_SCENE,
++ DRM_BO_HINT_DONT_FENCE, 0, 0,
++ &ta_mem->hw_data);
++ if (ret)
++ goto out_err0;
+
-+void psb_watchdog_init(struct drm_psb_private *dev_priv)
-+{
-+ struct timer_list *wt = &dev_priv->watchdog_timer;
-+ unsigned long irq_flags;
++ ret =
++ drm_buffer_object_create(dev, pages << PAGE_SHIFT,
++ drm_bo_type_kernel,
++ DRM_PSB_FLAG_MEM_RASTGEOM |
++ DRM_BO_FLAG_READ |
++ DRM_BO_FLAG_WRITE |
++ PSB_BO_FLAG_SCENE,
++ DRM_BO_HINT_DONT_FENCE, 0,
++ 1024 * 1024 >> PAGE_SHIFT,
++ &ta_mem->ta_memory);
++ if (ret)
++ goto out_err1;
+
-+ dev_priv->watchdog_lock = SPIN_LOCK_UNLOCKED;
-+ spin_lock_irqsave(&dev_priv->watchdog_lock, irq_flags);
-+ init_timer(wt);
-+ INIT_WORK(&dev_priv->watchdog_wq, &psb_reset_wq);
-+ INIT_WORK(&dev_priv->msvdx_watchdog_wq, &psb_msvdx_reset_wq);
-+ wt->data = (unsigned long)dev_priv;
-+ wt->function = &psb_watchdog_func;
-+ dev_priv->timer_available = 1;
-+ spin_unlock_irqrestore(&dev_priv->watchdog_lock, irq_flags);
++ ta_mem->ref_count = 1;
++ return ta_mem;
++ out_err1:
++ drm_bo_usage_deref_unlocked(&ta_mem->hw_data);
++ out_err0:
++ drm_free(ta_mem, sizeof(*ta_mem), DRM_MEM_DRIVER);
++ return NULL;
+}
+
-+void psb_watchdog_takedown(struct drm_psb_private *dev_priv)
++int drm_psb_scene_unref_ioctl(struct drm_device *dev,
++ void *data, struct drm_file *file_priv)
+{
-+ unsigned long irq_flags;
++ struct drm_psb_scene *scene = (struct drm_psb_scene *)data;
++ struct drm_user_object *uo;
++ struct drm_ref_object *ro;
++ int ret = 0;
+
-+ spin_lock_irqsave(&dev_priv->watchdog_lock, irq_flags);
-+ dev_priv->timer_available = 0;
-+ spin_unlock_irqrestore(&dev_priv->watchdog_lock, irq_flags);
-+ (void)del_timer_sync(&dev_priv->watchdog_timer);
++ mutex_lock(&dev->struct_mutex);
++ if (!scene->handle_valid)
++ goto out_unlock;
++
++ uo = drm_lookup_user_object(file_priv, scene->handle);
++ if (!uo) {
++ ret = -EINVAL;
++ goto out_unlock;
++ }
++ if (uo->type != PSB_USER_OBJECT_SCENE_POOL) {
++ DRM_ERROR("Not a scene pool object.\n");
++ ret = -EINVAL;
++ goto out_unlock;
++ }
++ if (uo->owner != file_priv) {
++ DRM_ERROR("Not owner of scene pool object.\n");
++ ret = -EPERM;
++ goto out_unlock;
++ }
++
++ scene->handle_valid = 0;
++ ro = drm_lookup_ref_object(file_priv, uo, _DRM_REF_USE);
++ BUG_ON(!ro);
++ drm_remove_ref_object(file_priv, ro);
++
++ out_unlock:
++ mutex_unlock(&dev->struct_mutex);
++ return ret;
+}
-Index: linux-2.6.28/drivers/gpu/drm/psb/psb_scene.c
+Index: linux-2.6.28/drivers/gpu/drm/psb/psb_scene.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/psb/psb_scene.c 2009-02-12 09:14:42.000000000 +0000
-@@ -0,0 +1,531 @@
++++ linux-2.6.28/drivers/gpu/drm/psb/psb_scene.h 2009-02-12 09:14:42.000000000 +0000
+@@ -0,0 +1,112 @@
+/**************************************************************************
+ * Copyright (c) 2007, Intel Corporation.
+ * All Rights Reserved.
+ * Authors: Thomas Hellstrom <thomas-at-tungstengraphics.com>
+ */
+
-+#include "drmP.h"
-+#include "psb_drv.h"
-+#include "psb_scene.h"
-+
-+void psb_clear_scene_atomic(struct psb_scene *scene)
-+{
-+ int i;
-+ struct page *page;
-+ void *v;
++#ifndef _PSB_SCENE_H_
++#define _PSB_SCENE_H_
+
-+ for (i = 0; i < scene->clear_num_pages; ++i) {
-+ page = drm_ttm_get_page(scene->hw_data->ttm,
-+ scene->clear_p_start + i);
-+ if (in_irq())
-+ v = kmap_atomic(page, KM_IRQ0);
-+ else
-+ v = kmap_atomic(page, KM_USER0);
++#define PSB_USER_OBJECT_SCENE_POOL drm_driver_type0
++#define PSB_USER_OBJECT_TA_MEM drm_driver_type1
++#define PSB_MAX_NUM_SCENES 8
+
-+ memset(v, 0, PAGE_SIZE);
++struct psb_hw_scene;
++struct psb_hw_ta_mem;
+
-+ if (in_irq())
-+ kunmap_atomic(v, KM_IRQ0);
-+ else
-+ kunmap_atomic(v, KM_USER0);
-+ }
-+}
++struct psb_scene_pool {
++ struct drm_device *dev;
++ struct drm_user_object user;
++ uint32_t ref_count;
++ uint32_t w;
++ uint32_t h;
++ uint32_t cur_scene;
++ struct psb_scene *scenes[PSB_MAX_NUM_SCENES];
++ uint32_t num_scenes;
++};
+
-+int psb_clear_scene(struct psb_scene *scene)
-+{
-+ struct drm_bo_kmap_obj bmo;
-+ int is_iomem;
-+ void *addr;
++struct psb_scene {
++ struct drm_device *dev;
++ atomic_t ref_count;
++ uint32_t hw_cookie[PSB_SCENE_HW_COOKIE_SIZE];
++ uint32_t bo_size;
++ uint32_t w;
++ uint32_t h;
++ struct psb_ta_mem *ta_mem;
++ struct psb_hw_scene *hw_scene;
++ struct drm_buffer_object *hw_data;
++ uint32_t flags;
++ uint32_t clear_p_start;
++ uint32_t clear_num_pages;
++};
+
-+ int ret = drm_bo_kmap(scene->hw_data, scene->clear_p_start,
-+ scene->clear_num_pages, &bmo);
++struct psb_scene_entry {
++ struct list_head head;
++ struct psb_scene *scene;
++};
+
-+ PSB_DEBUG_RENDER("Scene clear\n");
-+ if (ret)
-+ return ret;
++struct psb_user_scene {
++ struct drm_device *dev;
++ struct drm_user_object user;
++};
+
-+ addr = drm_bmo_virtual(&bmo, &is_iomem);
-+ BUG_ON(is_iomem);
-+ memset(addr, 0, scene->clear_num_pages << PAGE_SHIFT);
-+ drm_bo_kunmap(&bmo);
++struct psb_ta_mem {
++ struct drm_device *dev;
++ struct drm_user_object user;
++ uint32_t ref_count;
++ uint32_t hw_cookie[PSB_TA_MEM_HW_COOKIE_SIZE];
++ uint32_t bo_size;
++ struct drm_buffer_object *ta_memory;
++ struct drm_buffer_object *hw_data;
++ int is_deallocating;
++ int deallocating_scheduled;
++};
+
-+ return 0;
-+}
++extern struct psb_scene_pool *psb_scene_pool_alloc(struct drm_file *priv,
++ int shareable,
++ uint32_t num_scenes,
++ uint32_t w, uint32_t h);
++extern void psb_scene_pool_unref_devlocked(struct psb_scene_pool **pool);
++extern struct psb_scene_pool *psb_scene_pool_lookup_devlocked(struct drm_file
++ *priv,
++ uint32_t handle,
++ int check_owner);
++extern int psb_validate_scene_pool(struct psb_scene_pool *pool, uint64_t flags,
++ uint64_t mask, uint32_t hint, uint32_t w,
++ uint32_t h, int final_pass,
++ struct psb_scene **scene_p);
++extern void psb_scene_unref_devlocked(struct psb_scene **scene);
++extern struct psb_scene *psb_scene_ref(struct psb_scene *src);
++extern int drm_psb_scene_unref_ioctl(struct drm_device *dev,
++ void *data, struct drm_file *file_priv);
+
-+static void psb_destroy_scene_devlocked(struct psb_scene *scene)
++static inline uint32_t psb_scene_pool_handle(struct psb_scene_pool *pool)
+{
-+ if (!scene)
-+ return;
-+
-+ PSB_DEBUG_RENDER("Scene destroy\n");
-+ drm_bo_usage_deref_locked(&scene->hw_data);
-+ drm_free(scene, sizeof(*scene), DRM_MEM_DRIVER);
++ return pool->user.hash.key;
+}
++extern struct psb_ta_mem *psb_alloc_ta_mem(struct drm_device *dev,
++ uint32_t pages);
++extern void psb_ta_mem_ref_devlocked(struct psb_ta_mem **dst,
++ struct psb_ta_mem *src);
++extern void psb_ta_mem_unref_devlocked(struct psb_ta_mem **ta_mem);
+
-+void psb_scene_unref_devlocked(struct psb_scene **scene)
-+{
-+ struct psb_scene *tmp_scene = *scene;
++#endif
+Index: linux-2.6.28/drivers/gpu/drm/psb/psb_schedule.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.28/drivers/gpu/drm/psb/psb_schedule.c 2009-02-12 09:14:42.000000000 +0000
+@@ -0,0 +1,1445 @@
++/**************************************************************************
++ * Copyright (c) 2007, Intel Corporation.
++ * All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
++ *
++ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
++ * develop this driver.
++ *
++ **************************************************************************/
++/*
++ * Authors: Thomas Hellstrom <thomas-at-tungstengraphics.com>
++ */
+
-+ PSB_DEBUG_RENDER("Scene unref\n");
-+ *scene = NULL;
-+ if (atomic_dec_and_test(&tmp_scene->ref_count)) {
-+ psb_scheduler_remove_scene_refs(tmp_scene);
-+ psb_destroy_scene_devlocked(tmp_scene);
-+ }
-+}
++#include "drmP.h"
++#include "psb_drm.h"
++#include "psb_drv.h"
++#include "psb_reg.h"
++#include "psb_scene.h"
+
-+struct psb_scene *psb_scene_ref(struct psb_scene *src)
-+{
-+ PSB_DEBUG_RENDER("Scene ref\n");
-+ atomic_inc(&src->ref_count);
-+ return src;
-+}
++#define PSB_ALLOWED_RASTER_RUNTIME (DRM_HZ * 20)
++#define PSB_RASTER_TIMEOUT (DRM_HZ / 2)
++#define PSB_TA_TIMEOUT (DRM_HZ / 5)
+
-+static struct psb_scene *psb_alloc_scene(struct drm_device *dev,
-+ uint32_t w, uint32_t h)
-+{
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
-+ int ret = -EINVAL;
-+ struct psb_scene *scene;
-+ uint32_t bo_size;
-+ struct psb_xhw_buf buf;
++#undef PSB_SOFTWARE_WORKAHEAD
+
-+ PSB_DEBUG_RENDER("Alloc scene w %u h %u\n", w, h);
++#ifdef PSB_STABLE_SETTING
+
-+ scene = drm_calloc(1, sizeof(*scene), DRM_MEM_DRIVER);
++/*
++ * Software blocks completely while the engines are working so there can be no
++ * overlap.
++ */
+
-+ if (!scene) {
-+ DRM_ERROR("Out of memory allocating scene object.\n");
-+ return NULL;
-+ }
++#define PSB_WAIT_FOR_RASTER_COMPLETION
++#define PSB_WAIT_FOR_TA_COMPLETION
+
-+ scene->dev = dev;
-+ scene->w = w;
-+ scene->h = h;
-+ scene->hw_scene = NULL;
-+ atomic_set(&scene->ref_count, 1);
++#elif defined(PSB_PARANOID_SETTING)
++/*
++ * Software blocks "almost" while the engines are working so there can be no
++ * overlap.
++ */
+
-+ INIT_LIST_HEAD(&buf.head);
-+ ret = psb_xhw_scene_info(dev_priv, &buf, scene->w, scene->h,
-+ scene->hw_cookie, &bo_size,
-+ &scene->clear_p_start,
-+ &scene->clear_num_pages);
-+ if (ret)
-+ goto out_err;
++#define PSB_WAIT_FOR_RASTER_COMPLETION
++#define PSB_WAIT_FOR_TA_COMPLETION
++#define PSB_BE_PARANOID
+
-+ ret = drm_buffer_object_create(dev, bo_size, drm_bo_type_kernel,
-+ DRM_PSB_FLAG_MEM_MMU |
-+ DRM_BO_FLAG_READ |
-+ DRM_BO_FLAG_CACHED |
-+ PSB_BO_FLAG_SCENE |
-+ DRM_BO_FLAG_WRITE,
-+ DRM_BO_HINT_DONT_FENCE,
-+ 0, 0, &scene->hw_data);
-+ if (ret)
-+ goto out_err;
++#elif defined(PSB_SOME_OVERLAP_BUT_LOCKUP)
++/*
++ * Software leaps ahead while the rasterizer is running and prepares
++ * a new ta job that can be scheduled before the rasterizer has
++ * finished.
++ */
+
-+ return scene;
-+ out_err:
-+ drm_free(scene, sizeof(*scene), DRM_MEM_DRIVER);
-+ return NULL;
-+}
++#define PSB_WAIT_FOR_TA_COMPLETION
+
-+int psb_validate_scene_pool(struct psb_scene_pool *pool, uint64_t flags,
-+ uint64_t mask,
-+ uint32_t hint,
-+ uint32_t w,
-+ uint32_t h,
-+ int final_pass, struct psb_scene **scene_p)
-+{
-+ struct drm_device *dev = pool->dev;
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
-+ struct psb_scene *scene = pool->scenes[pool->cur_scene];
-+ int ret;
-+ unsigned long irq_flags;
-+ struct psb_scheduler *scheduler = &dev_priv->scheduler;
-+ uint32_t bin_pt_offset;
-+ uint32_t bin_param_offset;
++#elif defined(PSB_SOFTWARE_WORKAHEAD)
++/*
++ * Don't sync, but allow software to work ahead. and queue a number of jobs.
++ * But block overlapping in the scheduler.
++ */
+
-+ PSB_DEBUG_RENDER("Validate scene pool. Scene %u\n", pool->cur_scene);
++#define PSB_BLOCK_OVERLAP
++#define ONLY_ONE_JOB_IN_RASTER_QUEUE
+
-+ if (unlikely(!dev_priv->ta_mem)) {
-+ dev_priv->ta_mem =
-+ psb_alloc_ta_mem(dev, dev_priv->ta_mem_pages);
-+ if (!dev_priv->ta_mem)
-+ return -ENOMEM;
++#endif
+
-+ bin_pt_offset = ~0;
-+ bin_param_offset = ~0;
-+ } else {
-+ bin_pt_offset = dev_priv->ta_mem->hw_data->offset;
-+ bin_param_offset = dev_priv->ta_mem->ta_memory->offset;
-+ }
++/*
++ * Avoid pixelbe pagefaults on C0.
++ */
++#if 0
++#define PSB_BLOCK_OVERLAP
++#endif
+
-+ pool->w = w;
-+ pool->h = h;
-+ if (scene && (scene->w != pool->w || scene->h != pool->h)) {
-+ spin_lock_irqsave(&scheduler->lock, irq_flags);
-+ if (scene->flags & PSB_SCENE_FLAG_DIRTY) {
-+ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
-+ DRM_ERROR("Trying to resize a dirty scene.\n");
-+ return -EINVAL;
-+ }
-+ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
-+ mutex_lock(&dev->struct_mutex);
-+ psb_scene_unref_devlocked(&pool->scenes[pool->cur_scene]);
-+ mutex_unlock(&dev->struct_mutex);
-+ scene = NULL;
-+ }
++static void psb_dispatch_ta(struct drm_psb_private *dev_priv,
++ struct psb_scheduler *scheduler,
++ uint32_t reply_flag);
++static void psb_dispatch_raster(struct drm_psb_private *dev_priv,
++ struct psb_scheduler *scheduler,
++ uint32_t reply_flag);
+
-+ if (!scene) {
-+ pool->scenes[pool->cur_scene] = scene =
-+ psb_alloc_scene(pool->dev, pool->w, pool->h);
++#ifdef FIX_TG_16
+
-+ if (!scene)
-+ return -ENOMEM;
++static void psb_2d_atomic_unlock(struct drm_psb_private *dev_priv);
++static int psb_2d_trylock(struct drm_psb_private *dev_priv);
++static int psb_check_2d_idle(struct drm_psb_private *dev_priv);
+
-+ scene->flags = PSB_SCENE_FLAG_CLEARED;
-+ }
++#endif
+
-+ /*
-+ * FIXME: We need atomic bit manipulation here for the
-+ * scheduler. For now use the spinlock.
-+ */
++void psb_scheduler_lockup(struct drm_psb_private *dev_priv,
++ int *lockup, int *idle)
++{
++ unsigned long irq_flags;
++ struct psb_scheduler *scheduler = &dev_priv->scheduler;
+
-+ spin_lock_irqsave(&scheduler->lock, irq_flags);
-+ if (!(scene->flags & PSB_SCENE_FLAG_CLEARED)) {
-+ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
-+ PSB_DEBUG_RENDER("Waiting to clear scene memory.\n");
-+ mutex_lock(&scene->hw_data->mutex);
-+ ret = drm_bo_wait(scene->hw_data, 0, 0, 0);
-+ mutex_unlock(&scene->hw_data->mutex);
-+ if (ret)
-+ return ret;
++ *lockup = 0;
++ *idle = 1;
+
-+ ret = psb_clear_scene(scene);
++ spin_lock_irqsave(&scheduler->lock, irq_flags);
+
-+ if (ret)
-+ return ret;
-+ spin_lock_irqsave(&scheduler->lock, irq_flags);
-+ scene->flags |= PSB_SCENE_FLAG_CLEARED;
++ if (scheduler->current_task[PSB_SCENE_ENGINE_TA] != NULL &&
++ time_after_eq(jiffies, scheduler->ta_end_jiffies)) {
++ *lockup = 1;
++ }
++ if (!*lockup
++ && (scheduler->current_task[PSB_SCENE_ENGINE_RASTER] != NULL)
++ && time_after_eq(jiffies, scheduler->raster_end_jiffies)) {
++ *lockup = 1;
+ }
++ if (!*lockup)
++ *idle = scheduler->idle;
++
+ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
++}
+
-+ ret = drm_bo_do_validate(scene->hw_data, flags, mask, hint,
-+ PSB_ENGINE_TA, 0, NULL);
-+ if (ret)
-+ return ret;
-+ ret = drm_bo_do_validate(dev_priv->ta_mem->hw_data, 0, 0, 0,
-+ PSB_ENGINE_TA, 0, NULL);
-+ if (ret)
-+ return ret;
-+ ret = drm_bo_do_validate(dev_priv->ta_mem->ta_memory, 0, 0, 0,
-+ PSB_ENGINE_TA, 0, NULL);
-+ if (ret)
-+ return ret;
++static inline void psb_set_idle(struct psb_scheduler *scheduler)
++{
++ scheduler->idle =
++ (scheduler->current_task[PSB_SCENE_ENGINE_RASTER] == NULL) &&
++ (scheduler->current_task[PSB_SCENE_ENGINE_TA] == NULL);
++ if (scheduler->idle)
++ wake_up(&scheduler->idle_queue);
++}
+
-+ if (unlikely(bin_param_offset !=
-+ dev_priv->ta_mem->ta_memory->offset ||
-+ bin_pt_offset !=
-+ dev_priv->ta_mem->hw_data->offset ||
-+ dev_priv->force_ta_mem_load)) {
++/*
++ * Call with the scheduler spinlock held.
++ * Assigns a scene context to either the ta or the rasterizer,
++ * flushing out other scenes to memory if necessary.
++ */
+
-+ struct psb_xhw_buf buf;
++static int psb_set_scene_fire(struct psb_scheduler *scheduler,
++ struct psb_scene *scene,
++ int engine, struct psb_task *task)
++{
++ uint32_t flags = 0;
++ struct psb_hw_scene *hw_scene;
++ struct drm_device *dev = scene->dev;
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
+
-+ INIT_LIST_HEAD(&buf.head);
-+ ret = psb_xhw_ta_mem_load(dev_priv, &buf,
-+ PSB_TA_MEM_FLAG_TA |
-+ PSB_TA_MEM_FLAG_RASTER |
-+ PSB_TA_MEM_FLAG_HOSTA |
-+ PSB_TA_MEM_FLAG_HOSTD |
-+ PSB_TA_MEM_FLAG_INIT,
-+ dev_priv->ta_mem->ta_memory->offset,
-+ dev_priv->ta_mem->hw_data->offset,
-+ dev_priv->ta_mem->hw_cookie);
-+ if (ret)
-+ return ret;
++ hw_scene = scene->hw_scene;
++ if (hw_scene && hw_scene->last_scene == scene) {
+
-+ dev_priv->force_ta_mem_load = 0;
-+ }
++ /*
++ * Reuse the last hw scene context and delete it from the
++ * free list.
++ */
+
-+ if (final_pass) {
++ PSB_DEBUG_RENDER("Reusing hw scene %d.\n",
++ hw_scene->context_number);
++ if (scene->flags & PSB_SCENE_FLAG_DIRTY) {
++
++ /*
++ * No hw context initialization to be done.
++ */
++
++ flags |= PSB_SCENE_FLAG_SETUP_ONLY;
++ }
++
++ list_del_init(&hw_scene->head);
++
++ } else {
++ struct list_head *list;
++ hw_scene = NULL;
+
+ /*
-+ * Clear the scene on next use. Advance the scene counter.
++ * Grab a new hw scene context.
+ */
+
-+ spin_lock_irqsave(&scheduler->lock, irq_flags);
-+ scene->flags &= ~PSB_SCENE_FLAG_CLEARED;
-+ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
-+ pool->cur_scene = (pool->cur_scene + 1) % pool->num_scenes;
++ list_for_each(list, &scheduler->hw_scenes) {
++ hw_scene = list_entry(list, struct psb_hw_scene, head);
++ break;
++ }
++ BUG_ON(!hw_scene);
++ PSB_DEBUG_RENDER("New hw scene %d.\n",
++ hw_scene->context_number);
++
++ list_del_init(list);
+ }
++ scene->hw_scene = hw_scene;
++ hw_scene->last_scene = scene;
+
-+ *scene_p = psb_scene_ref(scene);
-+ return 0;
++ flags |= PSB_SCENE_FLAG_SETUP;
++
++ /*
++ * Switch context and setup the engine.
++ */
++
++ return psb_xhw_scene_bind_fire(dev_priv,
++ &task->buf,
++ task->flags,
++ hw_scene->context_number,
++ scene->hw_cookie,
++ task->oom_cmds,
++ task->oom_cmd_size,
++ scene->hw_data->offset,
++ engine, flags | scene->flags);
+}
+
-+static void psb_scene_pool_destroy_devlocked(struct psb_scene_pool *pool)
++static inline void psb_report_fence(struct psb_scheduler *scheduler,
++ uint32_t class,
++ uint32_t sequence,
++ uint32_t type, int call_handler)
+{
-+ int i;
++ struct psb_scheduler_seq *seq = &scheduler->seq[type];
+
-+ if (!pool)
-+ return;
++ seq->sequence = sequence;
++ seq->reported = 0;
++ if (call_handler)
++ psb_fence_handler(scheduler->dev, class);
++}
+
-+ PSB_DEBUG_RENDER("Scene pool destroy.\n");
-+ for (i = 0; i < pool->num_scenes; ++i) {
-+ PSB_DEBUG_RENDER("scenes %d is 0x%08lx\n", i,
-+ (unsigned long)pool->scenes[i]);
-+ if (pool->scenes[i])
-+ psb_scene_unref_devlocked(&pool->scenes[i]);
-+ }
-+ drm_free(pool, sizeof(*pool), DRM_MEM_DRIVER);
-+}
++static void psb_schedule_raster(struct drm_psb_private *dev_priv,
++ struct psb_scheduler *scheduler);
+
-+void psb_scene_pool_unref_devlocked(struct psb_scene_pool **pool)
++static void psb_schedule_ta(struct drm_psb_private *dev_priv,
++ struct psb_scheduler *scheduler)
+{
-+ struct psb_scene_pool *tmp_pool = *pool;
-+ struct drm_device *dev = tmp_pool->dev;
++ struct psb_task *task = NULL;
++ struct list_head *list, *next;
++ int pushed_raster_task = 0;
+
-+ PSB_DEBUG_RENDER("Scene pool unref\n");
-+ (void)dev;
-+ DRM_ASSERT_LOCKED(&dev->struct_mutex);
-+ *pool = NULL;
-+ if (--tmp_pool->ref_count == 0)
-+ psb_scene_pool_destroy_devlocked(tmp_pool);
-+}
++ PSB_DEBUG_RENDER("schedule ta\n");
+
-+struct psb_scene_pool *psb_scene_pool_ref_devlocked(struct psb_scene_pool *src)
-+{
-+ ++src->ref_count;
-+ return src;
-+}
++ if (scheduler->idle_count != 0)
++ return;
+
-+/*
-+ * Callback for user object manager.
-+ */
++ if (scheduler->current_task[PSB_SCENE_ENGINE_TA] != NULL)
++ return;
+
-+static void psb_scene_pool_destroy(struct drm_file *priv,
-+ struct drm_user_object *base)
-+{
-+ struct psb_scene_pool *pool =
-+ drm_user_object_entry(base, struct psb_scene_pool, user);
++ if (scheduler->ta_state)
++ return;
+
-+ psb_scene_pool_unref_devlocked(&pool);
-+}
++ /*
++ * Skip the ta stage for rasterization-only
++ * tasks. They arrive here to make sure we're rasterizing
++ * tasks in the correct order.
++ */
+
-+struct psb_scene_pool *psb_scene_pool_lookup_devlocked(struct drm_file *priv,
-+ uint32_t handle,
-+ int check_owner)
-+{
-+ struct drm_user_object *uo;
-+ struct psb_scene_pool *pool;
++ list_for_each_safe(list, next, &scheduler->ta_queue) {
++ task = list_entry(list, struct psb_task, head);
++ if (task->task_type != psb_raster_task)
++ break;
+
-+ uo = drm_lookup_user_object(priv, handle);
-+ if (!uo || (uo->type != PSB_USER_OBJECT_SCENE_POOL)) {
-+ DRM_ERROR("Could not find scene pool object 0x%08x\n", handle);
-+ return NULL;
++ list_del_init(list);
++ list_add_tail(list, &scheduler->raster_queue);
++ psb_report_fence(scheduler, task->engine, task->sequence,
++ _PSB_FENCE_TA_DONE_SHIFT, 1);
++ task = NULL;
++ pushed_raster_task = 1;
+ }
+
-+ if (check_owner && priv != uo->owner) {
-+ if (!drm_lookup_ref_object(priv, uo, _DRM_REF_USE))
-+ return NULL;
-+ }
++ if (pushed_raster_task)
++ psb_schedule_raster(dev_priv, scheduler);
+
-+ pool = drm_user_object_entry(uo, struct psb_scene_pool, user);
-+ return psb_scene_pool_ref_devlocked(pool);
-+}
++ if (!task)
++ return;
+
-+struct psb_scene_pool *psb_scene_pool_alloc(struct drm_file *priv,
-+ int shareable,
-+ uint32_t num_scenes,
-+ uint32_t w, uint32_t h)
-+{
-+ struct drm_device *dev = priv->minor->dev;
-+ struct psb_scene_pool *pool;
-+ int ret;
++ /*
++ * Still waiting for a vistest?
++ */
+
-+ PSB_DEBUG_RENDER("Scene pool alloc\n");
-+ pool = drm_calloc(1, sizeof(*pool), DRM_MEM_DRIVER);
-+ if (!pool) {
-+ DRM_ERROR("Out of memory allocating scene pool object.\n");
-+ return NULL;
-+ }
-+ pool->w = w;
-+ pool->h = h;
-+ pool->dev = dev;
-+ pool->num_scenes = num_scenes;
++ if (scheduler->feedback_task == task)
++ return;
+
-+ mutex_lock(&dev->struct_mutex);
-+ ret = drm_add_user_object(priv, &pool->user, shareable);
-+ if (ret)
-+ goto out_err;
++#ifdef ONLY_ONE_JOB_IN_RASTER_QUEUE
+
-+ pool->user.type = PSB_USER_OBJECT_SCENE_POOL;
-+ pool->user.remove = &psb_scene_pool_destroy;
-+ pool->ref_count = 2;
-+ mutex_unlock(&dev->struct_mutex);
-+ return pool;
-+ out_err:
-+ drm_free(pool, sizeof(*pool), DRM_MEM_DRIVER);
-+ return NULL;
-+}
++ /*
++ * Block ta from trying to use both hardware contexts
++ * without the rasterizer starting to render from one of them.
++ */
+
-+/*
-+ * Code to support multiple ta memory buffers.
-+ */
++ if (!list_empty(&scheduler->raster_queue)) {
++ return;
++ }
++#endif
+
-+static void psb_destroy_ta_mem_devlocked(struct psb_ta_mem *ta_mem)
-+{
-+ if (!ta_mem)
++#ifdef PSB_BLOCK_OVERLAP
++ /*
++ * Make sure rasterizer isn't doing anything.
++ */
++ if (scheduler->current_task[PSB_SCENE_ENGINE_RASTER] != NULL)
++ return;
++#endif
++ if (list_empty(&scheduler->hw_scenes))
+ return;
+
-+ drm_bo_usage_deref_locked(&ta_mem->hw_data);
-+ drm_bo_usage_deref_locked(&ta_mem->ta_memory);
-+ drm_free(ta_mem, sizeof(*ta_mem), DRM_MEM_DRIVER);
-+}
++#ifdef FIX_TG_16
++ if (psb_check_2d_idle(dev_priv))
++ return;
++#endif
+
-+void psb_ta_mem_unref_devlocked(struct psb_ta_mem **ta_mem)
-+{
-+ struct psb_ta_mem *tmp_ta_mem = *ta_mem;
-+ struct drm_device *dev = tmp_ta_mem->dev;
++ list_del_init(&task->head);
++ if (task->flags & PSB_FIRE_FLAG_XHW_OOM)
++ scheduler->ta_state = 1;
+
-+ (void)dev;
-+ DRM_ASSERT_LOCKED(&dev->struct_mutex);
-+ *ta_mem = NULL;
-+ if (--tmp_ta_mem->ref_count == 0)
-+ psb_destroy_ta_mem_devlocked(tmp_ta_mem);
++ scheduler->current_task[PSB_SCENE_ENGINE_TA] = task;
++ scheduler->idle = 0;
++ scheduler->ta_end_jiffies = jiffies + PSB_TA_TIMEOUT;
++
++ task->reply_flags = (task->flags & PSB_FIRE_FLAG_XHW_OOM) ?
++ 0x00000000 : PSB_RF_FIRE_TA;
++
++ (void)psb_reg_submit(dev_priv, task->ta_cmds, task->ta_cmd_size);
++ psb_set_scene_fire(scheduler, task->scene, PSB_SCENE_ENGINE_TA, task);
++ psb_schedule_watchdog(dev_priv);
+}
+
-+void psb_ta_mem_ref_devlocked(struct psb_ta_mem **dst, struct psb_ta_mem *src)
++static int psb_fire_raster(struct psb_scheduler *scheduler,
++ struct psb_task *task)
+{
-+ struct drm_device *dev = src->dev;
++ struct drm_device *dev = scheduler->dev;
++ struct drm_psb_private *dev_priv = (struct drm_psb_private *)
++ dev->dev_private;
+
-+ (void)dev;
-+ DRM_ASSERT_LOCKED(&dev->struct_mutex);
-+ *dst = src;
-+ ++src->ref_count;
++ PSB_DEBUG_RENDER("Fire raster %d\n", task->sequence);
++
++ return psb_xhw_fire_raster(dev_priv, &task->buf, task->flags);
+}
+
-+struct psb_ta_mem *psb_alloc_ta_mem(struct drm_device *dev, uint32_t pages)
-+{
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
-+ int ret = -EINVAL;
-+ struct psb_ta_mem *ta_mem;
-+ uint32_t bo_size;
-+ struct psb_xhw_buf buf;
++/*
++ * Take the first rasterization task from the hp raster queue or from the
++ * raster queue and fire the rasterizer.
++ */
+
-+ INIT_LIST_HEAD(&buf.head);
++static void psb_schedule_raster(struct drm_psb_private *dev_priv,
++ struct psb_scheduler *scheduler)
++{
++ struct psb_task *task;
++ struct list_head *list;
+
-+ ta_mem = drm_calloc(1, sizeof(*ta_mem), DRM_MEM_DRIVER);
++ if (scheduler->idle_count != 0)
++ return;
+
-+ if (!ta_mem) {
-+ DRM_ERROR("Out of memory allocating parameter memory.\n");
-+ return NULL;
++ if (scheduler->current_task[PSB_SCENE_ENGINE_RASTER] != NULL) {
++ PSB_DEBUG_RENDER("Raster busy.\n");
++ return;
++ }
++#ifdef PSB_BLOCK_OVERLAP
++ if (scheduler->current_task[PSB_SCENE_ENGINE_TA] != NULL) {
++ PSB_DEBUG_RENDER("TA busy.\n");
++ return;
+ }
++#endif
+
-+ ret = psb_xhw_ta_mem_info(dev_priv, &buf, pages,
-+ ta_mem->hw_cookie, &bo_size);
-+ if (ret == -ENOMEM) {
-+ DRM_ERROR("Parameter memory size is too small.\n");
-+ DRM_INFO("Attempted to use %u kiB of parameter memory.\n",
-+ (unsigned int)(pages * (PAGE_SIZE / 1024)));
-+ DRM_INFO("The Xpsb driver thinks this is too small and\n");
-+ DRM_INFO("suggests %u kiB. Check the psb DRM\n",
-+ (unsigned int)(bo_size / 1024));
-+ DRM_INFO("\"ta_mem_size\" parameter!\n");
++ if (!list_empty(&scheduler->hp_raster_queue))
++ list = scheduler->hp_raster_queue.next;
++ else if (!list_empty(&scheduler->raster_queue))
++ list = scheduler->raster_queue.next;
++ else {
++ PSB_DEBUG_RENDER("Nothing in list\n");
++ return;
+ }
-+ if (ret)
-+ goto out_err0;
+
-+ bo_size = pages * PAGE_SIZE;
-+ ta_mem->dev = dev;
-+ ret = drm_buffer_object_create(dev, bo_size, drm_bo_type_kernel,
-+ DRM_PSB_FLAG_MEM_MMU | DRM_BO_FLAG_READ |
-+ DRM_BO_FLAG_WRITE |
-+ PSB_BO_FLAG_SCENE,
-+ DRM_BO_HINT_DONT_FENCE, 0, 0,
-+ &ta_mem->hw_data);
-+ if (ret)
-+ goto out_err0;
++ task = list_entry(list, struct psb_task, head);
+
-+ ret =
-+ drm_buffer_object_create(dev, pages << PAGE_SHIFT,
-+ drm_bo_type_kernel,
-+ DRM_PSB_FLAG_MEM_RASTGEOM |
-+ DRM_BO_FLAG_READ |
-+ DRM_BO_FLAG_WRITE |
-+ PSB_BO_FLAG_SCENE,
-+ DRM_BO_HINT_DONT_FENCE, 0,
-+ 1024 * 1024 >> PAGE_SHIFT,
-+ &ta_mem->ta_memory);
-+ if (ret)
-+ goto out_err1;
++ /*
++ * Sometimes changing ZLS format requires an ISP reset.
++ * Doesn't seem to consume too much time.
++ */
+
-+ ta_mem->ref_count = 1;
-+ return ta_mem;
-+ out_err1:
-+ drm_bo_usage_deref_unlocked(&ta_mem->hw_data);
-+ out_err0:
-+ drm_free(ta_mem, sizeof(*ta_mem), DRM_MEM_DRIVER);
-+ return NULL;
-+}
++ if (task->scene)
++ PSB_WSGX32(_PSB_CS_RESET_ISP_RESET, PSB_CR_SOFT_RESET);
+
-+int drm_psb_scene_unref_ioctl(struct drm_device *dev,
-+ void *data, struct drm_file *file_priv)
-+{
-+ struct drm_psb_scene *scene = (struct drm_psb_scene *)data;
-+ struct drm_user_object *uo;
-+ struct drm_ref_object *ro;
-+ int ret = 0;
++ scheduler->current_task[PSB_SCENE_ENGINE_RASTER] = task;
+
-+ mutex_lock(&dev->struct_mutex);
-+ if (!scene->handle_valid)
-+ goto out_unlock;
++ list_del_init(list);
++ scheduler->idle = 0;
++ scheduler->raster_end_jiffies = jiffies + PSB_RASTER_TIMEOUT;
++ scheduler->total_raster_jiffies = 0;
+
-+ uo = drm_lookup_user_object(file_priv, scene->handle);
-+ if (!uo) {
-+ ret = -EINVAL;
-+ goto out_unlock;
-+ }
-+ if (uo->type != PSB_USER_OBJECT_SCENE_POOL) {
-+ DRM_ERROR("Not a scene pool object.\n");
-+ ret = -EINVAL;
-+ goto out_unlock;
-+ }
-+ if (uo->owner != file_priv) {
-+ DRM_ERROR("Not owner of scene pool object.\n");
-+ ret = -EPERM;
-+ goto out_unlock;
++ if (task->scene)
++ PSB_WSGX32(0, PSB_CR_SOFT_RESET);
++
++ (void)psb_reg_submit(dev_priv, task->raster_cmds,
++ task->raster_cmd_size);
++
++ if (task->scene) {
++ task->reply_flags = (task->flags & PSB_FIRE_FLAG_XHW_OOM) ?
++ 0x00000000 : PSB_RF_FIRE_RASTER;
++ psb_set_scene_fire(scheduler,
++ task->scene, PSB_SCENE_ENGINE_RASTER, task);
++ } else {
++ task->reply_flags = PSB_RF_DEALLOC | PSB_RF_FIRE_RASTER;
++ psb_fire_raster(scheduler, task);
+ }
++ psb_schedule_watchdog(dev_priv);
++}
+
-+ scene->handle_valid = 0;
-+ ro = drm_lookup_ref_object(file_priv, uo, _DRM_REF_USE);
-+ BUG_ON(!ro);
-+ drm_remove_ref_object(file_priv, ro);
++int psb_extend_raster_timeout(struct drm_psb_private *dev_priv)
++{
++ struct psb_scheduler *scheduler = &dev_priv->scheduler;
++ unsigned long irq_flags;
++ int ret;
+
-+ out_unlock:
-+ mutex_unlock(&dev->struct_mutex);
++ spin_lock_irqsave(&scheduler->lock, irq_flags);
++ scheduler->total_raster_jiffies +=
++ jiffies - scheduler->raster_end_jiffies + PSB_RASTER_TIMEOUT;
++ scheduler->raster_end_jiffies = jiffies + PSB_RASTER_TIMEOUT;
++ ret = (scheduler->total_raster_jiffies > PSB_ALLOWED_RASTER_RUNTIME) ?
++ -EBUSY : 0;
++ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
+ return ret;
+}
-Index: linux-2.6.28/drivers/gpu/drm/psb/psb_scene.h
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/psb/psb_scene.h 2009-02-12 09:14:42.000000000 +0000
-@@ -0,0 +1,112 @@
-+/**************************************************************************
-+ * Copyright (c) 2007, Intel Corporation.
-+ * All Rights Reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms and conditions of the GNU General Public License,
-+ * version 2, as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
-+ *
-+ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
-+ * develop this driver.
-+ *
-+ **************************************************************************/
++
+/*
-+ * Authors: Thomas Hellstrom <thomas-at-tungstengraphics.com>
++ * TA done handler.
+ */
+
-+#ifndef _PSB_SCENE_H_
-+#define _PSB_SCENE_H_
++static void psb_ta_done(struct drm_psb_private *dev_priv,
++ struct psb_scheduler *scheduler)
++{
++ struct psb_task *task = scheduler->current_task[PSB_SCENE_ENGINE_TA];
++ struct psb_scene *scene = task->scene;
+
-+#define PSB_USER_OBJECT_SCENE_POOL drm_driver_type0
-+#define PSB_USER_OBJECT_TA_MEM drm_driver_type1
-+#define PSB_MAX_NUM_SCENES 8
++ PSB_DEBUG_RENDER("TA done %u\n", task->sequence);
+
-+struct psb_hw_scene;
-+struct psb_hw_ta_mem;
++ switch (task->ta_complete_action) {
++ case PSB_RASTER_BLOCK:
++ scheduler->ta_state = 1;
++ scene->flags |=
++ (PSB_SCENE_FLAG_DIRTY | PSB_SCENE_FLAG_COMPLETE);
++ list_add_tail(&task->head, &scheduler->raster_queue);
++ break;
++ case PSB_RASTER:
++ scene->flags |=
++ (PSB_SCENE_FLAG_DIRTY | PSB_SCENE_FLAG_COMPLETE);
++ list_add_tail(&task->head, &scheduler->raster_queue);
++ break;
++ case PSB_RETURN:
++ scheduler->ta_state = 0;
++ scene->flags |= PSB_SCENE_FLAG_DIRTY;
++ list_add_tail(&scene->hw_scene->head, &scheduler->hw_scenes);
+
-+struct psb_scene_pool {
-+ struct drm_device *dev;
-+ struct drm_user_object user;
-+ uint32_t ref_count;
-+ uint32_t w;
-+ uint32_t h;
-+ uint32_t cur_scene;
-+ struct psb_scene *scenes[PSB_MAX_NUM_SCENES];
-+ uint32_t num_scenes;
-+};
++ break;
++ }
+
-+struct psb_scene {
-+ struct drm_device *dev;
-+ atomic_t ref_count;
-+ uint32_t hw_cookie[PSB_SCENE_HW_COOKIE_SIZE];
-+ uint32_t bo_size;
-+ uint32_t w;
-+ uint32_t h;
-+ struct psb_ta_mem *ta_mem;
-+ struct psb_hw_scene *hw_scene;
-+ struct drm_buffer_object *hw_data;
-+ uint32_t flags;
-+ uint32_t clear_p_start;
-+ uint32_t clear_num_pages;
-+};
++ scheduler->current_task[PSB_SCENE_ENGINE_TA] = NULL;
+
-+struct psb_scene_entry {
-+ struct list_head head;
-+ struct psb_scene *scene;
-+};
++#ifdef FIX_TG_16
++ psb_2d_atomic_unlock(dev_priv);
++#endif
+
-+struct psb_user_scene {
-+ struct drm_device *dev;
-+ struct drm_user_object user;
-+};
++ if (task->ta_complete_action != PSB_RASTER_BLOCK)
++ psb_report_fence(scheduler, task->engine, task->sequence,
++ _PSB_FENCE_TA_DONE_SHIFT, 1);
+
-+struct psb_ta_mem {
-+ struct drm_device *dev;
-+ struct drm_user_object user;
-+ uint32_t ref_count;
-+ uint32_t hw_cookie[PSB_TA_MEM_HW_COOKIE_SIZE];
-+ uint32_t bo_size;
-+ struct drm_buffer_object *ta_memory;
-+ struct drm_buffer_object *hw_data;
-+ int is_deallocating;
-+ int deallocating_scheduled;
-+};
++ psb_schedule_raster(dev_priv, scheduler);
++ psb_schedule_ta(dev_priv, scheduler);
++ psb_set_idle(scheduler);
+
-+extern struct psb_scene_pool *psb_scene_pool_alloc(struct drm_file *priv,
-+ int shareable,
-+ uint32_t num_scenes,
-+ uint32_t w, uint32_t h);
-+extern void psb_scene_pool_unref_devlocked(struct psb_scene_pool **pool);
-+extern struct psb_scene_pool *psb_scene_pool_lookup_devlocked(struct drm_file
-+ *priv,
-+ uint32_t handle,
-+ int check_owner);
-+extern int psb_validate_scene_pool(struct psb_scene_pool *pool, uint64_t flags,
-+ uint64_t mask, uint32_t hint, uint32_t w,
-+ uint32_t h, int final_pass,
-+ struct psb_scene **scene_p);
-+extern void psb_scene_unref_devlocked(struct psb_scene **scene);
-+extern struct psb_scene *psb_scene_ref(struct psb_scene *src);
-+extern int drm_psb_scene_unref_ioctl(struct drm_device *dev,
-+ void *data, struct drm_file *file_priv);
++ if (task->ta_complete_action != PSB_RETURN)
++ return;
+
-+static inline uint32_t psb_scene_pool_handle(struct psb_scene_pool *pool)
-+{
-+ return pool->user.hash.key;
++ list_add_tail(&task->head, &scheduler->task_done_queue);
++ schedule_delayed_work(&scheduler->wq, 1);
+}
-+extern struct psb_ta_mem *psb_alloc_ta_mem(struct drm_device *dev,
-+ uint32_t pages);
-+extern void psb_ta_mem_ref_devlocked(struct psb_ta_mem **dst,
-+ struct psb_ta_mem *src);
-+extern void psb_ta_mem_unref_devlocked(struct psb_ta_mem **ta_mem);
+
-+#endif
-Index: linux-2.6.28/drivers/gpu/drm/psb/psb_schedule.c
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/psb/psb_schedule.c 2009-02-12 09:14:42.000000000 +0000
-@@ -0,0 +1,1445 @@
-+/**************************************************************************
-+ * Copyright (c) 2007, Intel Corporation.
-+ * All Rights Reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms and conditions of the GNU General Public License,
-+ * version 2, as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
-+ *
-+ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
-+ * develop this driver.
-+ *
-+ **************************************************************************/
+/*
-+ * Authors: Thomas Hellstrom <thomas-at-tungstengraphics.com>
++ * Rasterizer done handler.
+ */
+
-+#include "drmP.h"
-+#include "psb_drm.h"
-+#include "psb_drv.h"
-+#include "psb_reg.h"
-+#include "psb_scene.h"
-+
-+#define PSB_ALLOWED_RASTER_RUNTIME (DRM_HZ * 20)
-+#define PSB_RASTER_TIMEOUT (DRM_HZ / 2)
-+#define PSB_TA_TIMEOUT (DRM_HZ / 5)
-+
-+#undef PSB_SOFTWARE_WORKAHEAD
-+
-+#ifdef PSB_STABLE_SETTING
-+
-+/*
-+ * Software blocks completely while the engines are working so there can be no
-+ * overlap.
-+ */
-+
-+#define PSB_WAIT_FOR_RASTER_COMPLETION
-+#define PSB_WAIT_FOR_TA_COMPLETION
-+
-+#elif defined(PSB_PARANOID_SETTING)
-+/*
-+ * Software blocks "almost" while the engines are working so there can be no
-+ * overlap.
-+ */
-+
-+#define PSB_WAIT_FOR_RASTER_COMPLETION
-+#define PSB_WAIT_FOR_TA_COMPLETION
-+#define PSB_BE_PARANOID
-+
-+#elif defined(PSB_SOME_OVERLAP_BUT_LOCKUP)
-+/*
-+ * Software leaps ahead while the rasterizer is running and prepares
-+ * a new ta job that can be scheduled before the rasterizer has
-+ * finished.
-+ */
-+
-+#define PSB_WAIT_FOR_TA_COMPLETION
++static void psb_raster_done(struct drm_psb_private *dev_priv,
++ struct psb_scheduler *scheduler)
++{
++ struct psb_task *task =
++ scheduler->current_task[PSB_SCENE_ENGINE_RASTER];
++ struct psb_scene *scene = task->scene;
++ uint32_t complete_action = task->raster_complete_action;
+
-+#elif defined(PSB_SOFTWARE_WORKAHEAD)
-+/*
-+ * Don't sync, but allow software to work ahead. and queue a number of jobs.
-+ * But block overlapping in the scheduler.
-+ */
++ PSB_DEBUG_RENDER("Raster done %u\n", task->sequence);
+
-+#define PSB_BLOCK_OVERLAP
-+#define ONLY_ONE_JOB_IN_RASTER_QUEUE
++ scheduler->current_task[PSB_SCENE_ENGINE_RASTER] = NULL;
+
-+#endif
++ if (complete_action != PSB_RASTER)
++ psb_schedule_raster(dev_priv, scheduler);
+
-+/*
-+ * Avoid pixelbe pagefaults on C0.
-+ */
-+#if 0
-+#define PSB_BLOCK_OVERLAP
-+#endif
++ if (scene) {
++ if (task->feedback.page) {
++ if (unlikely(scheduler->feedback_task)) {
++ /*
++ * This should never happen, since the previous
++ * feedback query will return before the next
++ * raster task is fired.
++ */
++ DRM_ERROR("Feedback task busy.\n");
++ }
++ scheduler->feedback_task = task;
++ psb_xhw_vistest(dev_priv, &task->buf);
++ }
++ switch (complete_action) {
++ case PSB_RETURN:
++ scene->flags &=
++ ~(PSB_SCENE_FLAG_DIRTY | PSB_SCENE_FLAG_COMPLETE);
++ list_add_tail(&scene->hw_scene->head,
++ &scheduler->hw_scenes);
++ psb_report_fence(scheduler, task->engine,
++ task->sequence,
++ _PSB_FENCE_SCENE_DONE_SHIFT, 1);
++ if (task->flags & PSB_FIRE_FLAG_XHW_OOM) {
++ scheduler->ta_state = 0;
++ }
++ break;
++ case PSB_RASTER:
++ list_add(&task->head, &scheduler->raster_queue);
++ task->raster_complete_action = PSB_RETURN;
++ psb_schedule_raster(dev_priv, scheduler);
++ break;
++ case PSB_TA:
++ list_add(&task->head, &scheduler->ta_queue);
++ scheduler->ta_state = 0;
++ task->raster_complete_action = PSB_RETURN;
++ task->ta_complete_action = PSB_RASTER;
++ break;
+
-+static void psb_dispatch_ta(struct drm_psb_private *dev_priv,
-+ struct psb_scheduler *scheduler,
-+ uint32_t reply_flag);
-+static void psb_dispatch_raster(struct drm_psb_private *dev_priv,
-+ struct psb_scheduler *scheduler,
-+ uint32_t reply_flag);
++ }
++ }
++ psb_schedule_ta(dev_priv, scheduler);
++ psb_set_idle(scheduler);
+
-+#ifdef FIX_TG_16
++ if (complete_action == PSB_RETURN) {
++ if (task->scene == NULL) {
++ psb_report_fence(scheduler, task->engine,
++ task->sequence,
++ _PSB_FENCE_RASTER_DONE_SHIFT, 1);
++ }
++ if (!task->feedback.page) {
++ list_add_tail(&task->head, &scheduler->task_done_queue);
++ schedule_delayed_work(&scheduler->wq, 1);
++ }
++ }
++}
+
-+static void psb_2d_atomic_unlock(struct drm_psb_private *dev_priv);
-+static int psb_2d_trylock(struct drm_psb_private *dev_priv);
-+static int psb_check_2d_idle(struct drm_psb_private *dev_priv);
++void psb_scheduler_pause(struct drm_psb_private *dev_priv)
++{
++ struct psb_scheduler *scheduler = &dev_priv->scheduler;
++ unsigned long irq_flags;
+
-+#endif
++ spin_lock_irqsave(&scheduler->lock, irq_flags);
++ scheduler->idle_count++;
++ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
++}
+
-+void psb_scheduler_lockup(struct drm_psb_private *dev_priv,
-+ int *lockup, int *idle)
++void psb_scheduler_restart(struct drm_psb_private *dev_priv)
+{
-+ unsigned long irq_flags;
+ struct psb_scheduler *scheduler = &dev_priv->scheduler;
-+
-+ *lockup = 0;
-+ *idle = 1;
++ unsigned long irq_flags;
+
+ spin_lock_irqsave(&scheduler->lock, irq_flags);
-+
-+ if (scheduler->current_task[PSB_SCENE_ENGINE_TA] != NULL &&
-+ time_after_eq(jiffies, scheduler->ta_end_jiffies)) {
-+ *lockup = 1;
-+ }
-+ if (!*lockup
-+ && (scheduler->current_task[PSB_SCENE_ENGINE_RASTER] != NULL)
-+ && time_after_eq(jiffies, scheduler->raster_end_jiffies)) {
-+ *lockup = 1;
++ if (--scheduler->idle_count == 0) {
++ psb_schedule_ta(dev_priv, scheduler);
++ psb_schedule_raster(dev_priv, scheduler);
+ }
-+ if (!*lockup)
-+ *idle = scheduler->idle;
-+
+ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
+}
+
-+static inline void psb_set_idle(struct psb_scheduler *scheduler)
++int psb_scheduler_idle(struct drm_psb_private *dev_priv)
+{
-+ scheduler->idle =
-+ (scheduler->current_task[PSB_SCENE_ENGINE_RASTER] == NULL) &&
-+ (scheduler->current_task[PSB_SCENE_ENGINE_TA] == NULL);
-+ if (scheduler->idle)
-+ wake_up(&scheduler->idle_queue);
++ struct psb_scheduler *scheduler = &dev_priv->scheduler;
++ unsigned long irq_flags;
++ int ret;
++ spin_lock_irqsave(&scheduler->lock, irq_flags);
++ ret = scheduler->idle_count != 0 && scheduler->idle;
++ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
++ return ret;
+}
+
-+/*
-+ * Call with the scheduler spinlock held.
-+ * Assigns a scene context to either the ta or the rasterizer,
-+ * flushing out other scenes to memory if necessary.
-+ */
++int psb_scheduler_finished(struct drm_psb_private *dev_priv)
++{
++ struct psb_scheduler *scheduler = &dev_priv->scheduler;
++ unsigned long irq_flags;
++ int ret;
++ spin_lock_irqsave(&scheduler->lock, irq_flags);
++ ret = (scheduler->idle &&
++ list_empty(&scheduler->raster_queue) &&
++ list_empty(&scheduler->ta_queue) &&
++ list_empty(&scheduler->hp_raster_queue));
++ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
++ return ret;
++}
+
-+static int psb_set_scene_fire(struct psb_scheduler *scheduler,
-+ struct psb_scene *scene,
-+ int engine, struct psb_task *task)
++static void psb_ta_oom(struct drm_psb_private *dev_priv,
++ struct psb_scheduler *scheduler)
+{
-+ uint32_t flags = 0;
-+ struct psb_hw_scene *hw_scene;
-+ struct drm_device *dev = scene->dev;
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
+
-+ hw_scene = scene->hw_scene;
-+ if (hw_scene && hw_scene->last_scene == scene) {
++ struct psb_task *task = scheduler->current_task[PSB_SCENE_ENGINE_TA];
++ if (!task)
++ return;
+
-+ /*
-+ * Reuse the last hw scene context and delete it from the
-+ * free list.
-+ */
++ if (task->aborting)
++ return;
++ task->aborting = 1;
+
-+ PSB_DEBUG_RENDER("Reusing hw scene %d.\n",
-+ hw_scene->context_number);
-+ if (scene->flags & PSB_SCENE_FLAG_DIRTY) {
++ DRM_INFO("Info: TA out of parameter memory.\n");
+
-+ /*
-+ * No hw context initialization to be done.
-+ */
++ (void)psb_xhw_ta_oom(dev_priv, &task->buf, task->scene->hw_cookie);
++}
+
-+ flags |= PSB_SCENE_FLAG_SETUP_ONLY;
-+ }
++static void psb_ta_oom_reply(struct drm_psb_private *dev_priv,
++ struct psb_scheduler *scheduler)
++{
+
-+ list_del_init(&hw_scene->head);
++ struct psb_task *task = scheduler->current_task[PSB_SCENE_ENGINE_TA];
++ uint32_t flags;
++ if (!task)
++ return;
+
-+ } else {
-+ struct list_head *list;
-+ hw_scene = NULL;
++ psb_xhw_ta_oom_reply(dev_priv, &task->buf,
++ task->scene->hw_cookie,
++ &task->ta_complete_action,
++ &task->raster_complete_action, &flags);
++ task->flags |= flags;
++ task->aborting = 0;
++ psb_dispatch_ta(dev_priv, scheduler, PSB_RF_OOM_REPLY);
++}
+
-+ /*
-+ * Grab a new hw scene context.
-+ */
++static void psb_ta_hw_scene_freed(struct drm_psb_private *dev_priv,
++ struct psb_scheduler *scheduler)
++{
++ DRM_ERROR("TA hw scene freed.\n");
++}
+
-+ list_for_each(list, &scheduler->hw_scenes) {
-+ hw_scene = list_entry(list, struct psb_hw_scene, head);
-+ break;
-+ }
-+ BUG_ON(!hw_scene);
-+ PSB_DEBUG_RENDER("New hw scene %d.\n",
-+ hw_scene->context_number);
++static void psb_vistest_reply(struct drm_psb_private *dev_priv,
++ struct psb_scheduler *scheduler)
++{
++ struct psb_task *task = scheduler->feedback_task;
++ uint8_t *feedback_map;
++ uint32_t add;
++ uint32_t cur;
++ struct drm_psb_vistest *vistest;
++ int i;
+
-+ list_del_init(list);
++ scheduler->feedback_task = NULL;
++ if (!task) {
++ DRM_ERROR("No Poulsbo feedback task.\n");
++ return;
++ }
++ if (!task->feedback.page) {
++ DRM_ERROR("No Poulsbo feedback page.\n");
++ goto out;
+ }
-+ scene->hw_scene = hw_scene;
-+ hw_scene->last_scene = scene;
+
-+ flags |= PSB_SCENE_FLAG_SETUP;
++ if (in_irq())
++ feedback_map = kmap_atomic(task->feedback.page, KM_IRQ0);
++ else
++ feedback_map = kmap_atomic(task->feedback.page, KM_USER0);
+
+ /*
-+ * Switch context and setup the engine.
++ * Loop over all requested vistest components here.
++ * Only one (vistest) currently.
+ */
+
-+ return psb_xhw_scene_bind_fire(dev_priv,
-+ &task->buf,
-+ task->flags,
-+ hw_scene->context_number,
-+ scene->hw_cookie,
-+ task->oom_cmds,
-+ task->oom_cmd_size,
-+ scene->hw_data->offset,
-+ engine, flags | scene->flags);
-+}
++ vistest = (struct drm_psb_vistest *)
++ (feedback_map + task->feedback.offset);
+
-+static inline void psb_report_fence(struct psb_scheduler *scheduler,
-+ uint32_t class,
-+ uint32_t sequence,
-+ uint32_t type, int call_handler)
-+{
-+ struct psb_scheduler_seq *seq = &scheduler->seq[type];
++ for (i = 0; i < PSB_HW_FEEDBACK_SIZE; ++i) {
++ add = task->buf.arg.arg.feedback[i];
++ cur = vistest->vt[i];
+
-+ seq->sequence = sequence;
-+ seq->reported = 0;
-+ if (call_handler)
-+ psb_fence_handler(scheduler->dev, class);
-+}
++ /*
++ * Vistest saturates.
++ */
+
-+static void psb_schedule_raster(struct drm_psb_private *dev_priv,
-+ struct psb_scheduler *scheduler);
++ vistest->vt[i] = (cur + add < cur) ? ~0 : cur + add;
++ }
++ if (in_irq())
++ kunmap_atomic(feedback_map, KM_IRQ0);
++ else
++ kunmap_atomic(feedback_map, KM_USER0);
++ out:
++ psb_report_fence(scheduler, task->engine, task->sequence,
++ _PSB_FENCE_FEEDBACK_SHIFT, 1);
+
-+static void psb_schedule_ta(struct drm_psb_private *dev_priv,
-+ struct psb_scheduler *scheduler)
++ if (list_empty(&task->head)) {
++ list_add_tail(&task->head, &scheduler->task_done_queue);
++ schedule_delayed_work(&scheduler->wq, 1);
++ } else
++ psb_schedule_ta(dev_priv, scheduler);
++}
++
++static void psb_ta_fire_reply(struct drm_psb_private *dev_priv,
++ struct psb_scheduler *scheduler)
+{
-+ struct psb_task *task = NULL;
-+ struct list_head *list, *next;
-+ int pushed_raster_task = 0;
++ struct psb_task *task = scheduler->current_task[PSB_SCENE_ENGINE_TA];
+
-+ PSB_DEBUG_RENDER("schedule ta\n");
++ psb_xhw_fire_reply(dev_priv, &task->buf, task->scene->hw_cookie);
+
-+ if (scheduler->idle_count != 0)
-+ return;
++ psb_dispatch_ta(dev_priv, scheduler, PSB_RF_FIRE_TA);
++}
+
-+ if (scheduler->current_task[PSB_SCENE_ENGINE_TA] != NULL)
-+ return;
++static void psb_raster_fire_reply(struct drm_psb_private *dev_priv,
++ struct psb_scheduler *scheduler)
++{
++ struct psb_task *task =
++ scheduler->current_task[PSB_SCENE_ENGINE_RASTER];
++ uint32_t reply_flags;
+
-+ if (scheduler->ta_state)
++ if (!task) {
++ DRM_ERROR("Null task.\n");
+ return;
-+
-+ /*
-+ * Skip the ta stage for rasterization-only
-+ * tasks. They arrive here to make sure we're rasterizing
-+ * tasks in the correct order.
-+ */
-+
-+ list_for_each_safe(list, next, &scheduler->ta_queue) {
-+ task = list_entry(list, struct psb_task, head);
-+ if (task->task_type != psb_raster_task)
-+ break;
-+
-+ list_del_init(list);
-+ list_add_tail(list, &scheduler->raster_queue);
-+ psb_report_fence(scheduler, task->engine, task->sequence,
-+ _PSB_FENCE_TA_DONE_SHIFT, 1);
-+ task = NULL;
-+ pushed_raster_task = 1;
+ }
+
-+ if (pushed_raster_task)
-+ psb_schedule_raster(dev_priv, scheduler);
-+
-+ if (!task)
-+ return;
-+
-+ /*
-+ * Still waiting for a vistest?
-+ */
-+
-+ if (scheduler->feedback_task == task)
-+ return;
++ task->raster_complete_action = task->buf.arg.arg.sb.rca;
++ psb_xhw_fire_reply(dev_priv, &task->buf, task->scene->hw_cookie);
+
-+#ifdef ONLY_ONE_JOB_IN_RASTER_QUEUE
++ reply_flags = PSB_RF_FIRE_RASTER;
++ if (task->raster_complete_action == PSB_RASTER)
++ reply_flags |= PSB_RF_DEALLOC;
+
-+ /*
-+ * Block ta from trying to use both hardware contexts
-+ * without the rasterizer starting to render from one of them.
-+ */
++ psb_dispatch_raster(dev_priv, scheduler, reply_flags);
++}
+
-+ if (!list_empty(&scheduler->raster_queue)) {
-+ return;
-+ }
-+#endif
++static int psb_user_interrupt(struct drm_psb_private *dev_priv,
++ struct psb_scheduler *scheduler)
++{
++ uint32_t type;
++ int ret;
++ unsigned long irq_flags;
+
-+#ifdef PSB_BLOCK_OVERLAP
+ /*
-+ * Make sure rasterizer isn't doing anything.
++ * Xhw cannot write directly to the comm page, so
++ * do it here. Firmware would have written directly.
+ */
-+ if (scheduler->current_task[PSB_SCENE_ENGINE_RASTER] != NULL)
-+ return;
-+#endif
-+ if (list_empty(&scheduler->hw_scenes))
-+ return;
-+
-+#ifdef FIX_TG_16
-+ if (psb_check_2d_idle(dev_priv))
-+ return;
-+#endif
+
-+ list_del_init(&task->head);
-+ if (task->flags & PSB_FIRE_FLAG_XHW_OOM)
-+ scheduler->ta_state = 1;
++ ret = psb_xhw_handler(dev_priv);
++ if (unlikely(ret))
++ return ret;
+
-+ scheduler->current_task[PSB_SCENE_ENGINE_TA] = task;
-+ scheduler->idle = 0;
-+ scheduler->ta_end_jiffies = jiffies + PSB_TA_TIMEOUT;
++ spin_lock_irqsave(&dev_priv->xhw_lock, irq_flags);
++ type = dev_priv->comm[PSB_COMM_USER_IRQ];
++ dev_priv->comm[PSB_COMM_USER_IRQ] = 0;
++ if (dev_priv->comm[PSB_COMM_USER_IRQ_LOST]) {
++ dev_priv->comm[PSB_COMM_USER_IRQ_LOST] = 0;
++ DRM_ERROR("Lost Poulsbo hardware event.\n");
++ }
++ spin_unlock_irqrestore(&dev_priv->xhw_lock, irq_flags);
+
-+ task->reply_flags = (task->flags & PSB_FIRE_FLAG_XHW_OOM) ?
-+ 0x00000000 : PSB_RF_FIRE_TA;
++ if (type == 0)
++ return 0;
+
-+ (void)psb_reg_submit(dev_priv, task->ta_cmds, task->ta_cmd_size);
-+ psb_set_scene_fire(scheduler, task->scene, PSB_SCENE_ENGINE_TA, task);
-+ psb_schedule_watchdog(dev_priv);
++ switch (type) {
++ case PSB_UIRQ_VISTEST:
++ psb_vistest_reply(dev_priv, scheduler);
++ break;
++ case PSB_UIRQ_OOM_REPLY:
++ psb_ta_oom_reply(dev_priv, scheduler);
++ break;
++ case PSB_UIRQ_FIRE_TA_REPLY:
++ psb_ta_fire_reply(dev_priv, scheduler);
++ break;
++ case PSB_UIRQ_FIRE_RASTER_REPLY:
++ psb_raster_fire_reply(dev_priv, scheduler);
++ break;
++ default:
++ DRM_ERROR("Unknown Poulsbo hardware event. %d\n", type);
++ }
++ return 0;
+}
+
-+static int psb_fire_raster(struct psb_scheduler *scheduler,
-+ struct psb_task *task)
++int psb_forced_user_interrupt(struct drm_psb_private *dev_priv)
+{
-+ struct drm_device *dev = scheduler->dev;
-+ struct drm_psb_private *dev_priv = (struct drm_psb_private *)
-+ dev->dev_private;
-+
-+ PSB_DEBUG_RENDER("Fire raster %d\n", task->sequence);
++ struct psb_scheduler *scheduler = &dev_priv->scheduler;
++ unsigned long irq_flags;
++ int ret;
+
-+ return psb_xhw_fire_raster(dev_priv, &task->buf, task->flags);
++ spin_lock_irqsave(&scheduler->lock, irq_flags);
++ ret = psb_user_interrupt(dev_priv, scheduler);
++ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
++ return ret;
+}
+
-+/*
-+ * Take the first rasterization task from the hp raster queue or from the
-+ * raster queue and fire the rasterizer.
-+ */
-+
-+static void psb_schedule_raster(struct drm_psb_private *dev_priv,
-+ struct psb_scheduler *scheduler)
++static void psb_dispatch_ta(struct drm_psb_private *dev_priv,
++ struct psb_scheduler *scheduler,
++ uint32_t reply_flag)
+{
-+ struct psb_task *task;
-+ struct list_head *list;
++ struct psb_task *task = scheduler->current_task[PSB_SCENE_ENGINE_TA];
++ uint32_t flags;
++ uint32_t mask;
+
-+ if (scheduler->idle_count != 0)
-+ return;
++ task->reply_flags |= reply_flag;
++ flags = task->reply_flags;
++ mask = PSB_RF_FIRE_TA;
+
-+ if (scheduler->current_task[PSB_SCENE_ENGINE_RASTER] != NULL) {
-+ PSB_DEBUG_RENDER("Raster busy.\n");
-+ return;
-+ }
-+#ifdef PSB_BLOCK_OVERLAP
-+ if (scheduler->current_task[PSB_SCENE_ENGINE_TA] != NULL) {
-+ PSB_DEBUG_RENDER("TA busy.\n");
++ if (!(flags & mask))
+ return;
-+ }
-+#endif
+
-+ if (!list_empty(&scheduler->hp_raster_queue))
-+ list = scheduler->hp_raster_queue.next;
-+ else if (!list_empty(&scheduler->raster_queue))
-+ list = scheduler->raster_queue.next;
-+ else {
-+ PSB_DEBUG_RENDER("Nothing in list\n");
-+ return;
++ mask = PSB_RF_TA_DONE;
++ if ((flags & mask) == mask) {
++ task->reply_flags &= ~mask;
++ psb_ta_done(dev_priv, scheduler);
+ }
+
-+ task = list_entry(list, struct psb_task, head);
++ mask = PSB_RF_OOM;
++ if ((flags & mask) == mask) {
++ task->reply_flags &= ~mask;
++ psb_ta_oom(dev_priv, scheduler);
++ }
+
-+ /*
-+ * Sometimes changing ZLS format requires an ISP reset.
-+ * Doesn't seem to consume too much time.
-+ */
++ mask = (PSB_RF_OOM_REPLY | PSB_RF_TERMINATE);
++ if ((flags & mask) == mask) {
++ task->reply_flags &= ~mask;
++ psb_ta_done(dev_priv, scheduler);
++ }
++}
+
-+ if (task->scene)
-+ PSB_WSGX32(_PSB_CS_RESET_ISP_RESET, PSB_CR_SOFT_RESET);
++static void psb_dispatch_raster(struct drm_psb_private *dev_priv,
++ struct psb_scheduler *scheduler,
++ uint32_t reply_flag)
++{
++ struct psb_task *task =
++ scheduler->current_task[PSB_SCENE_ENGINE_RASTER];
++ uint32_t flags;
++ uint32_t mask;
+
-+ scheduler->current_task[PSB_SCENE_ENGINE_RASTER] = task;
++ task->reply_flags |= reply_flag;
++ flags = task->reply_flags;
++ mask = PSB_RF_FIRE_RASTER;
+
-+ list_del_init(list);
-+ scheduler->idle = 0;
-+ scheduler->raster_end_jiffies = jiffies + PSB_RASTER_TIMEOUT;
-+ scheduler->total_raster_jiffies = 0;
++ if (!(flags & mask))
++ return;
+
-+ if (task->scene)
-+ PSB_WSGX32(0, PSB_CR_SOFT_RESET);
++ /*
++ * For rasterizer-only tasks, don't report fence done here,
++ * as this is time consuming and the rasterizer wants a new
++ * task immediately. For other tasks, the hardware is probably
++ * still busy deallocating TA memory, so we can report
++ * fence done in parallel.
++ */
+
-+ (void)psb_reg_submit(dev_priv, task->raster_cmds,
-+ task->raster_cmd_size);
++ if (task->raster_complete_action == PSB_RETURN &&
++ (reply_flag & PSB_RF_RASTER_DONE) && task->scene != NULL) {
++ psb_report_fence(scheduler, task->engine, task->sequence,
++ _PSB_FENCE_RASTER_DONE_SHIFT, 1);
++ }
+
-+ if (task->scene) {
-+ task->reply_flags = (task->flags & PSB_FIRE_FLAG_XHW_OOM) ?
-+ 0x00000000 : PSB_RF_FIRE_RASTER;
-+ psb_set_scene_fire(scheduler,
-+ task->scene, PSB_SCENE_ENGINE_RASTER, task);
-+ } else {
-+ task->reply_flags = PSB_RF_DEALLOC | PSB_RF_FIRE_RASTER;
-+ psb_fire_raster(scheduler, task);
++ mask = PSB_RF_RASTER_DONE | PSB_RF_DEALLOC;
++ if ((flags & mask) == mask) {
++ task->reply_flags &= ~mask;
++ psb_raster_done(dev_priv, scheduler);
+ }
-+ psb_schedule_watchdog(dev_priv);
+}
+
-+int psb_extend_raster_timeout(struct drm_psb_private *dev_priv)
++void psb_scheduler_handler(struct drm_psb_private *dev_priv, uint32_t status)
+{
+ struct psb_scheduler *scheduler = &dev_priv->scheduler;
-+ unsigned long irq_flags;
-+ int ret;
+
-+ spin_lock_irqsave(&scheduler->lock, irq_flags);
-+ scheduler->total_raster_jiffies +=
-+ jiffies - scheduler->raster_end_jiffies + PSB_RASTER_TIMEOUT;
-+ scheduler->raster_end_jiffies = jiffies + PSB_RASTER_TIMEOUT;
-+ ret = (scheduler->total_raster_jiffies > PSB_ALLOWED_RASTER_RUNTIME) ?
-+ -EBUSY : 0;
-+ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
-+ return ret;
-+}
++ spin_lock(&scheduler->lock);
+
-+/*
-+ * TA done handler.
-+ */
++ if (status & _PSB_CE_PIXELBE_END_RENDER) {
++ psb_dispatch_raster(dev_priv, scheduler, PSB_RF_RASTER_DONE);
++ }
++ if (status & _PSB_CE_DPM_3D_MEM_FREE) {
++ psb_dispatch_raster(dev_priv, scheduler, PSB_RF_DEALLOC);
++ }
++ if (status & _PSB_CE_TA_FINISHED) {
++ psb_dispatch_ta(dev_priv, scheduler, PSB_RF_TA_DONE);
++ }
++ if (status & _PSB_CE_TA_TERMINATE) {
++ psb_dispatch_ta(dev_priv, scheduler, PSB_RF_TERMINATE);
++ }
++ if (status & (_PSB_CE_DPM_REACHED_MEM_THRESH |
++ _PSB_CE_DPM_OUT_OF_MEMORY_GBL |
++ _PSB_CE_DPM_OUT_OF_MEMORY_MT)) {
++ psb_dispatch_ta(dev_priv, scheduler, PSB_RF_OOM);
++ }
++ if (status & _PSB_CE_DPM_TA_MEM_FREE) {
++ psb_ta_hw_scene_freed(dev_priv, scheduler);
++ }
++ if (status & _PSB_CE_SW_EVENT) {
++ psb_user_interrupt(dev_priv, scheduler);
++ }
++ spin_unlock(&scheduler->lock);
++}
+
-+static void psb_ta_done(struct drm_psb_private *dev_priv,
-+ struct psb_scheduler *scheduler)
++static void psb_free_task_wq(struct work_struct *work)
+{
-+ struct psb_task *task = scheduler->current_task[PSB_SCENE_ENGINE_TA];
-+ struct psb_scene *scene = task->scene;
-+
-+ PSB_DEBUG_RENDER("TA done %u\n", task->sequence);
-+
-+ switch (task->ta_complete_action) {
-+ case PSB_RASTER_BLOCK:
-+ scheduler->ta_state = 1;
-+ scene->flags |=
-+ (PSB_SCENE_FLAG_DIRTY | PSB_SCENE_FLAG_COMPLETE);
-+ list_add_tail(&task->head, &scheduler->raster_queue);
-+ break;
-+ case PSB_RASTER:
-+ scene->flags |=
-+ (PSB_SCENE_FLAG_DIRTY | PSB_SCENE_FLAG_COMPLETE);
-+ list_add_tail(&task->head, &scheduler->raster_queue);
-+ break;
-+ case PSB_RETURN:
-+ scheduler->ta_state = 0;
-+ scene->flags |= PSB_SCENE_FLAG_DIRTY;
-+ list_add_tail(&scene->hw_scene->head, &scheduler->hw_scenes);
++ struct psb_scheduler *scheduler =
++ container_of(work, struct psb_scheduler, wq.work);
+
-+ break;
-+ }
++ struct drm_device *dev = scheduler->dev;
++ struct list_head *list, *next;
++ unsigned long irq_flags;
++ struct psb_task *task;
+
-+ scheduler->current_task[PSB_SCENE_ENGINE_TA] = NULL;
++ if (!mutex_trylock(&scheduler->task_wq_mutex))
++ return;
+
-+#ifdef FIX_TG_16
-+ psb_2d_atomic_unlock(dev_priv);
-+#endif
++ spin_lock_irqsave(&scheduler->lock, irq_flags);
++ list_for_each_safe(list, next, &scheduler->task_done_queue) {
++ task = list_entry(list, struct psb_task, head);
++ list_del_init(list);
++ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
+
-+ if (task->ta_complete_action != PSB_RASTER_BLOCK)
-+ psb_report_fence(scheduler, task->engine, task->sequence,
-+ _PSB_FENCE_TA_DONE_SHIFT, 1);
++ PSB_DEBUG_RENDER("Checking Task %d: Scene 0x%08lx, "
++ "Feedback bo 0x%08lx, done %d\n",
++ task->sequence, (unsigned long)task->scene,
++ (unsigned long)task->feedback.bo,
++ atomic_read(&task->buf.done));
+
-+ psb_schedule_raster(dev_priv, scheduler);
-+ psb_schedule_ta(dev_priv, scheduler);
-+ psb_set_idle(scheduler);
++ if (task->scene) {
++ mutex_lock(&dev->struct_mutex);
++ PSB_DEBUG_RENDER("Unref scene %d\n", task->sequence);
++ psb_scene_unref_devlocked(&task->scene);
++ if (task->feedback.bo) {
++ PSB_DEBUG_RENDER("Unref feedback bo %d\n",
++ task->sequence);
++ drm_bo_usage_deref_locked(&task->feedback.bo);
++ }
++ mutex_unlock(&dev->struct_mutex);
++ }
+
-+ if (task->ta_complete_action != PSB_RETURN)
-+ return;
++ if (atomic_read(&task->buf.done)) {
++ PSB_DEBUG_RENDER("Deleting task %d\n", task->sequence);
++ drm_free(task, sizeof(*task), DRM_MEM_DRIVER);
++ task = NULL;
++ }
++ spin_lock_irqsave(&scheduler->lock, irq_flags);
++ if (task != NULL)
++ list_add(list, &scheduler->task_done_queue);
++ }
++ if (!list_empty(&scheduler->task_done_queue)) {
++ PSB_DEBUG_RENDER("Rescheduling wq\n");
++ schedule_delayed_work(&scheduler->wq, 1);
++ }
++ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
+
-+ list_add_tail(&task->head, &scheduler->task_done_queue);
-+ schedule_delayed_work(&scheduler->wq, 1);
++ mutex_unlock(&scheduler->task_wq_mutex);
+}
+
+/*
-+ * Rasterizer done handler.
++ * Check if any of the tasks in the queues is using a scene.
++ * In that case we know the TA memory buffer objects are
++ * fenced and will not be evicted until that fence is signaled.
+ */
+
-+static void psb_raster_done(struct drm_psb_private *dev_priv,
-+ struct psb_scheduler *scheduler)
++void psb_scheduler_ta_mem_check(struct drm_psb_private *dev_priv)
+{
-+ struct psb_task *task =
-+ scheduler->current_task[PSB_SCENE_ENGINE_RASTER];
-+ struct psb_scene *scene = task->scene;
-+ uint32_t complete_action = task->raster_complete_action;
++ struct psb_scheduler *scheduler = &dev_priv->scheduler;
++ unsigned long irq_flags;
++ struct psb_task *task;
++ struct psb_task *next_task;
+
-+ PSB_DEBUG_RENDER("Raster done %u\n", task->sequence);
++ dev_priv->force_ta_mem_load = 1;
++ spin_lock_irqsave(&scheduler->lock, irq_flags);
++ list_for_each_entry_safe(task, next_task, &scheduler->ta_queue, head) {
++ if (task->scene) {
++ dev_priv->force_ta_mem_load = 0;
++ break;
++ }
++ }
++ list_for_each_entry_safe(task, next_task, &scheduler->raster_queue,
++ head) {
++ if (task->scene) {
++ dev_priv->force_ta_mem_load = 0;
++ break;
++ }
++ }
++ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
++}
+
-+ scheduler->current_task[PSB_SCENE_ENGINE_RASTER] = NULL;
++void psb_scheduler_reset(struct drm_psb_private *dev_priv, int error_condition)
++{
++ struct psb_scheduler *scheduler = &dev_priv->scheduler;
++ unsigned long wait_jiffies;
++ unsigned long cur_jiffies;
++ struct psb_task *task;
++ struct psb_task *next_task;
++ unsigned long irq_flags;
+
-+ if (complete_action != PSB_RASTER)
-+ psb_schedule_raster(dev_priv, scheduler);
++ psb_scheduler_pause(dev_priv);
++ if (!psb_scheduler_idle(dev_priv)) {
++ spin_lock_irqsave(&scheduler->lock, irq_flags);
+
-+ if (scene) {
-+ if (task->feedback.page) {
-+ if (unlikely(scheduler->feedback_task)) {
-+ /*
-+ * This should never happen, since the previous
-+ * feedback query will return before the next
-+ * raster task is fired.
-+ */
-+ DRM_ERROR("Feedback task busy.\n");
-+ }
-+ scheduler->feedback_task = task;
-+ psb_xhw_vistest(dev_priv, &task->buf);
-+ }
-+ switch (complete_action) {
-+ case PSB_RETURN:
-+ scene->flags &=
-+ ~(PSB_SCENE_FLAG_DIRTY | PSB_SCENE_FLAG_COMPLETE);
-+ list_add_tail(&scene->hw_scene->head,
-+ &scheduler->hw_scenes);
-+ psb_report_fence(scheduler, task->engine,
-+ task->sequence,
-+ _PSB_FENCE_SCENE_DONE_SHIFT, 1);
-+ if (task->flags & PSB_FIRE_FLAG_XHW_OOM) {
-+ scheduler->ta_state = 0;
-+ }
-+ break;
-+ case PSB_RASTER:
-+ list_add(&task->head, &scheduler->raster_queue);
-+ task->raster_complete_action = PSB_RETURN;
-+ psb_schedule_raster(dev_priv, scheduler);
-+ break;
-+ case PSB_TA:
-+ list_add(&task->head, &scheduler->ta_queue);
-+ scheduler->ta_state = 0;
-+ task->raster_complete_action = PSB_RETURN;
-+ task->ta_complete_action = PSB_RASTER;
-+ break;
++ cur_jiffies = jiffies;
++ wait_jiffies = cur_jiffies;
++ if (scheduler->current_task[PSB_SCENE_ENGINE_TA] &&
++ time_after_eq(scheduler->ta_end_jiffies, wait_jiffies))
++ wait_jiffies = scheduler->ta_end_jiffies;
++ if (scheduler->current_task[PSB_SCENE_ENGINE_RASTER] &&
++ time_after_eq(scheduler->raster_end_jiffies, wait_jiffies))
++ wait_jiffies = scheduler->raster_end_jiffies;
+
-+ }
++ wait_jiffies -= cur_jiffies;
++ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
++
++ (void)wait_event_timeout(scheduler->idle_queue,
++ psb_scheduler_idle(dev_priv),
++ wait_jiffies);
+ }
-+ psb_schedule_ta(dev_priv, scheduler);
-+ psb_set_idle(scheduler);
+
-+ if (complete_action == PSB_RETURN) {
-+ if (task->scene == NULL) {
-+ psb_report_fence(scheduler, task->engine,
-+ task->sequence,
-+ _PSB_FENCE_RASTER_DONE_SHIFT, 1);
++ if (!psb_scheduler_idle(dev_priv)) {
++ spin_lock_irqsave(&scheduler->lock, irq_flags);
++ task = scheduler->current_task[PSB_SCENE_ENGINE_RASTER];
++ if (task) {
++ DRM_ERROR("Detected Poulsbo rasterizer lockup.\n");
++ if (task->engine == PSB_ENGINE_HPRAST) {
++ psb_fence_error(scheduler->dev,
++ PSB_ENGINE_HPRAST,
++ task->sequence,
++ _PSB_FENCE_TYPE_RASTER_DONE,
++ error_condition);
++
++ list_del(&task->head);
++ psb_xhw_clean_buf(dev_priv, &task->buf);
++ list_add_tail(&task->head,
++ &scheduler->task_done_queue);
++ } else {
++ list_add(&task->head, &scheduler->raster_queue);
++ }
+ }
-+ if (!task->feedback.page) {
-+ list_add_tail(&task->head, &scheduler->task_done_queue);
-+ schedule_delayed_work(&scheduler->wq, 1);
++ scheduler->current_task[PSB_SCENE_ENGINE_RASTER] = NULL;
++ task = scheduler->current_task[PSB_SCENE_ENGINE_TA];
++ if (task) {
++ DRM_ERROR("Detected Poulsbo ta lockup.\n");
++ list_add_tail(&task->head, &scheduler->raster_queue);
++#ifdef FIX_TG_16
++ psb_2d_atomic_unlock(dev_priv);
++#endif
+ }
++ scheduler->current_task[PSB_SCENE_ENGINE_TA] = NULL;
++ scheduler->ta_state = 0;
++
++#ifdef FIX_TG_16
++ atomic_set(&dev_priv->ta_wait_2d, 0);
++ atomic_set(&dev_priv->ta_wait_2d_irq, 0);
++ wake_up(&dev_priv->queue_2d);
++#endif
++ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
+ }
-+}
+
-+void psb_scheduler_pause(struct drm_psb_private *dev_priv)
-+{
-+ struct psb_scheduler *scheduler = &dev_priv->scheduler;
-+ unsigned long irq_flags;
++ /*
++ * Empty raster queue.
++ */
+
+ spin_lock_irqsave(&scheduler->lock, irq_flags);
-+ scheduler->idle_count++;
-+ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
-+}
++ list_for_each_entry_safe(task, next_task, &scheduler->raster_queue,
++ head) {
++ struct psb_scene *scene = task->scene;
+
-+void psb_scheduler_restart(struct drm_psb_private *dev_priv)
-+{
-+ struct psb_scheduler *scheduler = &dev_priv->scheduler;
-+ unsigned long irq_flags;
++ psb_fence_error(scheduler->dev,
++ task->engine,
++ task->sequence,
++ _PSB_FENCE_TYPE_TA_DONE |
++ _PSB_FENCE_TYPE_RASTER_DONE |
++ _PSB_FENCE_TYPE_SCENE_DONE |
++ _PSB_FENCE_TYPE_FEEDBACK, error_condition);
++ if (scene) {
++ scene->flags = 0;
++ if (scene->hw_scene) {
++ list_add_tail(&scene->hw_scene->head,
++ &scheduler->hw_scenes);
++ scene->hw_scene = NULL;
++ }
++ }
+
-+ spin_lock_irqsave(&scheduler->lock, irq_flags);
-+ if (--scheduler->idle_count == 0) {
-+ psb_schedule_ta(dev_priv, scheduler);
-+ psb_schedule_raster(dev_priv, scheduler);
++ psb_xhw_clean_buf(dev_priv, &task->buf);
++ list_del(&task->head);
++ list_add_tail(&task->head, &scheduler->task_done_queue);
+ }
-+ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
-+}
+
-+int psb_scheduler_idle(struct drm_psb_private *dev_priv)
-+{
-+ struct psb_scheduler *scheduler = &dev_priv->scheduler;
-+ unsigned long irq_flags;
-+ int ret;
-+ spin_lock_irqsave(&scheduler->lock, irq_flags);
-+ ret = scheduler->idle_count != 0 && scheduler->idle;
-+ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
-+ return ret;
-+}
++ schedule_delayed_work(&scheduler->wq, 1);
++ scheduler->idle = 1;
++ wake_up(&scheduler->idle_queue);
+
-+int psb_scheduler_finished(struct drm_psb_private *dev_priv)
-+{
-+ struct psb_scheduler *scheduler = &dev_priv->scheduler;
-+ unsigned long irq_flags;
-+ int ret;
-+ spin_lock_irqsave(&scheduler->lock, irq_flags);
-+ ret = (scheduler->idle &&
-+ list_empty(&scheduler->raster_queue) &&
-+ list_empty(&scheduler->ta_queue) &&
-+ list_empty(&scheduler->hp_raster_queue));
+ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
-+ return ret;
++ psb_scheduler_restart(dev_priv);
++
+}
+
-+static void psb_ta_oom(struct drm_psb_private *dev_priv,
-+ struct psb_scheduler *scheduler)
++int psb_scheduler_init(struct drm_device *dev, struct psb_scheduler *scheduler)
+{
++ struct psb_hw_scene *hw_scene;
++ int i;
+
-+ struct psb_task *task = scheduler->current_task[PSB_SCENE_ENGINE_TA];
-+ if (!task)
-+ return;
++ memset(scheduler, 0, sizeof(*scheduler));
++ scheduler->dev = dev;
++ mutex_init(&scheduler->task_wq_mutex);
++ scheduler->lock = SPIN_LOCK_UNLOCKED;
++ scheduler->idle = 1;
+
-+ if (task->aborting)
-+ return;
-+ task->aborting = 1;
++ INIT_LIST_HEAD(&scheduler->ta_queue);
++ INIT_LIST_HEAD(&scheduler->raster_queue);
++ INIT_LIST_HEAD(&scheduler->hp_raster_queue);
++ INIT_LIST_HEAD(&scheduler->hw_scenes);
++ INIT_LIST_HEAD(&scheduler->task_done_queue);
++ INIT_DELAYED_WORK(&scheduler->wq, &psb_free_task_wq);
++ init_waitqueue_head(&scheduler->idle_queue);
+
-+ DRM_INFO("Info: TA out of parameter memory.\n");
++ for (i = 0; i < PSB_NUM_HW_SCENES; ++i) {
++ hw_scene = &scheduler->hs[i];
++ hw_scene->context_number = i;
++ list_add_tail(&hw_scene->head, &scheduler->hw_scenes);
++ }
+
-+ (void)psb_xhw_ta_oom(dev_priv, &task->buf, task->scene->hw_cookie);
++ for (i = 0; i < _PSB_ENGINE_TA_FENCE_TYPES; ++i) {
++ scheduler->seq[i].reported = 0;
++ }
++
++ return 0;
+}
+
-+static void psb_ta_oom_reply(struct drm_psb_private *dev_priv,
-+ struct psb_scheduler *scheduler)
-+{
++/*
++ * Scene references maintained by the scheduler are not refcounted.
++ * Remove all references to a particular scene here.
++ */
+
-+ struct psb_task *task = scheduler->current_task[PSB_SCENE_ENGINE_TA];
-+ uint32_t flags;
-+ if (!task)
-+ return;
++void psb_scheduler_remove_scene_refs(struct psb_scene *scene)
++{
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)scene->dev->dev_private;
++ struct psb_scheduler *scheduler = &dev_priv->scheduler;
++ struct psb_hw_scene *hw_scene;
++ unsigned long irq_flags;
++ unsigned int i;
+
-+ psb_xhw_ta_oom_reply(dev_priv, &task->buf,
-+ task->scene->hw_cookie,
-+ &task->ta_complete_action,
-+ &task->raster_complete_action, &flags);
-+ task->flags |= flags;
-+ task->aborting = 0;
-+ psb_dispatch_ta(dev_priv, scheduler, PSB_RF_OOM_REPLY);
++ spin_lock_irqsave(&scheduler->lock, irq_flags);
++ for (i = 0; i < PSB_NUM_HW_SCENES; ++i) {
++ hw_scene = &scheduler->hs[i];
++ if (hw_scene->last_scene == scene) {
++ BUG_ON(list_empty(&hw_scene->head));
++ hw_scene->last_scene = NULL;
++ }
++ }
++ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
+}
+
-+static void psb_ta_hw_scene_freed(struct drm_psb_private *dev_priv,
-+ struct psb_scheduler *scheduler)
++void psb_scheduler_takedown(struct psb_scheduler *scheduler)
+{
-+ DRM_ERROR("TA hw scene freed.\n");
++ flush_scheduled_work();
+}
+
-+static void psb_vistest_reply(struct drm_psb_private *dev_priv,
-+ struct psb_scheduler *scheduler)
++static int psb_setup_task_devlocked(struct drm_device *dev,
++ struct drm_psb_cmdbuf_arg *arg,
++ struct drm_buffer_object *raster_cmd_buffer,
++ struct drm_buffer_object *ta_cmd_buffer,
++ struct drm_buffer_object *oom_cmd_buffer,
++ struct psb_scene *scene,
++ enum psb_task_type task_type,
++ uint32_t engine,
++ uint32_t flags, struct psb_task **task_p)
+{
-+ struct psb_task *task = scheduler->feedback_task;
-+ uint8_t *feedback_map;
-+ uint32_t add;
-+ uint32_t cur;
-+ struct drm_psb_vistest *vistest;
-+ int i;
++ struct psb_task *task;
++ int ret;
+
-+ scheduler->feedback_task = NULL;
-+ if (!task) {
-+ DRM_ERROR("No Poulsbo feedback task.\n");
-+ return;
-+ }
-+ if (!task->feedback.page) {
-+ DRM_ERROR("No Poulsbo feedback page.\n");
-+ goto out;
++ if (ta_cmd_buffer && arg->ta_size > PSB_MAX_TA_CMDS) {
++ DRM_ERROR("Too many ta cmds %d.\n", arg->ta_size);
++ return -EINVAL;
++ }
++ if (raster_cmd_buffer && arg->cmdbuf_size > PSB_MAX_RASTER_CMDS) {
++ DRM_ERROR("Too many raster cmds %d.\n", arg->cmdbuf_size);
++ return -EINVAL;
++ }
++ if (oom_cmd_buffer && arg->oom_size > PSB_MAX_OOM_CMDS) {
++ DRM_ERROR("Too many raster cmds %d.\n", arg->oom_size);
++ return -EINVAL;
+ }
+
-+ if (in_irq())
-+ feedback_map = kmap_atomic(task->feedback.page, KM_IRQ0);
-+ else
-+ feedback_map = kmap_atomic(task->feedback.page, KM_USER0);
-+
-+ /*
-+ * Loop over all requested vistest components here.
-+ * Only one (vistest) currently.
-+ */
-+
-+ vistest = (struct drm_psb_vistest *)
-+ (feedback_map + task->feedback.offset);
-+
-+ for (i = 0; i < PSB_HW_FEEDBACK_SIZE; ++i) {
-+ add = task->buf.arg.arg.feedback[i];
-+ cur = vistest->vt[i];
-+
-+ /*
-+ * Vistest saturates.
-+ */
++ task = drm_calloc(1, sizeof(*task), DRM_MEM_DRIVER);
++ if (!task)
++ return -ENOMEM;
+
-+ vistest->vt[i] = (cur + add < cur) ? ~0 : cur + add;
++ atomic_set(&task->buf.done, 1);
++ task->engine = engine;
++ INIT_LIST_HEAD(&task->head);
++ INIT_LIST_HEAD(&task->buf.head);
++ if (ta_cmd_buffer && arg->ta_size != 0) {
++ task->ta_cmd_size = arg->ta_size;
++ ret = psb_submit_copy_cmdbuf(dev, ta_cmd_buffer,
++ arg->ta_offset,
++ arg->ta_size,
++ PSB_ENGINE_TA, task->ta_cmds);
++ if (ret)
++ goto out_err;
+ }
-+ if (in_irq())
-+ kunmap_atomic(feedback_map, KM_IRQ0);
-+ else
-+ kunmap_atomic(feedback_map, KM_USER0);
-+ out:
-+ psb_report_fence(scheduler, task->engine, task->sequence,
-+ _PSB_FENCE_FEEDBACK_SHIFT, 1);
++ if (raster_cmd_buffer) {
++ task->raster_cmd_size = arg->cmdbuf_size;
++ ret = psb_submit_copy_cmdbuf(dev, raster_cmd_buffer,
++ arg->cmdbuf_offset,
++ arg->cmdbuf_size,
++ PSB_ENGINE_TA, task->raster_cmds);
++ if (ret)
++ goto out_err;
++ }
++ if (oom_cmd_buffer && arg->oom_size != 0) {
++ task->oom_cmd_size = arg->oom_size;
++ ret = psb_submit_copy_cmdbuf(dev, oom_cmd_buffer,
++ arg->oom_offset,
++ arg->oom_size,
++ PSB_ENGINE_TA, task->oom_cmds);
++ if (ret)
++ goto out_err;
++ }
++ task->task_type = task_type;
++ task->flags = flags;
++ if (scene)
++ task->scene = psb_scene_ref(scene);
+
-+ if (list_empty(&task->head)) {
-+ list_add_tail(&task->head, &scheduler->task_done_queue);
-+ schedule_delayed_work(&scheduler->wq, 1);
-+ } else
-+ psb_schedule_ta(dev_priv, scheduler);
++ *task_p = task;
++ return 0;
++ out_err:
++ drm_free(task, sizeof(*task), DRM_MEM_DRIVER);
++ *task_p = NULL;
++ return ret;
+}
+
-+static void psb_ta_fire_reply(struct drm_psb_private *dev_priv,
-+ struct psb_scheduler *scheduler)
++int psb_cmdbuf_ta(struct drm_file *priv,
++ struct drm_psb_cmdbuf_arg *arg,
++ struct drm_buffer_object *cmd_buffer,
++ struct drm_buffer_object *ta_buffer,
++ struct drm_buffer_object *oom_buffer,
++ struct psb_scene *scene,
++ struct psb_feedback_info *feedback,
++ struct drm_fence_arg *fence_arg)
+{
-+ struct psb_task *task = scheduler->current_task[PSB_SCENE_ENGINE_TA];
++ struct drm_device *dev = priv->minor->dev;
++ struct drm_psb_private *dev_priv = dev->dev_private;
++ struct drm_fence_object *fence = NULL;
++ struct psb_task *task = NULL;
++ int ret;
++ struct psb_scheduler *scheduler = &dev_priv->scheduler;
++ unsigned long irq_flags;
+
-+ psb_xhw_fire_reply(dev_priv, &task->buf, task->scene->hw_cookie);
++ PSB_DEBUG_RENDER("Cmdbuf ta\n");
+
-+ psb_dispatch_ta(dev_priv, scheduler, PSB_RF_FIRE_TA);
-+}
++ ret = mutex_lock_interruptible(&dev_priv->reset_mutex);
++ if (ret)
++ return -EAGAIN;
+
-+static void psb_raster_fire_reply(struct drm_psb_private *dev_priv,
-+ struct psb_scheduler *scheduler)
-+{
-+ struct psb_task *task =
-+ scheduler->current_task[PSB_SCENE_ENGINE_RASTER];
-+ uint32_t reply_flags;
++ mutex_lock(&dev->struct_mutex);
++ ret = psb_setup_task_devlocked(dev, arg, cmd_buffer, ta_buffer,
++ oom_buffer, scene,
++ psb_ta_task, PSB_ENGINE_TA,
++ PSB_FIRE_FLAG_RASTER_DEALLOC, &task);
++ mutex_unlock(&dev->struct_mutex);
+
-+ if (!task) {
-+ DRM_ERROR("Null task.\n");
-+ return;
-+ }
++ if (ret)
++ goto out_err;
+
-+ task->raster_complete_action = task->buf.arg.arg.sb.rca;
-+ psb_xhw_fire_reply(dev_priv, &task->buf, task->scene->hw_cookie);
++ task->feedback = *feedback;
+
-+ reply_flags = PSB_RF_FIRE_RASTER;
-+ if (task->raster_complete_action == PSB_RASTER)
-+ reply_flags |= PSB_RF_DEALLOC;
++ /*
++ * Hand the task over to the scheduler.
++ */
+
-+ psb_dispatch_raster(dev_priv, scheduler, reply_flags);
-+}
++ spin_lock_irqsave(&scheduler->lock, irq_flags);
++ task->sequence = psb_fence_advance_sequence(dev, PSB_ENGINE_TA);
+
-+static int psb_user_interrupt(struct drm_psb_private *dev_priv,
-+ struct psb_scheduler *scheduler)
-+{
-+ uint32_t type;
-+ int ret;
-+ unsigned long irq_flags;
++ psb_report_fence(scheduler, PSB_ENGINE_TA, task->sequence, 0, 1);
+
-+ /*
-+ * Xhw cannot write directly to the comm page, so
-+ * do it here. Firmware would have written directly.
-+ */
++ task->ta_complete_action = PSB_RASTER;
++ task->raster_complete_action = PSB_RETURN;
+
-+ ret = psb_xhw_handler(dev_priv);
-+ if (unlikely(ret))
-+ return ret;
++ list_add_tail(&task->head, &scheduler->ta_queue);
++ PSB_DEBUG_RENDER("queued ta %u\n", task->sequence);
+
-+ spin_lock_irqsave(&dev_priv->xhw_lock, irq_flags);
-+ type = dev_priv->comm[PSB_COMM_USER_IRQ];
-+ dev_priv->comm[PSB_COMM_USER_IRQ] = 0;
-+ if (dev_priv->comm[PSB_COMM_USER_IRQ_LOST]) {
-+ dev_priv->comm[PSB_COMM_USER_IRQ_LOST] = 0;
-+ DRM_ERROR("Lost Poulsbo hardware event.\n");
-+ }
-+ spin_unlock_irqrestore(&dev_priv->xhw_lock, irq_flags);
++ psb_schedule_ta(dev_priv, scheduler);
++ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
+
-+ if (type == 0)
-+ return 0;
++ psb_fence_or_sync(priv, PSB_ENGINE_TA, arg, fence_arg, &fence);
++ drm_regs_fence(&dev_priv->use_manager, fence);
++ if (fence)
++ fence_arg->signaled |= 0x1;
+
-+ switch (type) {
-+ case PSB_UIRQ_VISTEST:
-+ psb_vistest_reply(dev_priv, scheduler);
-+ break;
-+ case PSB_UIRQ_OOM_REPLY:
-+ psb_ta_oom_reply(dev_priv, scheduler);
-+ break;
-+ case PSB_UIRQ_FIRE_TA_REPLY:
-+ psb_ta_fire_reply(dev_priv, scheduler);
-+ break;
-+ case PSB_UIRQ_FIRE_RASTER_REPLY:
-+ psb_raster_fire_reply(dev_priv, scheduler);
-+ break;
-+ default:
-+ DRM_ERROR("Unknown Poulsbo hardware event. %d\n", type);
++ out_err:
++ if (ret && ret != -EAGAIN)
++ DRM_ERROR("TA task queue job failed.\n");
++
++ if (fence) {
++#ifdef PSB_WAIT_FOR_TA_COMPLETION
++ drm_fence_object_wait(fence, 1, 1, DRM_FENCE_TYPE_EXE |
++ _PSB_FENCE_TYPE_TA_DONE);
++#ifdef PSB_BE_PARANOID
++ drm_fence_object_wait(fence, 1, 1, DRM_FENCE_TYPE_EXE |
++ _PSB_FENCE_TYPE_SCENE_DONE);
++#endif
++#endif
++ drm_fence_usage_deref_unlocked(&fence);
+ }
-+ return 0;
++ mutex_unlock(&dev_priv->reset_mutex);
++
++ return ret;
+}
+
-+int psb_forced_user_interrupt(struct drm_psb_private *dev_priv)
++int psb_cmdbuf_raster(struct drm_file *priv,
++ struct drm_psb_cmdbuf_arg *arg,
++ struct drm_buffer_object *cmd_buffer,
++ struct drm_fence_arg *fence_arg)
+{
++ struct drm_device *dev = priv->minor->dev;
++ struct drm_psb_private *dev_priv = dev->dev_private;
++ struct drm_fence_object *fence = NULL;
++ struct psb_task *task = NULL;
++ int ret;
+ struct psb_scheduler *scheduler = &dev_priv->scheduler;
+ unsigned long irq_flags;
-+ int ret;
+
-+ spin_lock_irqsave(&scheduler->lock, irq_flags);
-+ ret = psb_user_interrupt(dev_priv, scheduler);
-+ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
-+ return ret;
-+}
++ PSB_DEBUG_RENDER("Cmdbuf Raster\n");
+
-+static void psb_dispatch_ta(struct drm_psb_private *dev_priv,
-+ struct psb_scheduler *scheduler,
-+ uint32_t reply_flag)
-+{
-+ struct psb_task *task = scheduler->current_task[PSB_SCENE_ENGINE_TA];
-+ uint32_t flags;
-+ uint32_t mask;
++ ret = mutex_lock_interruptible(&dev_priv->reset_mutex);
++ if (ret)
++ return -EAGAIN;
+
-+ task->reply_flags |= reply_flag;
-+ flags = task->reply_flags;
-+ mask = PSB_RF_FIRE_TA;
++ mutex_lock(&dev->struct_mutex);
++ ret = psb_setup_task_devlocked(dev, arg, cmd_buffer, NULL, NULL,
++ NULL, psb_raster_task,
++ PSB_ENGINE_TA, 0, &task);
++ mutex_unlock(&dev->struct_mutex);
+
-+ if (!(flags & mask))
-+ return;
++ if (ret)
++ goto out_err;
+
-+ mask = PSB_RF_TA_DONE;
-+ if ((flags & mask) == mask) {
-+ task->reply_flags &= ~mask;
-+ psb_ta_done(dev_priv, scheduler);
-+ }
++ /*
++ * Hand the task over to the scheduler.
++ */
+
-+ mask = PSB_RF_OOM;
-+ if ((flags & mask) == mask) {
-+ task->reply_flags &= ~mask;
-+ psb_ta_oom(dev_priv, scheduler);
-+ }
++ spin_lock_irqsave(&scheduler->lock, irq_flags);
++ task->sequence = psb_fence_advance_sequence(dev, PSB_ENGINE_TA);
++ psb_report_fence(scheduler, PSB_ENGINE_TA, task->sequence, 0, 1);
++ task->ta_complete_action = PSB_RASTER;
++ task->raster_complete_action = PSB_RETURN;
+
-+ mask = (PSB_RF_OOM_REPLY | PSB_RF_TERMINATE);
-+ if ((flags & mask) == mask) {
-+ task->reply_flags &= ~mask;
-+ psb_ta_done(dev_priv, scheduler);
++ list_add_tail(&task->head, &scheduler->ta_queue);
++ PSB_DEBUG_RENDER("queued raster %u\n", task->sequence);
++ psb_schedule_ta(dev_priv, scheduler);
++ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
++
++ psb_fence_or_sync(priv, PSB_ENGINE_TA, arg, fence_arg, &fence);
++ drm_regs_fence(&dev_priv->use_manager, fence);
++ if (fence)
++ fence_arg->signaled |= 0x1;
++ out_err:
++ if (ret && ret != -EAGAIN)
++ DRM_ERROR("Raster task queue job failed.\n");
++
++ if (fence) {
++#ifdef PSB_WAIT_FOR_RASTER_COMPLETION
++ drm_fence_object_wait(fence, 1, 1, fence->type);
++#endif
++ drm_fence_usage_deref_unlocked(&fence);
+ }
-+}
+
-+static void psb_dispatch_raster(struct drm_psb_private *dev_priv,
-+ struct psb_scheduler *scheduler,
-+ uint32_t reply_flag)
-+{
-+ struct psb_task *task =
-+ scheduler->current_task[PSB_SCENE_ENGINE_RASTER];
-+ uint32_t flags;
-+ uint32_t mask;
++ mutex_unlock(&dev_priv->reset_mutex);
+
-+ task->reply_flags |= reply_flag;
-+ flags = task->reply_flags;
-+ mask = PSB_RF_FIRE_RASTER;
++ return ret;
++}
+
-+ if (!(flags & mask))
-+ return;
++#ifdef FIX_TG_16
+
-+ /*
-+ * For rasterizer-only tasks, don't report fence done here,
-+ * as this is time consuming and the rasterizer wants a new
-+ * task immediately. For other tasks, the hardware is probably
-+ * still busy deallocating TA memory, so we can report
-+ * fence done in parallel.
-+ */
++static int psb_check_2d_idle(struct drm_psb_private *dev_priv)
++{
++ if (psb_2d_trylock(dev_priv)) {
++ if ((PSB_RSGX32(PSB_CR_2D_SOCIF) == _PSB_C2_SOCIF_EMPTY) &&
++ !((PSB_RSGX32(PSB_CR_2D_BLIT_STATUS) &
++ _PSB_C2B_STATUS_BUSY))) {
++ return 0;
++ }
++ if (atomic_cmpxchg(&dev_priv->ta_wait_2d_irq, 0, 1) == 0)
++ psb_2D_irq_on(dev_priv);
+
-+ if (task->raster_complete_action == PSB_RETURN &&
-+ (reply_flag & PSB_RF_RASTER_DONE) && task->scene != NULL) {
-+ psb_report_fence(scheduler, task->engine, task->sequence,
-+ _PSB_FENCE_RASTER_DONE_SHIFT, 1);
-+ }
++ PSB_WSGX32(PSB_2D_FENCE_BH, PSB_SGX_2D_SLAVE_PORT);
++ PSB_WSGX32(PSB_2D_FLUSH_BH, PSB_SGX_2D_SLAVE_PORT);
++ (void)PSB_RSGX32(PSB_SGX_2D_SLAVE_PORT);
+
-+ mask = PSB_RF_RASTER_DONE | PSB_RF_DEALLOC;
-+ if ((flags & mask) == mask) {
-+ task->reply_flags &= ~mask;
-+ psb_raster_done(dev_priv, scheduler);
++ psb_2d_atomic_unlock(dev_priv);
+ }
++
++ atomic_set(&dev_priv->ta_wait_2d, 1);
++ return -EBUSY;
+}
+
-+void psb_scheduler_handler(struct drm_psb_private *dev_priv, uint32_t status)
++static void psb_atomic_resume_ta_2d_idle(struct drm_psb_private *dev_priv)
+{
+ struct psb_scheduler *scheduler = &dev_priv->scheduler;
+
-+ spin_lock(&scheduler->lock);
-+
-+ if (status & _PSB_CE_PIXELBE_END_RENDER) {
-+ psb_dispatch_raster(dev_priv, scheduler, PSB_RF_RASTER_DONE);
-+ }
-+ if (status & _PSB_CE_DPM_3D_MEM_FREE) {
-+ psb_dispatch_raster(dev_priv, scheduler, PSB_RF_DEALLOC);
-+ }
-+ if (status & _PSB_CE_TA_FINISHED) {
-+ psb_dispatch_ta(dev_priv, scheduler, PSB_RF_TA_DONE);
-+ }
-+ if (status & _PSB_CE_TA_TERMINATE) {
-+ psb_dispatch_ta(dev_priv, scheduler, PSB_RF_TERMINATE);
-+ }
-+ if (status & (_PSB_CE_DPM_REACHED_MEM_THRESH |
-+ _PSB_CE_DPM_OUT_OF_MEMORY_GBL |
-+ _PSB_CE_DPM_OUT_OF_MEMORY_MT)) {
-+ psb_dispatch_ta(dev_priv, scheduler, PSB_RF_OOM);
-+ }
-+ if (status & _PSB_CE_DPM_TA_MEM_FREE) {
-+ psb_ta_hw_scene_freed(dev_priv, scheduler);
-+ }
-+ if (status & _PSB_CE_SW_EVENT) {
-+ psb_user_interrupt(dev_priv, scheduler);
++ if (atomic_cmpxchg(&dev_priv->ta_wait_2d, 1, 0) == 1) {
++ psb_schedule_ta(dev_priv, scheduler);
++ if (atomic_read(&dev_priv->waiters_2d) != 0)
++ wake_up(&dev_priv->queue_2d);
+ }
-+ spin_unlock(&scheduler->lock);
+}
+
-+static void psb_free_task_wq(struct work_struct *work)
++void psb_resume_ta_2d_idle(struct drm_psb_private *dev_priv)
+{
-+ struct psb_scheduler *scheduler =
-+ container_of(work, struct psb_scheduler, wq.work);
-+
-+ struct drm_device *dev = scheduler->dev;
-+ struct list_head *list, *next;
++ struct psb_scheduler *scheduler = &dev_priv->scheduler;
+ unsigned long irq_flags;
-+ struct psb_task *task;
-+
-+ if (!mutex_trylock(&scheduler->task_wq_mutex))
-+ return;
+
+ spin_lock_irqsave(&scheduler->lock, irq_flags);
-+ list_for_each_safe(list, next, &scheduler->task_done_queue) {
-+ task = list_entry(list, struct psb_task, head);
-+ list_del_init(list);
-+ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
-+
-+ PSB_DEBUG_RENDER("Checking Task %d: Scene 0x%08lx, "
-+ "Feedback bo 0x%08lx, done %d\n",
-+ task->sequence, (unsigned long)task->scene,
-+ (unsigned long)task->feedback.bo,
-+ atomic_read(&task->buf.done));
-+
-+ if (task->scene) {
-+ mutex_lock(&dev->struct_mutex);
-+ PSB_DEBUG_RENDER("Unref scene %d\n", task->sequence);
-+ psb_scene_unref_devlocked(&task->scene);
-+ if (task->feedback.bo) {
-+ PSB_DEBUG_RENDER("Unref feedback bo %d\n",
-+ task->sequence);
-+ drm_bo_usage_deref_locked(&task->feedback.bo);
-+ }
-+ mutex_unlock(&dev->struct_mutex);
-+ }
-+
-+ if (atomic_read(&task->buf.done)) {
-+ PSB_DEBUG_RENDER("Deleting task %d\n", task->sequence);
-+ drm_free(task, sizeof(*task), DRM_MEM_DRIVER);
-+ task = NULL;
-+ }
-+ spin_lock_irqsave(&scheduler->lock, irq_flags);
-+ if (task != NULL)
-+ list_add(list, &scheduler->task_done_queue);
-+ }
-+ if (!list_empty(&scheduler->task_done_queue)) {
-+ PSB_DEBUG_RENDER("Rescheduling wq\n");
-+ schedule_delayed_work(&scheduler->wq, 1);
++ if (atomic_cmpxchg(&dev_priv->ta_wait_2d_irq, 1, 0) == 1) {
++ atomic_set(&dev_priv->ta_wait_2d, 0);
++ psb_2D_irq_off(dev_priv);
++ psb_schedule_ta(dev_priv, scheduler);
++ if (atomic_read(&dev_priv->waiters_2d) != 0)
++ wake_up(&dev_priv->queue_2d);
+ }
+ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
-+
-+ mutex_unlock(&scheduler->task_wq_mutex);
+}
+
+/*
-+ * Check if any of the tasks in the queues is using a scene.
-+ * In that case we know the TA memory buffer objects are
-+ * fenced and will not be evicted until that fence is signaled.
++ * 2D locking functions. Can't use a mutex since the trylock() and
++ * unlock() methods need to be accessible from interrupt context.
+ */
+
-+void psb_scheduler_ta_mem_check(struct drm_psb_private *dev_priv)
++static int psb_2d_trylock(struct drm_psb_private *dev_priv)
+{
-+ struct psb_scheduler *scheduler = &dev_priv->scheduler;
-+ unsigned long irq_flags;
-+ struct psb_task *task;
-+ struct psb_task *next_task;
++ return (atomic_cmpxchg(&dev_priv->lock_2d, 0, 1) == 0);
++}
+
-+ dev_priv->force_ta_mem_load = 1;
-+ spin_lock_irqsave(&scheduler->lock, irq_flags);
-+ list_for_each_entry_safe(task, next_task, &scheduler->ta_queue, head) {
-+ if (task->scene) {
-+ dev_priv->force_ta_mem_load = 0;
-+ break;
-+ }
-+ }
-+ list_for_each_entry_safe(task, next_task, &scheduler->raster_queue,
-+ head) {
-+ if (task->scene) {
-+ dev_priv->force_ta_mem_load = 0;
-+ break;
-+ }
-+ }
-+ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
++static void psb_2d_atomic_unlock(struct drm_psb_private *dev_priv)
++{
++ atomic_set(&dev_priv->lock_2d, 0);
++ if (atomic_read(&dev_priv->waiters_2d) != 0)
++ wake_up(&dev_priv->queue_2d);
+}
+
-+void psb_scheduler_reset(struct drm_psb_private *dev_priv, int error_condition)
++void psb_2d_unlock(struct drm_psb_private *dev_priv)
+{
+ struct psb_scheduler *scheduler = &dev_priv->scheduler;
-+ unsigned long wait_jiffies;
-+ unsigned long cur_jiffies;
-+ struct psb_task *task;
-+ struct psb_task *next_task;
+ unsigned long irq_flags;
+
-+ psb_scheduler_pause(dev_priv);
-+ if (!psb_scheduler_idle(dev_priv)) {
-+ spin_lock_irqsave(&scheduler->lock, irq_flags);
-+
-+ cur_jiffies = jiffies;
-+ wait_jiffies = cur_jiffies;
-+ if (scheduler->current_task[PSB_SCENE_ENGINE_TA] &&
-+ time_after_eq(scheduler->ta_end_jiffies, wait_jiffies))
-+ wait_jiffies = scheduler->ta_end_jiffies;
-+ if (scheduler->current_task[PSB_SCENE_ENGINE_RASTER] &&
-+ time_after_eq(scheduler->raster_end_jiffies, wait_jiffies))
-+ wait_jiffies = scheduler->raster_end_jiffies;
-+
-+ wait_jiffies -= cur_jiffies;
-+ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
++ spin_lock_irqsave(&scheduler->lock, irq_flags);
++ psb_2d_atomic_unlock(dev_priv);
++ if (atomic_read(&dev_priv->ta_wait_2d) != 0)
++ psb_atomic_resume_ta_2d_idle(dev_priv);
++ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
++}
+
-+ (void)wait_event_timeout(scheduler->idle_queue,
-+ psb_scheduler_idle(dev_priv),
-+ wait_jiffies);
-+ }
++void psb_2d_lock(struct drm_psb_private *dev_priv)
++{
++ atomic_inc(&dev_priv->waiters_2d);
++ wait_event(dev_priv->queue_2d, atomic_read(&dev_priv->ta_wait_2d) == 0);
++ wait_event(dev_priv->queue_2d, psb_2d_trylock(dev_priv));
++ atomic_dec(&dev_priv->waiters_2d);
++}
+
-+ if (!psb_scheduler_idle(dev_priv)) {
-+ spin_lock_irqsave(&scheduler->lock, irq_flags);
-+ task = scheduler->current_task[PSB_SCENE_ENGINE_RASTER];
-+ if (task) {
-+ DRM_ERROR("Detected Poulsbo rasterizer lockup.\n");
-+ if (task->engine == PSB_ENGINE_HPRAST) {
-+ psb_fence_error(scheduler->dev,
-+ PSB_ENGINE_HPRAST,
-+ task->sequence,
-+ _PSB_FENCE_TYPE_RASTER_DONE,
-+ error_condition);
-+
-+ list_del(&task->head);
-+ psb_xhw_clean_buf(dev_priv, &task->buf);
-+ list_add_tail(&task->head,
-+ &scheduler->task_done_queue);
-+ } else {
-+ list_add(&task->head, &scheduler->raster_queue);
-+ }
-+ }
-+ scheduler->current_task[PSB_SCENE_ENGINE_RASTER] = NULL;
-+ task = scheduler->current_task[PSB_SCENE_ENGINE_TA];
-+ if (task) {
-+ DRM_ERROR("Detected Poulsbo ta lockup.\n");
-+ list_add_tail(&task->head, &scheduler->raster_queue);
-+#ifdef FIX_TG_16
-+ psb_2d_atomic_unlock(dev_priv);
+#endif
-+ }
-+ scheduler->current_task[PSB_SCENE_ENGINE_TA] = NULL;
-+ scheduler->ta_state = 0;
-+
-+#ifdef FIX_TG_16
-+ atomic_set(&dev_priv->ta_wait_2d, 0);
-+ atomic_set(&dev_priv->ta_wait_2d_irq, 0);
-+ wake_up(&dev_priv->queue_2d);
-+#endif
-+ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
-+ }
+Index: linux-2.6.28/drivers/gpu/drm/psb/psb_schedule.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.28/drivers/gpu/drm/psb/psb_schedule.h 2009-02-12 09:14:42.000000000 +0000
+@@ -0,0 +1,170 @@
++/**************************************************************************
++ * Copyright (c) 2007, Intel Corporation.
++ * All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
++ *
++ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
++ * develop this driver.
++ *
++ **************************************************************************/
++/*
++ * Authors: Thomas Hellstrom <thomas-at-tungstengraphics.com>
++ */
+
-+ /*
-+ * Empty raster queue.
-+ */
++#ifndef _PSB_SCHEDULE_H_
++#define _PSB_SCHEDULE_H_
+
-+ spin_lock_irqsave(&scheduler->lock, irq_flags);
-+ list_for_each_entry_safe(task, next_task, &scheduler->raster_queue,
-+ head) {
-+ struct psb_scene *scene = task->scene;
++#include "drmP.h"
+
-+ psb_fence_error(scheduler->dev,
-+ task->engine,
-+ task->sequence,
-+ _PSB_FENCE_TYPE_TA_DONE |
-+ _PSB_FENCE_TYPE_RASTER_DONE |
-+ _PSB_FENCE_TYPE_SCENE_DONE |
-+ _PSB_FENCE_TYPE_FEEDBACK, error_condition);
-+ if (scene) {
-+ scene->flags = 0;
-+ if (scene->hw_scene) {
-+ list_add_tail(&scene->hw_scene->head,
-+ &scheduler->hw_scenes);
-+ scene->hw_scene = NULL;
-+ }
-+ }
++enum psb_task_type {
++ psb_ta_midscene_task,
++ psb_ta_task,
++ psb_raster_task,
++ psb_freescene_task
++};
+
-+ psb_xhw_clean_buf(dev_priv, &task->buf);
-+ list_del(&task->head);
-+ list_add_tail(&task->head, &scheduler->task_done_queue);
-+ }
++#define PSB_MAX_TA_CMDS 60
++#define PSB_MAX_RASTER_CMDS 60
++#define PSB_MAX_OOM_CMDS 6
+
-+ schedule_delayed_work(&scheduler->wq, 1);
-+ scheduler->idle = 1;
-+ wake_up(&scheduler->idle_queue);
++struct psb_xhw_buf {
++ struct list_head head;
++ int copy_back;
++ atomic_t done;
++ struct drm_psb_xhw_arg arg;
+
-+ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
-+ psb_scheduler_restart(dev_priv);
++};
+
-+}
++struct psb_feedback_info {
++ struct drm_buffer_object *bo;
++ struct page *page;
++ uint32_t offset;
++};
+
-+int psb_scheduler_init(struct drm_device *dev, struct psb_scheduler *scheduler)
-+{
-+ struct psb_hw_scene *hw_scene;
-+ int i;
++struct psb_task {
++ struct list_head head;
++ struct psb_scene *scene;
++ struct psb_feedback_info feedback;
++ enum psb_task_type task_type;
++ uint32_t engine;
++ uint32_t sequence;
++ uint32_t ta_cmds[PSB_MAX_TA_CMDS];
++ uint32_t raster_cmds[PSB_MAX_RASTER_CMDS];
++ uint32_t oom_cmds[PSB_MAX_OOM_CMDS];
++ uint32_t ta_cmd_size;
++ uint32_t raster_cmd_size;
++ uint32_t oom_cmd_size;
++ uint32_t feedback_offset;
++ uint32_t ta_complete_action;
++ uint32_t raster_complete_action;
++ uint32_t hw_cookie;
++ uint32_t flags;
++ uint32_t reply_flags;
++ uint32_t aborting;
++ struct psb_xhw_buf buf;
++};
+
-+ memset(scheduler, 0, sizeof(*scheduler));
-+ scheduler->dev = dev;
-+ mutex_init(&scheduler->task_wq_mutex);
-+ scheduler->lock = SPIN_LOCK_UNLOCKED;
-+ scheduler->idle = 1;
++struct psb_hw_scene {
++ struct list_head head;
++ uint32_t context_number;
+
-+ INIT_LIST_HEAD(&scheduler->ta_queue);
-+ INIT_LIST_HEAD(&scheduler->raster_queue);
-+ INIT_LIST_HEAD(&scheduler->hp_raster_queue);
-+ INIT_LIST_HEAD(&scheduler->hw_scenes);
-+ INIT_LIST_HEAD(&scheduler->task_done_queue);
-+ INIT_DELAYED_WORK(&scheduler->wq, &psb_free_task_wq);
-+ init_waitqueue_head(&scheduler->idle_queue);
++ /*
++ * This pointer does not refcount the last_scene_buffer,
++ * so we must make sure it is set to NULL before destroying
++ * the corresponding task.
++ */
+
-+ for (i = 0; i < PSB_NUM_HW_SCENES; ++i) {
-+ hw_scene = &scheduler->hs[i];
-+ hw_scene->context_number = i;
-+ list_add_tail(&hw_scene->head, &scheduler->hw_scenes);
-+ }
++ struct psb_scene *last_scene;
++};
+
-+ for (i = 0; i < _PSB_ENGINE_TA_FENCE_TYPES; ++i) {
-+ scheduler->seq[i].reported = 0;
-+ }
++struct psb_scene;
++struct drm_psb_private;
+
-+ return 0;
-+}
++struct psb_scheduler_seq {
++ uint32_t sequence;
++ int reported;
++};
+
-+/*
-+ * Scene references maintained by the scheduler are not refcounted.
-+ * Remove all references to a particular scene here.
-+ */
++struct psb_scheduler {
++ struct drm_device *dev;
++ struct psb_scheduler_seq seq[_PSB_ENGINE_TA_FENCE_TYPES];
++ struct psb_hw_scene hs[PSB_NUM_HW_SCENES];
++ struct mutex task_wq_mutex;
++ spinlock_t lock;
++ struct list_head hw_scenes;
++ struct list_head ta_queue;
++ struct list_head raster_queue;
++ struct list_head hp_raster_queue;
++ struct list_head task_done_queue;
++ struct psb_task *current_task[PSB_SCENE_NUM_ENGINES];
++ struct psb_task *feedback_task;
++ int ta_state;
++ struct psb_hw_scene *pending_hw_scene;
++ uint32_t pending_hw_scene_seq;
++ struct delayed_work wq;
++ struct psb_scene_pool *pool;
++ uint32_t idle_count;
++ int idle;
++ wait_queue_head_t idle_queue;
++ unsigned long ta_end_jiffies;
++ unsigned long raster_end_jiffies;
++ unsigned long total_raster_jiffies;
++};
+
-+void psb_scheduler_remove_scene_refs(struct psb_scene *scene)
-+{
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)scene->dev->dev_private;
-+ struct psb_scheduler *scheduler = &dev_priv->scheduler;
-+ struct psb_hw_scene *hw_scene;
-+ unsigned long irq_flags;
-+ unsigned int i;
++#define PSB_RF_FIRE_TA (1 << 0)
++#define PSB_RF_OOM (1 << 1)
++#define PSB_RF_OOM_REPLY (1 << 2)
++#define PSB_RF_TERMINATE (1 << 3)
++#define PSB_RF_TA_DONE (1 << 4)
++#define PSB_RF_FIRE_RASTER (1 << 5)
++#define PSB_RF_RASTER_DONE (1 << 6)
++#define PSB_RF_DEALLOC (1 << 7)
+
-+ spin_lock_irqsave(&scheduler->lock, irq_flags);
-+ for (i = 0; i < PSB_NUM_HW_SCENES; ++i) {
-+ hw_scene = &scheduler->hs[i];
-+ if (hw_scene->last_scene == scene) {
-+ BUG_ON(list_empty(&hw_scene->head));
-+ hw_scene->last_scene = NULL;
-+ }
-+ }
-+ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
-+}
++extern struct psb_scene_pool *psb_alloc_scene_pool(struct drm_file *priv,
++ int shareable, uint32_t w,
++ uint32_t h);
++extern uint32_t psb_scene_handle(struct psb_scene *scene);
++extern int psb_scheduler_init(struct drm_device *dev,
++ struct psb_scheduler *scheduler);
++extern void psb_scheduler_takedown(struct psb_scheduler *scheduler);
++extern int psb_cmdbuf_ta(struct drm_file *priv,
++ struct drm_psb_cmdbuf_arg *arg,
++ struct drm_buffer_object *cmd_buffer,
++ struct drm_buffer_object *ta_buffer,
++ struct drm_buffer_object *oom_buffer,
++ struct psb_scene *scene,
++ struct psb_feedback_info *feedback,
++ struct drm_fence_arg *fence_arg);
++extern int psb_cmdbuf_raster(struct drm_file *priv,
++ struct drm_psb_cmdbuf_arg *arg,
++ struct drm_buffer_object *cmd_buffer,
++ struct drm_fence_arg *fence_arg);
++extern void psb_scheduler_handler(struct drm_psb_private *dev_priv,
++ uint32_t status);
++extern void psb_scheduler_pause(struct drm_psb_private *dev_priv);
++extern void psb_scheduler_restart(struct drm_psb_private *dev_priv);
++extern int psb_scheduler_idle(struct drm_psb_private *dev_priv);
++extern int psb_scheduler_finished(struct drm_psb_private *dev_priv);
+
-+void psb_scheduler_takedown(struct psb_scheduler *scheduler)
-+{
-+ flush_scheduled_work();
-+}
-+
-+static int psb_setup_task_devlocked(struct drm_device *dev,
-+ struct drm_psb_cmdbuf_arg *arg,
-+ struct drm_buffer_object *raster_cmd_buffer,
-+ struct drm_buffer_object *ta_cmd_buffer,
-+ struct drm_buffer_object *oom_cmd_buffer,
-+ struct psb_scene *scene,
-+ enum psb_task_type task_type,
-+ uint32_t engine,
-+ uint32_t flags, struct psb_task **task_p)
-+{
-+ struct psb_task *task;
-+ int ret;
-+
-+ if (ta_cmd_buffer && arg->ta_size > PSB_MAX_TA_CMDS) {
-+ DRM_ERROR("Too many ta cmds %d.\n", arg->ta_size);
-+ return -EINVAL;
-+ }
-+ if (raster_cmd_buffer && arg->cmdbuf_size > PSB_MAX_RASTER_CMDS) {
-+ DRM_ERROR("Too many raster cmds %d.\n", arg->cmdbuf_size);
-+ return -EINVAL;
-+ }
-+ if (oom_cmd_buffer && arg->oom_size > PSB_MAX_OOM_CMDS) {
-+ DRM_ERROR("Too many raster cmds %d.\n", arg->oom_size);
-+ return -EINVAL;
-+ }
++extern void psb_scheduler_lockup(struct drm_psb_private *dev_priv,
++ int *lockup, int *idle);
++extern void psb_scheduler_reset(struct drm_psb_private *dev_priv,
++ int error_condition);
++extern int psb_forced_user_interrupt(struct drm_psb_private *dev_priv);
++extern void psb_scheduler_remove_scene_refs(struct psb_scene *scene);
++extern void psb_scheduler_ta_mem_check(struct drm_psb_private *dev_priv);
++extern int psb_extend_raster_timeout(struct drm_psb_private *dev_priv);
+
-+ task = drm_calloc(1, sizeof(*task), DRM_MEM_DRIVER);
-+ if (!task)
-+ return -ENOMEM;
++#endif
+Index: linux-2.6.28/drivers/gpu/drm/psb/psb_setup.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.28/drivers/gpu/drm/psb/psb_setup.c 2009-02-12 09:59:18.000000000 +0000
+@@ -0,0 +1,18 @@
++#include "drmP.h"
++#include "drm.h"
++#include "drm_crtc.h"
++#include "drm_edid.h"
++#include "psb_drm.h"
++#include "psb_priv.h"
++//#include "i915_reg.h"
++//#include "intel_drv.h"
++#include "../i915/intel_crt.c"
+
-+ atomic_set(&task->buf.done, 1);
-+ task->engine = engine;
-+ INIT_LIST_HEAD(&task->head);
-+ INIT_LIST_HEAD(&task->buf.head);
-+ if (ta_cmd_buffer && arg->ta_size != 0) {
-+ task->ta_cmd_size = arg->ta_size;
-+ ret = psb_submit_copy_cmdbuf(dev, ta_cmd_buffer,
-+ arg->ta_offset,
-+ arg->ta_size,
-+ PSB_ENGINE_TA, task->ta_cmds);
-+ if (ret)
-+ goto out_err;
-+ }
-+ if (raster_cmd_buffer) {
-+ task->raster_cmd_size = arg->cmdbuf_size;
-+ ret = psb_submit_copy_cmdbuf(dev, raster_cmd_buffer,
-+ arg->cmdbuf_offset,
-+ arg->cmdbuf_size,
-+ PSB_ENGINE_TA, task->raster_cmds);
-+ if (ret)
-+ goto out_err;
-+ }
-+ if (oom_cmd_buffer && arg->oom_size != 0) {
-+ task->oom_cmd_size = arg->oom_size;
-+ ret = psb_submit_copy_cmdbuf(dev, oom_cmd_buffer,
-+ arg->oom_offset,
-+ arg->oom_size,
-+ PSB_ENGINE_TA, task->oom_cmds);
-+ if (ret)
-+ goto out_err;
-+ }
-+ task->task_type = task_type;
-+ task->flags = flags;
-+ if (scene)
-+ task->scene = psb_scene_ref(scene);
++/* Fixed name */
++#define ACPI_EDID_LCD "\\_SB_.PCI0.GFX0.DD04._DDC"
++#define ACPI_DOD "\\_SB_.PCI0.GFX0._DOD"
+
-+ *task_p = task;
-+ return 0;
-+ out_err:
-+ drm_free(task, sizeof(*task), DRM_MEM_DRIVER);
-+ *task_p = NULL;
-+ return ret;
-+}
++#include "../i915/intel_lvds.c"
++#include "../i915/intel_sdvo.c"
++#include "../i915/intel_display.c"
++#include "../i915/intel_modes.c"
+Index: linux-2.6.28/drivers/gpu/drm/psb/psb_sgx.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.28/drivers/gpu/drm/psb/psb_sgx.c 2009-02-12 09:14:42.000000000 +0000
+@@ -0,0 +1,1422 @@
++/**************************************************************************
++ * Copyright (c) 2007, Intel Corporation.
++ * All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
++ *
++ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
++ * develop this driver.
++ *
++ **************************************************************************/
++/*
++ */
+
-+int psb_cmdbuf_ta(struct drm_file *priv,
-+ struct drm_psb_cmdbuf_arg *arg,
-+ struct drm_buffer_object *cmd_buffer,
-+ struct drm_buffer_object *ta_buffer,
-+ struct drm_buffer_object *oom_buffer,
-+ struct psb_scene *scene,
-+ struct psb_feedback_info *feedback,
-+ struct drm_fence_arg *fence_arg)
-+{
-+ struct drm_device *dev = priv->minor->dev;
-+ struct drm_psb_private *dev_priv = dev->dev_private;
-+ struct drm_fence_object *fence = NULL;
-+ struct psb_task *task = NULL;
-+ int ret;
-+ struct psb_scheduler *scheduler = &dev_priv->scheduler;
-+ unsigned long irq_flags;
++#include "drmP.h"
++#include "psb_drv.h"
++#include "psb_drm.h"
++#include "psb_reg.h"
++#include "psb_scene.h"
+
-+ PSB_DEBUG_RENDER("Cmdbuf ta\n");
++#include "psb_msvdx.h"
+
-+ ret = mutex_lock_interruptible(&dev_priv->reset_mutex);
-+ if (ret)
-+ return -EAGAIN;
++int psb_submit_video_cmdbuf(struct drm_device *dev,
++ struct drm_buffer_object *cmd_buffer,
++ unsigned long cmd_offset, unsigned long cmd_size,
++ struct drm_fence_object *fence);
+
-+ mutex_lock(&dev->struct_mutex);
-+ ret = psb_setup_task_devlocked(dev, arg, cmd_buffer, ta_buffer,
-+ oom_buffer, scene,
-+ psb_ta_task, PSB_ENGINE_TA,
-+ PSB_FIRE_FLAG_RASTER_DEALLOC, &task);
-+ mutex_unlock(&dev->struct_mutex);
++struct psb_dstbuf_cache {
++ unsigned int dst;
++ uint32_t *use_page;
++ unsigned int use_index;
++ uint32_t use_background;
++ struct drm_buffer_object *dst_buf;
++ unsigned long dst_offset;
++ uint32_t *dst_page;
++ unsigned int dst_page_offset;
++ struct drm_bo_kmap_obj dst_kmap;
++ int dst_is_iomem;
++};
+
-+ if (ret)
-+ goto out_err;
++struct psb_buflist_item {
++ struct drm_buffer_object *bo;
++ void __user *data;
++ int ret;
++ int presumed_offset_correct;
++};
+
-+ task->feedback = *feedback;
+
-+ /*
-+ * Hand the task over to the scheduler.
-+ */
++#define PSB_REG_GRAN_SHIFT 2
++#define PSB_REG_GRANULARITY (1 << PSB_REG_GRAN_SHIFT)
++#define PSB_MAX_REG 0x1000
+
-+ spin_lock_irqsave(&scheduler->lock, irq_flags);
-+ task->sequence = psb_fence_advance_sequence(dev, PSB_ENGINE_TA);
++static const uint32_t disallowed_ranges[][2] = {
++ {0x0000, 0x0200},
++ {0x0208, 0x0214},
++ {0x021C, 0x0224},
++ {0x0230, 0x0234},
++ {0x0248, 0x024C},
++ {0x0254, 0x0358},
++ {0x0428, 0x0428},
++ {0x0430, 0x043C},
++ {0x0498, 0x04B4},
++ {0x04CC, 0x04D8},
++ {0x04E0, 0x07FC},
++ {0x0804, 0x0A58},
++ {0x0A68, 0x0A80},
++ {0x0AA0, 0x0B1C},
++ {0x0B2C, 0x0CAC},
++ {0x0CB4, PSB_MAX_REG - PSB_REG_GRANULARITY}
++};
+
-+ psb_report_fence(scheduler, PSB_ENGINE_TA, task->sequence, 0, 1);
++static uint32_t psb_disallowed_regs[PSB_MAX_REG /
++ (PSB_REG_GRANULARITY *
++ (sizeof(uint32_t) << 3))];
+
-+ task->ta_complete_action = PSB_RASTER;
-+ task->raster_complete_action = PSB_RETURN;
++static inline int psb_disallowed(uint32_t reg)
++{
++ reg >>= PSB_REG_GRAN_SHIFT;
++ return ((psb_disallowed_regs[reg >> 5] & (1 << (reg & 31))) != 0);
++}
+
-+ list_add_tail(&task->head, &scheduler->ta_queue);
-+ PSB_DEBUG_RENDER("queued ta %u\n", task->sequence);
++void psb_init_disallowed(void)
++{
++ int i;
++ uint32_t reg, tmp;
++ static int initialized = 0;
+
-+ psb_schedule_ta(dev_priv, scheduler);
-+ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
++ if (initialized)
++ return;
+
-+ psb_fence_or_sync(priv, PSB_ENGINE_TA, arg, fence_arg, &fence);
-+ drm_regs_fence(&dev_priv->use_manager, fence);
-+ if (fence)
-+ fence_arg->signaled |= 0x1;
++ initialized = 1;
++ memset(psb_disallowed_regs, 0, sizeof(psb_disallowed_regs));
+
-+ out_err:
-+ if (ret && ret != -EAGAIN)
-+ DRM_ERROR("TA task queue job failed.\n");
++ for (i = 0; i < (sizeof(disallowed_ranges) / (2 * sizeof(uint32_t)));
++ ++i) {
++ for (reg = disallowed_ranges[i][0];
++ reg <= disallowed_ranges[i][1]; reg += 4) {
++ tmp = reg >> 2;
++ psb_disallowed_regs[tmp >> 5] |= (1 << (tmp & 31));
++ }
++ }
++}
+
-+ if (fence) {
-+#ifdef PSB_WAIT_FOR_TA_COMPLETION
-+ drm_fence_object_wait(fence, 1, 1, DRM_FENCE_TYPE_EXE |
-+ _PSB_FENCE_TYPE_TA_DONE);
-+#ifdef PSB_BE_PARANOID
-+ drm_fence_object_wait(fence, 1, 1, DRM_FENCE_TYPE_EXE |
-+ _PSB_FENCE_TYPE_SCENE_DONE);
-+#endif
-+#endif
-+ drm_fence_usage_deref_unlocked(&fence);
++static int psb_memcpy_check(uint32_t * dst, const uint32_t * src, uint32_t size)
++{
++ size >>= 3;
++ while (size--) {
++ if (unlikely((*src >= 0x1000) || psb_disallowed(*src))) {
++ DRM_ERROR("Forbidden SGX register access: "
++ "0x%04x.\n", *src);
++ return -EPERM;
++ }
++ *dst++ = *src++;
++ *dst++ = *src++;
+ }
-+ mutex_unlock(&dev_priv->reset_mutex);
++ return 0;
++}
++
++static int psb_2d_wait_available(struct drm_psb_private *dev_priv,
++ unsigned size)
++{
++ uint32_t avail = PSB_RSGX32(PSB_CR_2D_SOCIF);
++ int ret = 0;
++
++ retry:
++ if (avail < size) {
++#if 0
++ /* We'd ideally
++ * like to have an IRQ-driven event here.
++ */
+
++ psb_2D_irq_on(dev_priv);
++ DRM_WAIT_ON(ret, dev_priv->event_2d_queue, DRM_HZ,
++ ((avail = PSB_RSGX32(PSB_CR_2D_SOCIF)) >= size));
++ psb_2D_irq_off(dev_priv);
++ if (ret == 0)
++ return 0;
++ if (ret == -EINTR) {
++ ret = 0;
++ goto retry;
++ }
++#else
++ avail = PSB_RSGX32(PSB_CR_2D_SOCIF);
++ goto retry;
++#endif
++ }
+ return ret;
+}
+
-+int psb_cmdbuf_raster(struct drm_file *priv,
-+ struct drm_psb_cmdbuf_arg *arg,
-+ struct drm_buffer_object *cmd_buffer,
-+ struct drm_fence_arg *fence_arg)
++int psb_2d_submit(struct drm_psb_private *dev_priv, uint32_t * cmdbuf,
++ unsigned size)
+{
-+ struct drm_device *dev = priv->minor->dev;
-+ struct drm_psb_private *dev_priv = dev->dev_private;
-+ struct drm_fence_object *fence = NULL;
-+ struct psb_task *task = NULL;
-+ int ret;
-+ struct psb_scheduler *scheduler = &dev_priv->scheduler;
-+ unsigned long irq_flags;
++ int ret = 0;
++ int i;
++ unsigned submit_size;
+
-+ PSB_DEBUG_RENDER("Cmdbuf Raster\n");
++ while (size > 0) {
++ submit_size = (size < 0x60) ? size : 0x60;
++ size -= submit_size;
++ ret = psb_2d_wait_available(dev_priv, submit_size);
++ if (ret)
++ return ret;
+
-+ ret = mutex_lock_interruptible(&dev_priv->reset_mutex);
-+ if (ret)
-+ return -EAGAIN;
++ submit_size <<= 2;
+
-+ mutex_lock(&dev->struct_mutex);
-+ ret = psb_setup_task_devlocked(dev, arg, cmd_buffer, NULL, NULL,
-+ NULL, psb_raster_task,
-+ PSB_ENGINE_TA, 0, &task);
-+ mutex_unlock(&dev->struct_mutex);
++ for (i = 0; i < submit_size; i += 4) {
++ PSB_WSGX32(*cmdbuf++, PSB_SGX_2D_SLAVE_PORT + i);
++ }
++ (void)PSB_RSGX32(PSB_SGX_2D_SLAVE_PORT + i - 4);
++ }
++ return 0;
++}
+
-+ if (ret)
-+ goto out_err;
++int psb_blit_sequence(struct drm_psb_private *dev_priv, uint32_t sequence)
++{
++ uint32_t buffer[8];
++ uint32_t *bufp = buffer;
++ int ret;
+
-+ /*
-+ * Hand the task over to the scheduler.
-+ */
++ *bufp++ = PSB_2D_FENCE_BH;
+
-+ spin_lock_irqsave(&scheduler->lock, irq_flags);
-+ task->sequence = psb_fence_advance_sequence(dev, PSB_ENGINE_TA);
-+ psb_report_fence(scheduler, PSB_ENGINE_TA, task->sequence, 0, 1);
-+ task->ta_complete_action = PSB_RASTER;
-+ task->raster_complete_action = PSB_RETURN;
++ *bufp++ = PSB_2D_DST_SURF_BH |
++ PSB_2D_DST_8888ARGB | (4 << PSB_2D_DST_STRIDE_SHIFT);
++ *bufp++ = dev_priv->comm_mmu_offset - dev_priv->mmu_2d_offset;
+
-+ list_add_tail(&task->head, &scheduler->ta_queue);
-+ PSB_DEBUG_RENDER("queued raster %u\n", task->sequence);
-+ psb_schedule_ta(dev_priv, scheduler);
-+ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
++ *bufp++ = PSB_2D_BLIT_BH |
++ PSB_2D_ROT_NONE |
++ PSB_2D_COPYORDER_TL2BR |
++ PSB_2D_DSTCK_DISABLE |
++ PSB_2D_SRCCK_DISABLE | PSB_2D_USE_FILL | PSB_2D_ROP3_PATCOPY;
+
-+ psb_fence_or_sync(priv, PSB_ENGINE_TA, arg, fence_arg, &fence);
-+ drm_regs_fence(&dev_priv->use_manager, fence);
-+ if (fence)
-+ fence_arg->signaled |= 0x1;
-+ out_err:
-+ if (ret && ret != -EAGAIN)
-+ DRM_ERROR("Raster task queue job failed.\n");
++ *bufp++ = sequence << PSB_2D_FILLCOLOUR_SHIFT;
++ *bufp++ = (0 << PSB_2D_DST_XSTART_SHIFT) |
++ (0 << PSB_2D_DST_YSTART_SHIFT);
++ *bufp++ = (1 << PSB_2D_DST_XSIZE_SHIFT) | (1 << PSB_2D_DST_YSIZE_SHIFT);
+
-+ if (fence) {
-+#ifdef PSB_WAIT_FOR_RASTER_COMPLETION
-+ drm_fence_object_wait(fence, 1, 1, fence->type);
-+#endif
-+ drm_fence_usage_deref_unlocked(&fence);
-+ }
++ *bufp++ = PSB_2D_FLUSH_BH;
+
-+ mutex_unlock(&dev_priv->reset_mutex);
++ psb_2d_lock(dev_priv);
++ ret = psb_2d_submit(dev_priv, buffer, bufp - buffer);
++ psb_2d_unlock(dev_priv);
+
++ if (!ret)
++ psb_schedule_watchdog(dev_priv);
+ return ret;
+}
+
-+#ifdef FIX_TG_16
-+
-+static int psb_check_2d_idle(struct drm_psb_private *dev_priv)
++int psb_emit_2d_copy_blit(struct drm_device *dev,
++ uint32_t src_offset,
++ uint32_t dst_offset, uint32_t pages, int direction)
+{
-+ if (psb_2d_trylock(dev_priv)) {
-+ if ((PSB_RSGX32(PSB_CR_2D_SOCIF) == _PSB_C2_SOCIF_EMPTY) &&
-+ !((PSB_RSGX32(PSB_CR_2D_BLIT_STATUS) &
-+ _PSB_C2B_STATUS_BUSY))) {
-+ return 0;
-+ }
-+ if (atomic_cmpxchg(&dev_priv->ta_wait_2d_irq, 0, 1) == 0)
-+ psb_2D_irq_on(dev_priv);
++ uint32_t cur_pages;
++ struct drm_psb_private *dev_priv = dev->dev_private;
++ uint32_t buf[10];
++ uint32_t *bufp;
++ uint32_t xstart;
++ uint32_t ystart;
++ uint32_t blit_cmd;
++ uint32_t pg_add;
++ int ret = 0;
+
-+ PSB_WSGX32(PSB_2D_FENCE_BH, PSB_SGX_2D_SLAVE_PORT);
-+ PSB_WSGX32(PSB_2D_FLUSH_BH, PSB_SGX_2D_SLAVE_PORT);
-+ (void)PSB_RSGX32(PSB_SGX_2D_SLAVE_PORT);
++ if (!dev_priv)
++ return 0;
+
-+ psb_2d_atomic_unlock(dev_priv);
++ if (direction) {
++ pg_add = (pages - 1) << PAGE_SHIFT;
++ src_offset += pg_add;
++ dst_offset += pg_add;
+ }
+
-+ atomic_set(&dev_priv->ta_wait_2d, 1);
-+ return -EBUSY;
-+}
++ blit_cmd = PSB_2D_BLIT_BH |
++ PSB_2D_ROT_NONE |
++ PSB_2D_DSTCK_DISABLE |
++ PSB_2D_SRCCK_DISABLE |
++ PSB_2D_USE_PAT |
++ PSB_2D_ROP3_SRCCOPY |
++ (direction ? PSB_2D_COPYORDER_BR2TL : PSB_2D_COPYORDER_TL2BR);
++ xstart = (direction) ? ((PAGE_SIZE - 1) >> 2) : 0;
+
-+static void psb_atomic_resume_ta_2d_idle(struct drm_psb_private *dev_priv)
-+{
-+ struct psb_scheduler *scheduler = &dev_priv->scheduler;
++ psb_2d_lock(dev_priv);
++ while (pages > 0) {
++ cur_pages = pages;
++ if (cur_pages > 2048)
++ cur_pages = 2048;
++ pages -= cur_pages;
++ ystart = (direction) ? cur_pages - 1 : 0;
+
-+ if (atomic_cmpxchg(&dev_priv->ta_wait_2d, 1, 0) == 1) {
-+ psb_schedule_ta(dev_priv, scheduler);
-+ if (atomic_read(&dev_priv->waiters_2d) != 0)
-+ wake_up(&dev_priv->queue_2d);
-+ }
-+}
++ bufp = buf;
++ *bufp++ = PSB_2D_FENCE_BH;
+
-+void psb_resume_ta_2d_idle(struct drm_psb_private *dev_priv)
-+{
-+ struct psb_scheduler *scheduler = &dev_priv->scheduler;
-+ unsigned long irq_flags;
++ *bufp++ = PSB_2D_DST_SURF_BH | PSB_2D_DST_8888ARGB |
++ (PAGE_SIZE << PSB_2D_DST_STRIDE_SHIFT);
++ *bufp++ = dst_offset;
++ *bufp++ = PSB_2D_SRC_SURF_BH | PSB_2D_SRC_8888ARGB |
++ (PAGE_SIZE << PSB_2D_SRC_STRIDE_SHIFT);
++ *bufp++ = src_offset;
++ *bufp++ =
++ PSB_2D_SRC_OFF_BH | (xstart << PSB_2D_SRCOFF_XSTART_SHIFT) |
++ (ystart << PSB_2D_SRCOFF_YSTART_SHIFT);
++ *bufp++ = blit_cmd;
++ *bufp++ = (xstart << PSB_2D_DST_XSTART_SHIFT) |
++ (ystart << PSB_2D_DST_YSTART_SHIFT);
++ *bufp++ = ((PAGE_SIZE >> 2) << PSB_2D_DST_XSIZE_SHIFT) |
++ (cur_pages << PSB_2D_DST_YSIZE_SHIFT);
+
-+ spin_lock_irqsave(&scheduler->lock, irq_flags);
-+ if (atomic_cmpxchg(&dev_priv->ta_wait_2d_irq, 1, 0) == 1) {
-+ atomic_set(&dev_priv->ta_wait_2d, 0);
-+ psb_2D_irq_off(dev_priv);
-+ psb_schedule_ta(dev_priv, scheduler);
-+ if (atomic_read(&dev_priv->waiters_2d) != 0)
-+ wake_up(&dev_priv->queue_2d);
++ ret = psb_2d_submit(dev_priv, buf, bufp - buf);
++ if (ret)
++ goto out;
++ pg_add = (cur_pages << PAGE_SHIFT) * ((direction) ? -1 : 1);
++ src_offset += pg_add;
++ dst_offset += pg_add;
+ }
-+ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
++ out:
++ psb_2d_unlock(dev_priv);
++ return ret;
+}
+
-+/*
-+ * 2D locking functions. Can't use a mutex since the trylock() and
-+ * unlock() methods need to be accessible from interrupt context.
-+ */
-+
-+static int psb_2d_trylock(struct drm_psb_private *dev_priv)
++void psb_init_2d(struct drm_psb_private *dev_priv)
+{
-+ return (atomic_cmpxchg(&dev_priv->lock_2d, 0, 1) == 0);
++ dev_priv->sequence_lock = SPIN_LOCK_UNLOCKED;
++ psb_reset(dev_priv, 1);
++ dev_priv->mmu_2d_offset = dev_priv->pg->gatt_start;
++ PSB_WSGX32(dev_priv->mmu_2d_offset, PSB_CR_BIF_TWOD_REQ_BASE);
++ (void)PSB_RSGX32(PSB_CR_BIF_TWOD_REQ_BASE);
+}
+
-+static void psb_2d_atomic_unlock(struct drm_psb_private *dev_priv)
++int psb_idle_2d(struct drm_device *dev)
+{
-+ atomic_set(&dev_priv->lock_2d, 0);
-+ if (atomic_read(&dev_priv->waiters_2d) != 0)
-+ wake_up(&dev_priv->queue_2d);
-+}
++ struct drm_psb_private *dev_priv = dev->dev_private;
++ unsigned long _end = jiffies + DRM_HZ;
++ int busy = 0;
+
-+void psb_2d_unlock(struct drm_psb_private *dev_priv)
++ /*
++ * First idle the 2D engine.
++ */
++
++ if (dev_priv->engine_lockup_2d)
++ return -EBUSY;
++
++ if ((PSB_RSGX32(PSB_CR_2D_SOCIF) == _PSB_C2_SOCIF_EMPTY) &&
++ ((PSB_RSGX32(PSB_CR_2D_BLIT_STATUS) & _PSB_C2B_STATUS_BUSY) == 0))
++ goto out;
++
++ do {
++ busy = (PSB_RSGX32(PSB_CR_2D_SOCIF) != _PSB_C2_SOCIF_EMPTY);
++ } while (busy && !time_after_eq(jiffies, _end));
++
++ if (busy)
++ busy = (PSB_RSGX32(PSB_CR_2D_SOCIF) != _PSB_C2_SOCIF_EMPTY);
++ if (busy)
++ goto out;
++
++ do {
++ busy =
++ ((PSB_RSGX32(PSB_CR_2D_BLIT_STATUS) & _PSB_C2B_STATUS_BUSY)
++ != 0);
++ } while (busy && !time_after_eq(jiffies, _end));
++ if (busy)
++ busy =
++ ((PSB_RSGX32(PSB_CR_2D_BLIT_STATUS) & _PSB_C2B_STATUS_BUSY)
++ != 0);
++
++ out:
++ if (busy)
++ dev_priv->engine_lockup_2d = 1;
++
++ return (busy) ? -EBUSY : 0;
++}
++
++int psb_idle_3d(struct drm_device *dev)
+{
++ struct drm_psb_private *dev_priv = dev->dev_private;
+ struct psb_scheduler *scheduler = &dev_priv->scheduler;
-+ unsigned long irq_flags;
++ int ret;
+
-+ spin_lock_irqsave(&scheduler->lock, irq_flags);
-+ psb_2d_atomic_unlock(dev_priv);
-+ if (atomic_read(&dev_priv->ta_wait_2d) != 0)
-+ psb_atomic_resume_ta_2d_idle(dev_priv);
-+ spin_unlock_irqrestore(&scheduler->lock, irq_flags);
++ ret = wait_event_timeout(scheduler->idle_queue,
++ psb_scheduler_finished(dev_priv), DRM_HZ * 10);
++
++ return (ret < 1) ? -EBUSY : 0;
+}
+
-+void psb_2d_lock(struct drm_psb_private *dev_priv)
++static void psb_dereference_buffers_locked(struct psb_buflist_item *buffers,
++ unsigned num_buffers)
+{
-+ atomic_inc(&dev_priv->waiters_2d);
-+ wait_event(dev_priv->queue_2d, atomic_read(&dev_priv->ta_wait_2d) == 0);
-+ wait_event(dev_priv->queue_2d, psb_2d_trylock(dev_priv));
-+ atomic_dec(&dev_priv->waiters_2d);
++ while (num_buffers--)
++ drm_bo_usage_deref_locked(&((buffers++)->bo));
++
+}
+
-+#endif
-Index: linux-2.6.28/drivers/gpu/drm/psb/psb_schedule.h
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/psb/psb_schedule.h 2009-02-12 09:14:42.000000000 +0000
-@@ -0,0 +1,170 @@
-+/**************************************************************************
-+ * Copyright (c) 2007, Intel Corporation.
-+ * All Rights Reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms and conditions of the GNU General Public License,
-+ * version 2, as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
-+ *
-+ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
-+ * develop this driver.
-+ *
-+ **************************************************************************/
-+/*
-+ * Authors: Thomas Hellstrom <thomas-at-tungstengraphics.com>
-+ */
++static int psb_check_presumed(struct drm_bo_op_arg *arg,
++ struct drm_buffer_object *bo,
++ uint32_t __user * data, int *presumed_ok)
++{
++ struct drm_bo_op_req *req = &arg->d.req;
++ uint32_t hint_offset;
++ uint32_t hint = req->bo_req.hint;
+
-+#ifndef _PSB_SCHEDULE_H_
-+#define _PSB_SCHEDULE_H_
++ *presumed_ok = 0;
+
-+#include "drmP.h"
++ if (!(hint & DRM_BO_HINT_PRESUMED_OFFSET))
++ return 0;
++ if (bo->mem.mem_type == DRM_BO_MEM_LOCAL) {
++ *presumed_ok = 1;
++ return 0;
++ }
++ if (bo->offset == req->bo_req.presumed_offset) {
++ *presumed_ok = 1;
++ return 0;
++ }
+
-+enum psb_task_type {
-+ psb_ta_midscene_task,
-+ psb_ta_task,
-+ psb_raster_task,
-+ psb_freescene_task
-+};
++ /*
++ * We need to turn off the HINT_PRESUMED_OFFSET for this buffer in
++ * the user-space IOCTL argument list, since the buffer has moved,
++ * we're about to apply relocations and we might subsequently
++ * hit an -EAGAIN. In that case the argument list will be reused by
++ * user-space, but the presumed offset is no longer valid.
++ *
++ * Needless to say, this is a bit ugly.
++ */
+
-+#define PSB_MAX_TA_CMDS 60
-+#define PSB_MAX_RASTER_CMDS 60
-+#define PSB_MAX_OOM_CMDS 6
++ hint_offset = (uint32_t *) & req->bo_req.hint - (uint32_t *) arg;
++ hint &= ~DRM_BO_HINT_PRESUMED_OFFSET;
++ return __put_user(hint, data + hint_offset);
++}
+
-+struct psb_xhw_buf {
-+ struct list_head head;
-+ int copy_back;
-+ atomic_t done;
-+ struct drm_psb_xhw_arg arg;
++static int psb_validate_buffer_list(struct drm_file *file_priv,
++ unsigned fence_class,
++ unsigned long data,
++ struct psb_buflist_item *buffers,
++ unsigned *num_buffers)
++{
++ struct drm_bo_op_arg arg;
++ struct drm_bo_op_req *req = &arg.d.req;
++ int ret = 0;
++ unsigned buf_count = 0;
++ struct psb_buflist_item *item = buffers;
+
-+};
++ do {
++ if (buf_count >= *num_buffers) {
++ DRM_ERROR("Buffer count exceeded %d\n.", *num_buffers);
++ ret = -EINVAL;
++ goto out_err;
++ }
++ item = buffers + buf_count;
++ item->bo = NULL;
+
-+struct psb_feedback_info {
-+ struct drm_buffer_object *bo;
-+ struct page *page;
-+ uint32_t offset;
-+};
++ if (copy_from_user(&arg, (void __user *)data, sizeof(arg))) {
++ ret = -EFAULT;
++ DRM_ERROR("Error copying validate list.\n"
++ "\tbuffer %d, user addr 0x%08lx %d\n",
++ buf_count, (unsigned long)data, sizeof(arg));
++ goto out_err;
++ }
+
-+struct psb_task {
-+ struct list_head head;
-+ struct psb_scene *scene;
-+ struct psb_feedback_info feedback;
-+ enum psb_task_type task_type;
-+ uint32_t engine;
-+ uint32_t sequence;
-+ uint32_t ta_cmds[PSB_MAX_TA_CMDS];
-+ uint32_t raster_cmds[PSB_MAX_RASTER_CMDS];
-+ uint32_t oom_cmds[PSB_MAX_OOM_CMDS];
-+ uint32_t ta_cmd_size;
-+ uint32_t raster_cmd_size;
-+ uint32_t oom_cmd_size;
-+ uint32_t feedback_offset;
-+ uint32_t ta_complete_action;
-+ uint32_t raster_complete_action;
-+ uint32_t hw_cookie;
-+ uint32_t flags;
-+ uint32_t reply_flags;
-+ uint32_t aborting;
-+ struct psb_xhw_buf buf;
-+};
++ ret = 0;
++ if (req->op != drm_bo_validate) {
++ DRM_ERROR
++ ("Buffer object operation wasn't \"validate\".\n");
++ ret = -EINVAL;
++ goto out_err;
++ }
+
-+struct psb_hw_scene {
-+ struct list_head head;
-+ uint32_t context_number;
++ item->ret = 0;
++ item->data = (void *)__user data;
++ ret = drm_bo_handle_validate(file_priv,
++ req->bo_req.handle,
++ fence_class,
++ req->bo_req.flags,
++ req->bo_req.mask,
++ req->bo_req.hint,
++ 0, NULL, &item->bo);
++ if (ret)
++ goto out_err;
+
-+ /*
-+ * This pointer does not refcount the last_scene_buffer,
-+ * so we must make sure it is set to NULL before destroying
-+ * the corresponding task.
-+ */
++ PSB_DEBUG_GENERAL("Validated buffer at 0x%08lx\n",
++ buffers[buf_count].bo->offset);
+
-+ struct psb_scene *last_scene;
-+};
++ buf_count++;
+
-+struct psb_scene;
-+struct drm_psb_private;
+
-+struct psb_scheduler_seq {
-+ uint32_t sequence;
-+ int reported;
-+};
++ ret = psb_check_presumed(&arg, item->bo,
++ (uint32_t __user *)
++ (unsigned long) data,
++ &item->presumed_offset_correct);
+
-+struct psb_scheduler {
-+ struct drm_device *dev;
-+ struct psb_scheduler_seq seq[_PSB_ENGINE_TA_FENCE_TYPES];
-+ struct psb_hw_scene hs[PSB_NUM_HW_SCENES];
-+ struct mutex task_wq_mutex;
-+ spinlock_t lock;
-+ struct list_head hw_scenes;
-+ struct list_head ta_queue;
-+ struct list_head raster_queue;
-+ struct list_head hp_raster_queue;
-+ struct list_head task_done_queue;
-+ struct psb_task *current_task[PSB_SCENE_NUM_ENGINES];
-+ struct psb_task *feedback_task;
-+ int ta_state;
-+ struct psb_hw_scene *pending_hw_scene;
-+ uint32_t pending_hw_scene_seq;
-+ struct delayed_work wq;
-+ struct psb_scene_pool *pool;
-+ uint32_t idle_count;
-+ int idle;
-+ wait_queue_head_t idle_queue;
-+ unsigned long ta_end_jiffies;
-+ unsigned long raster_end_jiffies;
-+ unsigned long total_raster_jiffies;
-+};
++ if (ret)
++ goto out_err;
+
-+#define PSB_RF_FIRE_TA (1 << 0)
-+#define PSB_RF_OOM (1 << 1)
-+#define PSB_RF_OOM_REPLY (1 << 2)
-+#define PSB_RF_TERMINATE (1 << 3)
-+#define PSB_RF_TA_DONE (1 << 4)
-+#define PSB_RF_FIRE_RASTER (1 << 5)
-+#define PSB_RF_RASTER_DONE (1 << 6)
-+#define PSB_RF_DEALLOC (1 << 7)
++ data = arg.next;
++ } while (data);
+
-+extern struct psb_scene_pool *psb_alloc_scene_pool(struct drm_file *priv,
-+ int shareable, uint32_t w,
-+ uint32_t h);
-+extern uint32_t psb_scene_handle(struct psb_scene *scene);
-+extern int psb_scheduler_init(struct drm_device *dev,
-+ struct psb_scheduler *scheduler);
-+extern void psb_scheduler_takedown(struct psb_scheduler *scheduler);
-+extern int psb_cmdbuf_ta(struct drm_file *priv,
-+ struct drm_psb_cmdbuf_arg *arg,
-+ struct drm_buffer_object *cmd_buffer,
-+ struct drm_buffer_object *ta_buffer,
-+ struct drm_buffer_object *oom_buffer,
-+ struct psb_scene *scene,
-+ struct psb_feedback_info *feedback,
-+ struct drm_fence_arg *fence_arg);
-+extern int psb_cmdbuf_raster(struct drm_file *priv,
-+ struct drm_psb_cmdbuf_arg *arg,
-+ struct drm_buffer_object *cmd_buffer,
-+ struct drm_fence_arg *fence_arg);
-+extern void psb_scheduler_handler(struct drm_psb_private *dev_priv,
-+ uint32_t status);
-+extern void psb_scheduler_pause(struct drm_psb_private *dev_priv);
-+extern void psb_scheduler_restart(struct drm_psb_private *dev_priv);
-+extern int psb_scheduler_idle(struct drm_psb_private *dev_priv);
-+extern int psb_scheduler_finished(struct drm_psb_private *dev_priv);
++ *num_buffers = buf_count;
+
-+extern void psb_scheduler_lockup(struct drm_psb_private *dev_priv,
-+ int *lockup, int *idle);
-+extern void psb_scheduler_reset(struct drm_psb_private *dev_priv,
-+ int error_condition);
-+extern int psb_forced_user_interrupt(struct drm_psb_private *dev_priv);
-+extern void psb_scheduler_remove_scene_refs(struct psb_scene *scene);
-+extern void psb_scheduler_ta_mem_check(struct drm_psb_private *dev_priv);
-+extern int psb_extend_raster_timeout(struct drm_psb_private *dev_priv);
++ return 0;
++ out_err:
+
-+#endif
-Index: linux-2.6.28/drivers/gpu/drm/psb/psb_setup.c
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/psb/psb_setup.c 2009-02-12 09:14:42.000000000 +0000
-@@ -0,0 +1,18 @@
-+#include "drmP.h"
-+#include "drm.h"
-+#include "drm_crtc.h"
-+#include "drm_edid.h"
-+#include "psb_drm.h"
-+#include "psb_priv.h"
-+//#include "i915_reg.h"
-+//#include "intel_drv.h"
-+#include "../i915/intel_crt.c"
++ *num_buffers = buf_count;
++ item->ret = (ret != -EAGAIN) ? ret : 0;
++ return ret;
++}
+
-+/* Fixed name */
-+#define ACPI_EDID_LCD "\\_SB_.PCI0.GFX0.DD04._DDC"
-+#define ACPI_DOD "\\_SB_.PCI0.GFX0._DOD"
++int
++psb_reg_submit(struct drm_psb_private *dev_priv, uint32_t * regs,
++ unsigned int cmds)
++{
++ int i;
++
++ /*
++ * cmds is 32-bit words.
++ */
++
++ cmds >>= 1;
++ for (i = 0; i < cmds; ++i) {
++ PSB_WSGX32(regs[1], regs[0]);
++ regs += 2;
++ }
++ wmb();
++ return 0;
++}
+
-+#include "../i915/intel_lvds.c"
-+#include "../i915/intel_sdvo.c"
-+#include "intel_display.c"
-+#include "../i915/intel_modes.c"
-Index: linux-2.6.28/drivers/gpu/drm/psb/psb_sgx.c
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/psb/psb_sgx.c 2009-02-12 09:14:42.000000000 +0000
-@@ -0,0 +1,1422 @@
-+/**************************************************************************
-+ * Copyright (c) 2007, Intel Corporation.
-+ * All Rights Reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms and conditions of the GNU General Public License,
-+ * version 2, as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
-+ *
-+ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
-+ * develop this driver.
-+ *
-+ **************************************************************************/
+/*
++ * Security: Block user-space writing to MMU mapping registers.
++ * This is important for security and brings Poulsbo DRM
++ * up to par with the other DRM drivers. Using this,
++ * user-space should not be able to map arbitrary memory
++ * pages to graphics memory, but all user-space processes
++ * basically have access to all buffer objects mapped to
++ * graphics memory.
+ */
+
-+#include "drmP.h"
-+#include "psb_drv.h"
-+#include "psb_drm.h"
-+#include "psb_reg.h"
-+#include "psb_scene.h"
-+
-+#include "psb_msvdx.h"
++int
++psb_submit_copy_cmdbuf(struct drm_device *dev,
++ struct drm_buffer_object *cmd_buffer,
++ unsigned long cmd_offset,
++ unsigned long cmd_size,
++ int engine, uint32_t * copy_buffer)
++{
++ unsigned long cmd_end = cmd_offset + (cmd_size << 2);
++ struct drm_psb_private *dev_priv = dev->dev_private;
++ unsigned long cmd_page_offset = cmd_offset - (cmd_offset & PAGE_MASK);
++ unsigned long cmd_next;
++ struct drm_bo_kmap_obj cmd_kmap;
++ uint32_t *cmd_page;
++ unsigned cmds;
++ int is_iomem;
++ int ret = 0;
+
-+int psb_submit_video_cmdbuf(struct drm_device *dev,
-+ struct drm_buffer_object *cmd_buffer,
-+ unsigned long cmd_offset, unsigned long cmd_size,
-+ struct drm_fence_object *fence);
++ if (cmd_size == 0)
++ return 0;
+
-+struct psb_dstbuf_cache {
-+ unsigned int dst;
-+ uint32_t *use_page;
-+ unsigned int use_index;
-+ uint32_t use_background;
-+ struct drm_buffer_object *dst_buf;
-+ unsigned long dst_offset;
-+ uint32_t *dst_page;
-+ unsigned int dst_page_offset;
-+ struct drm_bo_kmap_obj dst_kmap;
-+ int dst_is_iomem;
-+};
++ if (engine == PSB_ENGINE_2D)
++ psb_2d_lock(dev_priv);
+
-+struct psb_buflist_item {
-+ struct drm_buffer_object *bo;
-+ void __user *data;
-+ int ret;
-+ int presumed_offset_correct;
-+};
++ do {
++ cmd_next = drm_bo_offset_end(cmd_offset, cmd_end);
++ ret = drm_bo_kmap(cmd_buffer, cmd_offset >> PAGE_SHIFT,
++ 1, &cmd_kmap);
+
++ if (ret)
++ return ret;
++ cmd_page = drm_bmo_virtual(&cmd_kmap, &is_iomem);
++ cmd_page_offset = (cmd_offset & ~PAGE_MASK) >> 2;
++ cmds = (cmd_next - cmd_offset) >> 2;
+
-+#define PSB_REG_GRAN_SHIFT 2
-+#define PSB_REG_GRANULARITY (1 << PSB_REG_GRAN_SHIFT)
-+#define PSB_MAX_REG 0x1000
++ switch (engine) {
++ case PSB_ENGINE_2D:
++ ret =
++ psb_2d_submit(dev_priv, cmd_page + cmd_page_offset,
++ cmds);
++ break;
++ case PSB_ENGINE_RASTERIZER:
++ case PSB_ENGINE_TA:
++ case PSB_ENGINE_HPRAST:
++ PSB_DEBUG_GENERAL("Reg copy.\n");
++ ret = psb_memcpy_check(copy_buffer,
++ cmd_page + cmd_page_offset,
++ cmds * sizeof(uint32_t));
++ copy_buffer += cmds;
++ break;
++ default:
++ ret = -EINVAL;
++ }
++ drm_bo_kunmap(&cmd_kmap);
++ if (ret)
++ break;
++ } while (cmd_offset = cmd_next, cmd_offset != cmd_end);
+
-+static const uint32_t disallowed_ranges[][2] = {
-+ {0x0000, 0x0200},
-+ {0x0208, 0x0214},
-+ {0x021C, 0x0224},
-+ {0x0230, 0x0234},
-+ {0x0248, 0x024C},
-+ {0x0254, 0x0358},
-+ {0x0428, 0x0428},
-+ {0x0430, 0x043C},
-+ {0x0498, 0x04B4},
-+ {0x04CC, 0x04D8},
-+ {0x04E0, 0x07FC},
-+ {0x0804, 0x0A58},
-+ {0x0A68, 0x0A80},
-+ {0x0AA0, 0x0B1C},
-+ {0x0B2C, 0x0CAC},
-+ {0x0CB4, PSB_MAX_REG - PSB_REG_GRANULARITY}
-+};
++ if (engine == PSB_ENGINE_2D)
++ psb_2d_unlock(dev_priv);
+
-+static uint32_t psb_disallowed_regs[PSB_MAX_REG /
-+ (PSB_REG_GRANULARITY *
-+ (sizeof(uint32_t) << 3))];
++ return ret;
++}
+
-+static inline int psb_disallowed(uint32_t reg)
++static void psb_clear_dstbuf_cache(struct psb_dstbuf_cache *dst_cache)
+{
-+ reg >>= PSB_REG_GRAN_SHIFT;
-+ return ((psb_disallowed_regs[reg >> 5] & (1 << (reg & 31))) != 0);
++ if (dst_cache->dst_page) {
++ drm_bo_kunmap(&dst_cache->dst_kmap);
++ dst_cache->dst_page = NULL;
++ }
++ dst_cache->dst_buf = NULL;
++ dst_cache->dst = ~0;
++ dst_cache->use_page = NULL;
+}
+
-+void psb_init_disallowed(void)
++static int psb_update_dstbuf_cache(struct psb_dstbuf_cache *dst_cache,
++ struct psb_buflist_item *buffers,
++ unsigned int dst, unsigned long dst_offset)
+{
-+ int i;
-+ uint32_t reg, tmp;
-+ static int initialized = 0;
++ int ret;
+
-+ if (initialized)
-+ return;
++ PSB_DEBUG_RELOC("Destination buffer is %d.\n", dst);
+
-+ initialized = 1;
-+ memset(psb_disallowed_regs, 0, sizeof(psb_disallowed_regs));
++ if (unlikely(dst != dst_cache->dst || NULL == dst_cache->dst_buf)) {
++ psb_clear_dstbuf_cache(dst_cache);
++ dst_cache->dst = dst;
++ dst_cache->dst_buf = buffers[dst].bo;
++ }
+
-+ for (i = 0; i < (sizeof(disallowed_ranges) / (2 * sizeof(uint32_t)));
-+ ++i) {
-+ for (reg = disallowed_ranges[i][0];
-+ reg <= disallowed_ranges[i][1]; reg += 4) {
-+ tmp = reg >> 2;
-+ psb_disallowed_regs[tmp >> 5] |= (1 << (tmp & 31));
-+ }
++ if (unlikely(dst_offset > dst_cache->dst_buf->num_pages * PAGE_SIZE)) {
++ DRM_ERROR("Relocation destination out of bounds.\n");
++ return -EINVAL;
+ }
-+}
+
-+static int psb_memcpy_check(uint32_t * dst, const uint32_t * src, uint32_t size)
-+{
-+ size >>= 3;
-+ while (size--) {
-+ if (unlikely((*src >= 0x1000) || psb_disallowed(*src))) {
-+ DRM_ERROR("Forbidden SGX register access: "
-+ "0x%04x.\n", *src);
-+ return -EPERM;
++ if (!drm_bo_same_page(dst_cache->dst_offset, dst_offset) ||
++ NULL == dst_cache->dst_page) {
++ if (NULL != dst_cache->dst_page) {
++ drm_bo_kunmap(&dst_cache->dst_kmap);
++ dst_cache->dst_page = NULL;
+ }
-+ *dst++ = *src++;
-+ *dst++ = *src++;
++
++ ret = drm_bo_kmap(dst_cache->dst_buf, dst_offset >> PAGE_SHIFT,
++ 1, &dst_cache->dst_kmap);
++ if (ret) {
++ DRM_ERROR("Could not map destination buffer for "
++ "relocation.\n");
++ return ret;
++ }
++
++ dst_cache->dst_page = drm_bmo_virtual(&dst_cache->dst_kmap,
++ &dst_cache->dst_is_iomem);
++ dst_cache->dst_offset = dst_offset & PAGE_MASK;
++ dst_cache->dst_page_offset = dst_cache->dst_offset >> 2;
+ }
+ return 0;
+}
+
-+static int psb_2d_wait_available(struct drm_psb_private *dev_priv,
-+ unsigned size)
++static int psb_apply_reloc(struct drm_psb_private *dev_priv,
++ uint32_t fence_class,
++ const struct drm_psb_reloc *reloc,
++ struct psb_buflist_item *buffers,
++ int num_buffers,
++ struct psb_dstbuf_cache *dst_cache,
++ int no_wait, int interruptible)
+{
-+ uint32_t avail = PSB_RSGX32(PSB_CR_2D_SOCIF);
-+ int ret = 0;
++ int reg;
++ uint32_t val;
++ uint32_t background;
++ unsigned int index;
++ int ret;
++ unsigned int shift;
++ unsigned int align_shift;
++ uint32_t fence_type;
++ struct drm_buffer_object *reloc_bo;
+
-+ retry:
-+ if (avail < size) {
-+#if 0
-+ /* We'd ideally
-+ * like to have an IRQ-driven event here.
-+ */
++ PSB_DEBUG_RELOC("Reloc type %d\n"
++ "\t where 0x%04x\n"
++ "\t buffer 0x%04x\n"
++ "\t mask 0x%08x\n"
++ "\t shift 0x%08x\n"
++ "\t pre_add 0x%08x\n"
++ "\t background 0x%08x\n"
++ "\t dst_buffer 0x%08x\n"
++ "\t arg0 0x%08x\n"
++ "\t arg1 0x%08x\n",
++ reloc->reloc_op,
++ reloc->where,
++ reloc->buffer,
++ reloc->mask,
++ reloc->shift,
++ reloc->pre_add,
++ reloc->background,
++ reloc->dst_buffer, reloc->arg0, reloc->arg1);
+
-+ psb_2D_irq_on(dev_priv);
-+ DRM_WAIT_ON(ret, dev_priv->event_2d_queue, DRM_HZ,
-+ ((avail = PSB_RSGX32(PSB_CR_2D_SOCIF)) >= size));
-+ psb_2D_irq_off(dev_priv);
-+ if (ret == 0)
-+ return 0;
-+ if (ret == -EINTR) {
-+ ret = 0;
-+ goto retry;
-+ }
-+#else
-+ avail = PSB_RSGX32(PSB_CR_2D_SOCIF);
-+ goto retry;
-+#endif
++ if (unlikely(reloc->buffer >= num_buffers)) {
++ DRM_ERROR("Illegal relocation buffer %d.\n", reloc->buffer);
++ return -EINVAL;
+ }
-+ return ret;
-+}
+
-+int psb_2d_submit(struct drm_psb_private *dev_priv, uint32_t * cmdbuf,
-+ unsigned size)
-+{
-+ int ret = 0;
-+ int i;
-+ unsigned submit_size;
++ if (buffers[reloc->buffer].presumed_offset_correct)
++ return 0;
+
-+ while (size > 0) {
-+ submit_size = (size < 0x60) ? size : 0x60;
-+ size -= submit_size;
-+ ret = psb_2d_wait_available(dev_priv, submit_size);
-+ if (ret)
-+ return ret;
++ if (unlikely(reloc->dst_buffer >= num_buffers)) {
++ DRM_ERROR("Illegal destination buffer for relocation %d.\n",
++ reloc->dst_buffer);
++ return -EINVAL;
++ }
+
-+ submit_size <<= 2;
++ ret = psb_update_dstbuf_cache(dst_cache, buffers, reloc->dst_buffer,
++ reloc->where << 2);
++ if (ret)
++ return ret;
+
-+ for (i = 0; i < submit_size; i += 4) {
-+ PSB_WSGX32(*cmdbuf++, PSB_SGX_2D_SLAVE_PORT + i);
++ reloc_bo = buffers[reloc->buffer].bo;
++
++ if (unlikely(reloc->pre_add > (reloc_bo->num_pages << PAGE_SHIFT))) {
++ DRM_ERROR("Illegal relocation offset add.\n");
++ return -EINVAL;
++ }
++
++ switch (reloc->reloc_op) {
++ case PSB_RELOC_OP_OFFSET:
++ val = reloc_bo->offset + reloc->pre_add;
++ break;
++ case PSB_RELOC_OP_2D_OFFSET:
++ val = reloc_bo->offset + reloc->pre_add -
++ dev_priv->mmu_2d_offset;
++ if (unlikely(val >= PSB_2D_SIZE)) {
++ DRM_ERROR("2D relocation out of bounds\n");
++ return -EINVAL;
+ }
-+ (void)PSB_RSGX32(PSB_SGX_2D_SLAVE_PORT + i - 4);
++ break;
++ case PSB_RELOC_OP_PDS_OFFSET:
++ val = reloc_bo->offset + reloc->pre_add - PSB_MEM_PDS_START;
++ if (unlikely(val >= (PSB_MEM_MMU_START - PSB_MEM_PDS_START))) {
++ DRM_ERROR("PDS relocation out of bounds\n");
++ return -EINVAL;
++ }
++ break;
++ case PSB_RELOC_OP_USE_OFFSET:
++ case PSB_RELOC_OP_USE_REG:
++
++ /*
++ * Security:
++ * Only allow VERTEX or PIXEL data masters, as
++ * shaders run under other data masters may in theory
++ * alter MMU mappings.
++ */
++
++ if (unlikely(reloc->arg1 != _PSB_CUC_DM_PIXEL &&
++ reloc->arg1 != _PSB_CUC_DM_VERTEX)) {
++ DRM_ERROR("Invalid data master in relocation. %d\n",
++ reloc->arg1);
++ return -EPERM;
++ }
++
++ fence_type = reloc_bo->fence_type;
++ ret = psb_grab_use_base(dev_priv,
++ reloc_bo->offset +
++ reloc->pre_add, reloc->arg0,
++ reloc->arg1, fence_class,
++ fence_type, no_wait,
++ interruptible, ®, &val);
++ if (ret)
++ return ret;
++
++ val = (reloc->reloc_op == PSB_RELOC_OP_USE_REG) ? reg : val;
++ break;
++ default:
++ DRM_ERROR("Unimplemented relocation.\n");
++ return -EINVAL;
+ }
-+ return 0;
-+}
+
-+int psb_blit_sequence(struct drm_psb_private *dev_priv, uint32_t sequence)
-+{
-+ uint32_t buffer[8];
-+ uint32_t *bufp = buffer;
-+ int ret;
++ shift = (reloc->shift & PSB_RELOC_SHIFT_MASK) >> PSB_RELOC_SHIFT_SHIFT;
++ align_shift = (reloc->shift & PSB_RELOC_ALSHIFT_MASK) >>
++ PSB_RELOC_ALSHIFT_SHIFT;
+
-+ *bufp++ = PSB_2D_FENCE_BH;
++ val = ((val >> align_shift) << shift);
++ index = reloc->where - dst_cache->dst_page_offset;
+
-+ *bufp++ = PSB_2D_DST_SURF_BH |
-+ PSB_2D_DST_8888ARGB | (4 << PSB_2D_DST_STRIDE_SHIFT);
-+ *bufp++ = dev_priv->comm_mmu_offset - dev_priv->mmu_2d_offset;
++ background = reloc->background;
+
-+ *bufp++ = PSB_2D_BLIT_BH |
-+ PSB_2D_ROT_NONE |
-+ PSB_2D_COPYORDER_TL2BR |
-+ PSB_2D_DSTCK_DISABLE |
-+ PSB_2D_SRCCK_DISABLE | PSB_2D_USE_FILL | PSB_2D_ROP3_PATCOPY;
++ if (reloc->reloc_op == PSB_RELOC_OP_USE_OFFSET) {
++ if (dst_cache->use_page == dst_cache->dst_page &&
++ dst_cache->use_index == index)
++ background = dst_cache->use_background;
++ else
++ background = dst_cache->dst_page[index];
++ }
++#if 0
++ if (dst_cache->dst_page[index] != PSB_RELOC_MAGIC &&
++ reloc->reloc_op != PSB_RELOC_OP_USE_OFFSET)
++ DRM_ERROR("Inconsistent relocation 0x%08lx.\n",
++ (unsigned long)dst_cache->dst_page[index]);
++#endif
+
-+ *bufp++ = sequence << PSB_2D_FILLCOLOUR_SHIFT;
-+ *bufp++ = (0 << PSB_2D_DST_XSTART_SHIFT) |
-+ (0 << PSB_2D_DST_YSTART_SHIFT);
-+ *bufp++ = (1 << PSB_2D_DST_XSIZE_SHIFT) | (1 << PSB_2D_DST_YSIZE_SHIFT);
++ val = (background & ~reloc->mask) | (val & reloc->mask);
++ dst_cache->dst_page[index] = val;
+
-+ *bufp++ = PSB_2D_FLUSH_BH;
++ if (reloc->reloc_op == PSB_RELOC_OP_USE_OFFSET ||
++ reloc->reloc_op == PSB_RELOC_OP_USE_REG) {
++ dst_cache->use_page = dst_cache->dst_page;
++ dst_cache->use_index = index;
++ dst_cache->use_background = val;
++ }
+
-+ psb_2d_lock(dev_priv);
-+ ret = psb_2d_submit(dev_priv, buffer, bufp - buffer);
-+ psb_2d_unlock(dev_priv);
++ PSB_DEBUG_RELOC("Reloc buffer %d index 0x%08x, value 0x%08x\n",
++ reloc->dst_buffer, index, dst_cache->dst_page[index]);
+
-+ if (!ret)
-+ psb_schedule_watchdog(dev_priv);
-+ return ret;
++ return 0;
+}
+
-+int psb_emit_2d_copy_blit(struct drm_device *dev,
-+ uint32_t src_offset,
-+ uint32_t dst_offset, uint32_t pages, int direction)
++static int psb_ok_to_map_reloc(struct drm_psb_private *dev_priv,
++ unsigned int num_pages)
+{
-+ uint32_t cur_pages;
-+ struct drm_psb_private *dev_priv = dev->dev_private;
-+ uint32_t buf[10];
-+ uint32_t *bufp;
-+ uint32_t xstart;
-+ uint32_t ystart;
-+ uint32_t blit_cmd;
-+ uint32_t pg_add;
+ int ret = 0;
+
-+ if (!dev_priv)
-+ return 0;
-+
-+ if (direction) {
-+ pg_add = (pages - 1) << PAGE_SHIFT;
-+ src_offset += pg_add;
-+ dst_offset += pg_add;
++ spin_lock(&dev_priv->reloc_lock);
++ if (dev_priv->rel_mapped_pages + num_pages <= PSB_MAX_RELOC_PAGES) {
++ dev_priv->rel_mapped_pages += num_pages;
++ ret = 1;
+ }
++ spin_unlock(&dev_priv->reloc_lock);
++ return ret;
++}
+
-+ blit_cmd = PSB_2D_BLIT_BH |
-+ PSB_2D_ROT_NONE |
-+ PSB_2D_DSTCK_DISABLE |
-+ PSB_2D_SRCCK_DISABLE |
-+ PSB_2D_USE_PAT |
-+ PSB_2D_ROP3_SRCCOPY |
-+ (direction ? PSB_2D_COPYORDER_BR2TL : PSB_2D_COPYORDER_TL2BR);
-+ xstart = (direction) ? ((PAGE_SIZE - 1) >> 2) : 0;
++static int psb_fixup_relocs(struct drm_file *file_priv,
++ uint32_t fence_class,
++ unsigned int num_relocs,
++ unsigned int reloc_offset,
++ uint32_t reloc_handle,
++ struct psb_buflist_item *buffers,
++ unsigned int num_buffers,
++ int no_wait, int interruptible)
++{
++ struct drm_device *dev = file_priv->minor->dev;
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
++ struct drm_buffer_object *reloc_buffer = NULL;
++ unsigned int reloc_num_pages;
++ unsigned int reloc_first_page;
++ unsigned int reloc_last_page;
++ struct psb_dstbuf_cache dst_cache;
++ struct drm_psb_reloc *reloc;
++ struct drm_bo_kmap_obj reloc_kmap;
++ int reloc_is_iomem;
++ int count;
++ int ret = 0;
++ int registered = 0;
++ int short_circuit = 1;
++ int i;
+
-+ psb_2d_lock(dev_priv);
-+ while (pages > 0) {
-+ cur_pages = pages;
-+ if (cur_pages > 2048)
-+ cur_pages = 2048;
-+ pages -= cur_pages;
-+ ystart = (direction) ? cur_pages - 1 : 0;
++ if (num_relocs == 0)
++ return 0;
+
-+ bufp = buf;
-+ *bufp++ = PSB_2D_FENCE_BH;
++ for (i=0; i<num_buffers; ++i) {
++ if (!buffers[i].presumed_offset_correct) {
++ short_circuit = 0;
++ break;
++ }
++ }
+
-+ *bufp++ = PSB_2D_DST_SURF_BH | PSB_2D_DST_8888ARGB |
-+ (PAGE_SIZE << PSB_2D_DST_STRIDE_SHIFT);
-+ *bufp++ = dst_offset;
-+ *bufp++ = PSB_2D_SRC_SURF_BH | PSB_2D_SRC_8888ARGB |
-+ (PAGE_SIZE << PSB_2D_SRC_STRIDE_SHIFT);
-+ *bufp++ = src_offset;
-+ *bufp++ =
-+ PSB_2D_SRC_OFF_BH | (xstart << PSB_2D_SRCOFF_XSTART_SHIFT) |
-+ (ystart << PSB_2D_SRCOFF_YSTART_SHIFT);
-+ *bufp++ = blit_cmd;
-+ *bufp++ = (xstart << PSB_2D_DST_XSTART_SHIFT) |
-+ (ystart << PSB_2D_DST_YSTART_SHIFT);
-+ *bufp++ = ((PAGE_SIZE >> 2) << PSB_2D_DST_XSIZE_SHIFT) |
-+ (cur_pages << PSB_2D_DST_YSIZE_SHIFT);
++ if (short_circuit)
++ return 0;
+
-+ ret = psb_2d_submit(dev_priv, buf, bufp - buf);
-+ if (ret)
-+ goto out;
-+ pg_add = (cur_pages << PAGE_SHIFT) * ((direction) ? -1 : 1);
-+ src_offset += pg_add;
-+ dst_offset += pg_add;
-+ }
-+ out:
-+ psb_2d_unlock(dev_priv);
-+ return ret;
-+}
++ memset(&dst_cache, 0, sizeof(dst_cache));
++ memset(&reloc_kmap, 0, sizeof(reloc_kmap));
+
-+void psb_init_2d(struct drm_psb_private *dev_priv)
-+{
-+ dev_priv->sequence_lock = SPIN_LOCK_UNLOCKED;
-+ psb_reset(dev_priv, 1);
-+ dev_priv->mmu_2d_offset = dev_priv->pg->gatt_start;
-+ PSB_WSGX32(dev_priv->mmu_2d_offset, PSB_CR_BIF_TWOD_REQ_BASE);
-+ (void)PSB_RSGX32(PSB_CR_BIF_TWOD_REQ_BASE);
-+}
++ mutex_lock(&dev->struct_mutex);
++ reloc_buffer = drm_lookup_buffer_object(file_priv, reloc_handle, 1);
++ mutex_unlock(&dev->struct_mutex);
++ if (!reloc_buffer)
++ goto out;
+
-+int psb_idle_2d(struct drm_device *dev)
-+{
-+ struct drm_psb_private *dev_priv = dev->dev_private;
-+ unsigned long _end = jiffies + DRM_HZ;
-+ int busy = 0;
++ reloc_first_page = reloc_offset >> PAGE_SHIFT;
++ reloc_last_page =
++ (reloc_offset +
++ num_relocs * sizeof(struct drm_psb_reloc)) >> PAGE_SHIFT;
++ reloc_num_pages = reloc_last_page - reloc_first_page + 1;
++ reloc_offset &= ~PAGE_MASK;
+
-+ /*
-+ * First idle the 2D engine.
-+ */
++ if (reloc_num_pages > PSB_MAX_RELOC_PAGES) {
++ DRM_ERROR("Relocation buffer is too large\n");
++ ret = -EINVAL;
++ goto out;
++ }
+
-+ if (dev_priv->engine_lockup_2d)
-+ return -EBUSY;
++ DRM_WAIT_ON(ret, dev_priv->rel_mapped_queue, 3 * DRM_HZ,
++ (registered =
++ psb_ok_to_map_reloc(dev_priv, reloc_num_pages)));
+
-+ if ((PSB_RSGX32(PSB_CR_2D_SOCIF) == _PSB_C2_SOCIF_EMPTY) &&
-+ ((PSB_RSGX32(PSB_CR_2D_BLIT_STATUS) & _PSB_C2B_STATUS_BUSY) == 0))
++ if (ret == -EINTR) {
++ ret = -EAGAIN;
+ goto out;
++ }
++ if (ret) {
++ DRM_ERROR("Error waiting for space to map "
++ "relocation buffer.\n");
++ goto out;
++ }
+
-+ do {
-+ busy = (PSB_RSGX32(PSB_CR_2D_SOCIF) != _PSB_C2_SOCIF_EMPTY);
-+ } while (busy && !time_after_eq(jiffies, _end));
++ ret = drm_bo_kmap(reloc_buffer, reloc_first_page,
++ reloc_num_pages, &reloc_kmap);
+
-+ if (busy)
-+ busy = (PSB_RSGX32(PSB_CR_2D_SOCIF) != _PSB_C2_SOCIF_EMPTY);
-+ if (busy)
++ if (ret) {
++ DRM_ERROR("Could not map relocation buffer.\n"
++ "\tReloc buffer id 0x%08x.\n"
++ "\tReloc first page %d.\n"
++ "\tReloc num pages %d.\n",
++ reloc_handle, reloc_first_page, reloc_num_pages);
+ goto out;
++ }
+
-+ do {
-+ busy =
-+ ((PSB_RSGX32(PSB_CR_2D_BLIT_STATUS) & _PSB_C2B_STATUS_BUSY)
-+ != 0);
-+ } while (busy && !time_after_eq(jiffies, _end));
-+ if (busy)
-+ busy =
-+ ((PSB_RSGX32(PSB_CR_2D_BLIT_STATUS) & _PSB_C2B_STATUS_BUSY)
-+ != 0);
++ reloc = (struct drm_psb_reloc *)
++ ((unsigned long)drm_bmo_virtual(&reloc_kmap, &reloc_is_iomem) +
++ reloc_offset);
++
++ for (count = 0; count < num_relocs; ++count) {
++ ret = psb_apply_reloc(dev_priv, fence_class,
++ reloc, buffers,
++ num_buffers, &dst_cache,
++ no_wait, interruptible);
++ if (ret)
++ goto out1;
++ reloc++;
++ }
+
++ out1:
++ drm_bo_kunmap(&reloc_kmap);
+ out:
-+ if (busy)
-+ dev_priv->engine_lockup_2d = 1;
++ if (registered) {
++ spin_lock(&dev_priv->reloc_lock);
++ dev_priv->rel_mapped_pages -= reloc_num_pages;
++ spin_unlock(&dev_priv->reloc_lock);
++ DRM_WAKEUP(&dev_priv->rel_mapped_queue);
++ }
+
-+ return (busy) ? -EBUSY : 0;
++ psb_clear_dstbuf_cache(&dst_cache);
++ if (reloc_buffer)
++ drm_bo_usage_deref_unlocked(&reloc_buffer);
++ return ret;
+}
+
-+int psb_idle_3d(struct drm_device *dev)
++static int psb_cmdbuf_2d(struct drm_file *priv,
++ struct drm_psb_cmdbuf_arg *arg,
++ struct drm_buffer_object *cmd_buffer,
++ struct drm_fence_arg *fence_arg)
+{
-+ struct drm_psb_private *dev_priv = dev->dev_private;
-+ struct psb_scheduler *scheduler = &dev_priv->scheduler;
++ struct drm_device *dev = priv->minor->dev;
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
+ int ret;
+
-+ ret = wait_event_timeout(scheduler->idle_queue,
-+ psb_scheduler_finished(dev_priv), DRM_HZ * 10);
++ ret = mutex_lock_interruptible(&dev_priv->reset_mutex);
++ if (ret)
++ return -EAGAIN;
+
-+ return (ret < 1) ? -EBUSY : 0;
-+}
++ ret = psb_submit_copy_cmdbuf(dev, cmd_buffer, arg->cmdbuf_offset,
++ arg->cmdbuf_size, PSB_ENGINE_2D, NULL);
++ if (ret)
++ goto out_unlock;
+
-+static void psb_dereference_buffers_locked(struct psb_buflist_item *buffers,
-+ unsigned num_buffers)
-+{
-+ while (num_buffers--)
-+ drm_bo_usage_deref_locked(&((buffers++)->bo));
++ psb_fence_or_sync(priv, PSB_ENGINE_2D, arg, fence_arg, NULL);
+
++ mutex_lock(&cmd_buffer->mutex);
++ if (cmd_buffer->fence != NULL)
++ drm_fence_usage_deref_unlocked(&cmd_buffer->fence);
++ mutex_unlock(&cmd_buffer->mutex);
++ out_unlock:
++ mutex_unlock(&dev_priv->reset_mutex);
++ return ret;
+}
+
-+static int psb_check_presumed(struct drm_bo_op_arg *arg,
-+ struct drm_buffer_object *bo,
-+ uint32_t __user * data, int *presumed_ok)
++#if 0
++static int psb_dump_page(struct drm_buffer_object *bo,
++ unsigned int page_offset, unsigned int num)
+{
-+ struct drm_bo_op_req *req = &arg->d.req;
-+ uint32_t hint_offset;
-+ uint32_t hint = req->bo_req.hint;
++ struct drm_bo_kmap_obj kmobj;
++ int is_iomem;
++ uint32_t *p;
++ int ret;
++ unsigned int i;
+
-+ *presumed_ok = 0;
++ ret = drm_bo_kmap(bo, page_offset, 1, &kmobj);
++ if (ret)
++ return ret;
+
-+ if (!(hint & DRM_BO_HINT_PRESUMED_OFFSET))
-+ return 0;
-+ if (bo->mem.mem_type == DRM_BO_MEM_LOCAL) {
-+ *presumed_ok = 1;
-+ return 0;
-+ }
-+ if (bo->offset == req->bo_req.presumed_offset) {
-+ *presumed_ok = 1;
-+ return 0;
-+ }
-+
-+ /*
-+ * We need to turn off the HINT_PRESUMED_OFFSET for this buffer in
-+ * the user-space IOCTL argument list, since the buffer has moved,
-+ * we're about to apply relocations and we might subsequently
-+ * hit an -EAGAIN. In that case the argument list will be reused by
-+ * user-space, but the presumed offset is no longer valid.
-+ *
-+ * Needless to say, this is a bit ugly.
-+ */
++ p = drm_bmo_virtual(&kmobj, &is_iomem);
++ for (i = 0; i < num; ++i)
++ PSB_DEBUG_GENERAL("0x%04x: 0x%08x\n", i, *p++);
+
-+ hint_offset = (uint32_t *) & req->bo_req.hint - (uint32_t *) arg;
-+ hint &= ~DRM_BO_HINT_PRESUMED_OFFSET;
-+ return __put_user(hint, data + hint_offset);
++ drm_bo_kunmap(&kmobj);
++ return 0;
+}
++#endif
+
-+static int psb_validate_buffer_list(struct drm_file *file_priv,
-+ unsigned fence_class,
-+ unsigned long data,
-+ struct psb_buflist_item *buffers,
-+ unsigned *num_buffers)
++static void psb_idle_engine(struct drm_device *dev, int engine)
+{
-+ struct drm_bo_op_arg arg;
-+ struct drm_bo_op_req *req = &arg.d.req;
-+ int ret = 0;
-+ unsigned buf_count = 0;
-+ struct psb_buflist_item *item = buffers;
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
++ uint32_t dummy;
+
-+ do {
-+ if (buf_count >= *num_buffers) {
-+ DRM_ERROR("Buffer count exceeded %d\n.", *num_buffers);
-+ ret = -EINVAL;
-+ goto out_err;
-+ }
-+ item = buffers + buf_count;
-+ item->bo = NULL;
++ switch (engine) {
++ case PSB_ENGINE_2D:
+
-+ if (copy_from_user(&arg, (void __user *)data, sizeof(arg))) {
-+ ret = -EFAULT;
-+ DRM_ERROR("Error copying validate list.\n"
-+ "\tbuffer %d, user addr 0x%08lx %d\n",
-+ buf_count, (unsigned long)data, sizeof(arg));
-+ goto out_err;
-+ }
++ /*
++ * Make sure we flush 2D properly using a dummy
++ * fence sequence emit.
++ */
+
-+ ret = 0;
-+ if (req->op != drm_bo_validate) {
-+ DRM_ERROR
-+ ("Buffer object operation wasn't \"validate\".\n");
-+ ret = -EINVAL;
-+ goto out_err;
-+ }
++ (void)psb_fence_emit_sequence(dev, PSB_ENGINE_2D, 0,
++ &dummy, &dummy);
++ psb_2d_lock(dev_priv);
++ (void)psb_idle_2d(dev);
++ psb_2d_unlock(dev_priv);
++ break;
++ case PSB_ENGINE_TA:
++ case PSB_ENGINE_RASTERIZER:
++ case PSB_ENGINE_HPRAST:
++ (void)psb_idle_3d(dev);
++ break;
++ default:
+
-+ item->ret = 0;
-+ item->data = (void *)__user data;
-+ ret = drm_bo_handle_validate(file_priv,
-+ req->bo_req.handle,
-+ fence_class,
-+ req->bo_req.flags,
-+ req->bo_req.mask,
-+ req->bo_req.hint,
-+ 0, NULL, &item->bo);
-+ if (ret)
-+ goto out_err;
++ /*
++ * FIXME: Insert video engine idle command here.
++ */
+
-+ PSB_DEBUG_GENERAL("Validated buffer at 0x%08lx\n",
-+ buffers[buf_count].bo->offset);
++ break;
++ }
++}
+
-+ buf_count++;
++void psb_fence_or_sync(struct drm_file *priv,
++ int engine,
++ struct drm_psb_cmdbuf_arg *arg,
++ struct drm_fence_arg *fence_arg,
++ struct drm_fence_object **fence_p)
++{
++ struct drm_device *dev = priv->minor->dev;
++ int ret;
++ struct drm_fence_object *fence;
+
++ ret = drm_fence_buffer_objects(dev, NULL, arg->fence_flags,
++ NULL, &fence);
+
-+ ret = psb_check_presumed(&arg, item->bo,
-+ (uint32_t __user *)
-+ (unsigned long) data,
-+ &item->presumed_offset_correct);
++ if (ret) {
+
-+ if (ret)
-+ goto out_err;
++ /*
++ * Fence creation failed.
++ * Fall back to synchronous operation and idle the engine.
++ */
+
-+ data = arg.next;
-+ } while (data);
++ psb_idle_engine(dev, engine);
++ if (!(arg->fence_flags & DRM_FENCE_FLAG_NO_USER)) {
+
-+ *num_buffers = buf_count;
++ /*
++ * Communicate to user-space that
++ * fence creation has failed and that
++ * the engine is idle.
++ */
+
-+ return 0;
-+ out_err:
++ fence_arg->handle = ~0;
++ fence_arg->error = ret;
++ }
+
-+ *num_buffers = buf_count;
-+ item->ret = (ret != -EAGAIN) ? ret : 0;
-+ return ret;
++ drm_putback_buffer_objects(dev);
++ if (fence_p)
++ *fence_p = NULL;
++ return;
++ }
++
++ if (!(arg->fence_flags & DRM_FENCE_FLAG_NO_USER)) {
++
++ ret = drm_fence_add_user_object(priv, fence,
++ arg->fence_flags &
++ DRM_FENCE_FLAG_SHAREABLE);
++ if (!ret)
++ drm_fence_fill_arg(fence, fence_arg);
++ else {
++ /*
++ * Fence user object creation failed.
++ * We must idle the engine here as well, as user-
++ * space expects a fence object to wait on. Since we
++ * have a fence object we wait for it to signal
++ * to indicate engine "sufficiently" idle.
++ */
++
++ (void)drm_fence_object_wait(fence, 0, 1, fence->type);
++ drm_fence_usage_deref_unlocked(&fence);
++ fence_arg->handle = ~0;
++ fence_arg->error = ret;
++ }
++ }
++
++ if (fence_p)
++ *fence_p = fence;
++ else if (fence)
++ drm_fence_usage_deref_unlocked(&fence);
+}
+
-+int
-+psb_reg_submit(struct drm_psb_private *dev_priv, uint32_t * regs,
-+ unsigned int cmds)
++int psb_handle_copyback(struct drm_device *dev,
++ struct psb_buflist_item *buffers,
++ unsigned int num_buffers, int ret, void *data)
+{
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
++ struct drm_bo_op_arg arg;
++ struct psb_buflist_item *item = buffers;
++ struct drm_buffer_object *bo;
++ int err = ret;
+ int i;
+
+ /*
-+ * cmds is 32-bit words.
++ * Clear the unfenced use base register lists and buffer lists.
+ */
+
-+ cmds >>= 1;
-+ for (i = 0; i < cmds; ++i) {
-+ PSB_WSGX32(regs[1], regs[0]);
-+ regs += 2;
++ if (ret) {
++ drm_regs_fence(&dev_priv->use_manager, NULL);
++ drm_putback_buffer_objects(dev);
+ }
-+ wmb();
-+ return 0;
-+}
+
-+/*
-+ * Security: Block user-space writing to MMU mapping registers.
-+ * This is important for security and brings Poulsbo DRM
-+ * up to par with the other DRM drivers. Using this,
-+ * user-space should not be able to map arbitrary memory
-+ * pages to graphics memory, but all user-space processes
-+ * basically have access to all buffer objects mapped to
-+ * graphics memory.
-+ */
++ if (ret != -EAGAIN) {
++ for (i = 0; i < num_buffers; ++i) {
++ arg.handled = 1;
++ arg.d.rep.ret = item->ret;
++ bo = item->bo;
++ mutex_lock(&bo->mutex);
++ drm_bo_fill_rep_arg(bo, &arg.d.rep.bo_info);
++ mutex_unlock(&bo->mutex);
++ if (copy_to_user(item->data, &arg, sizeof(arg)))
++ err = -EFAULT;
++ ++item;
++ }
++ }
+
-+int
-+psb_submit_copy_cmdbuf(struct drm_device *dev,
-+ struct drm_buffer_object *cmd_buffer,
-+ unsigned long cmd_offset,
-+ unsigned long cmd_size,
-+ int engine, uint32_t * copy_buffer)
-+{
-+ unsigned long cmd_end = cmd_offset + (cmd_size << 2);
-+ struct drm_psb_private *dev_priv = dev->dev_private;
-+ unsigned long cmd_page_offset = cmd_offset - (cmd_offset & PAGE_MASK);
-+ unsigned long cmd_next;
-+ struct drm_bo_kmap_obj cmd_kmap;
-+ uint32_t *cmd_page;
-+ unsigned cmds;
-+ int is_iomem;
-+ int ret = 0;
++ return err;
++}
+
-+ if (cmd_size == 0)
-+ return 0;
++static int psb_cmdbuf_video(struct drm_file *priv,
++ struct drm_psb_cmdbuf_arg *arg,
++ unsigned int num_buffers,
++ struct drm_buffer_object *cmd_buffer,
++ struct drm_fence_arg *fence_arg)
++{
++ struct drm_device *dev = priv->minor->dev;
++ struct drm_fence_object *fence;
++ int ret;
+
-+ if (engine == PSB_ENGINE_2D)
-+ psb_2d_lock(dev_priv);
++ /*
++ * Check this. Doesn't seem right. Have fencing done AFTER command
++ * submission and make sure drm_psb_idle idles the MSVDX completely.
++ */
+
-+ do {
-+ cmd_next = drm_bo_offset_end(cmd_offset, cmd_end);
-+ ret = drm_bo_kmap(cmd_buffer, cmd_offset >> PAGE_SHIFT,
-+ 1, &cmd_kmap);
-+
-+ if (ret)
-+ return ret;
-+ cmd_page = drm_bmo_virtual(&cmd_kmap, &is_iomem);
-+ cmd_page_offset = (cmd_offset & ~PAGE_MASK) >> 2;
-+ cmds = (cmd_next - cmd_offset) >> 2;
-+
-+ switch (engine) {
-+ case PSB_ENGINE_2D:
-+ ret =
-+ psb_2d_submit(dev_priv, cmd_page + cmd_page_offset,
-+ cmds);
-+ break;
-+ case PSB_ENGINE_RASTERIZER:
-+ case PSB_ENGINE_TA:
-+ case PSB_ENGINE_HPRAST:
-+ PSB_DEBUG_GENERAL("Reg copy.\n");
-+ ret = psb_memcpy_check(copy_buffer,
-+ cmd_page + cmd_page_offset,
-+ cmds * sizeof(uint32_t));
-+ copy_buffer += cmds;
-+ break;
-+ default:
-+ ret = -EINVAL;
-+ }
-+ drm_bo_kunmap(&cmd_kmap);
-+ if (ret)
-+ break;
-+ } while (cmd_offset = cmd_next, cmd_offset != cmd_end);
-+
-+ if (engine == PSB_ENGINE_2D)
-+ psb_2d_unlock(dev_priv);
++ psb_fence_or_sync(priv, PSB_ENGINE_VIDEO, arg, fence_arg, &fence);
++ ret = psb_submit_video_cmdbuf(dev, cmd_buffer, arg->cmdbuf_offset,
++ arg->cmdbuf_size, fence);
+
-+ return ret;
-+}
++ if (ret)
++ return ret;
+
-+static void psb_clear_dstbuf_cache(struct psb_dstbuf_cache *dst_cache)
-+{
-+ if (dst_cache->dst_page) {
-+ drm_bo_kunmap(&dst_cache->dst_kmap);
-+ dst_cache->dst_page = NULL;
-+ }
-+ dst_cache->dst_buf = NULL;
-+ dst_cache->dst = ~0;
-+ dst_cache->use_page = NULL;
++ drm_fence_usage_deref_unlocked(&fence);
++ mutex_lock(&cmd_buffer->mutex);
++ if (cmd_buffer->fence != NULL)
++ drm_fence_usage_deref_unlocked(&cmd_buffer->fence);
++ mutex_unlock(&cmd_buffer->mutex);
++ return 0;
+}
+
-+static int psb_update_dstbuf_cache(struct psb_dstbuf_cache *dst_cache,
-+ struct psb_buflist_item *buffers,
-+ unsigned int dst, unsigned long dst_offset)
++int psb_feedback_buf(struct drm_file *file_priv,
++ uint32_t feedback_ops,
++ uint32_t handle,
++ uint32_t offset,
++ uint32_t feedback_breakpoints,
++ uint32_t feedback_size, struct psb_feedback_info *feedback)
+{
++ struct drm_buffer_object *bo;
++ struct page *page;
++ uint32_t page_no;
++ uint32_t page_offset;
+ int ret;
+
-+ PSB_DEBUG_RELOC("Destination buffer is %d.\n", dst);
++ if (feedback_ops & ~PSB_FEEDBACK_OP_VISTEST) {
++ DRM_ERROR("Illegal feedback op.\n");
++ return -EINVAL;
++ }
+
-+ if (unlikely(dst != dst_cache->dst || NULL == dst_cache->dst_buf)) {
-+ psb_clear_dstbuf_cache(dst_cache);
-+ dst_cache->dst = dst;
-+ dst_cache->dst_buf = buffers[dst].bo;
++ if (feedback_breakpoints != 0) {
++ DRM_ERROR("Feedback breakpoints not implemented yet.\n");
++ return -EINVAL;
+ }
+
-+ if (unlikely(dst_offset > dst_cache->dst_buf->num_pages * PAGE_SIZE)) {
-+ DRM_ERROR("Relocation destination out of bounds.\n");
++ if (feedback_size < PSB_HW_FEEDBACK_SIZE * sizeof(uint32_t)) {
++ DRM_ERROR("Feedback buffer size too small.\n");
+ return -EINVAL;
+ }
+
-+ if (!drm_bo_same_page(dst_cache->dst_offset, dst_offset) ||
-+ NULL == dst_cache->dst_page) {
-+ if (NULL != dst_cache->dst_page) {
-+ drm_bo_kunmap(&dst_cache->dst_kmap);
-+ dst_cache->dst_page = NULL;
-+ }
++ page_offset = offset & ~PAGE_MASK;
++ if ((PAGE_SIZE - PSB_HW_FEEDBACK_SIZE * sizeof(uint32_t))
++ < page_offset) {
++ DRM_ERROR("Illegal feedback buffer alignment.\n");
++ return -EINVAL;
++ }
+
-+ ret = drm_bo_kmap(dst_cache->dst_buf, dst_offset >> PAGE_SHIFT,
-+ 1, &dst_cache->dst_kmap);
-+ if (ret) {
-+ DRM_ERROR("Could not map destination buffer for "
-+ "relocation.\n");
-+ return ret;
-+ }
++ ret = drm_bo_handle_validate(file_priv,
++ handle,
++ PSB_ENGINE_TA,
++ DRM_BO_FLAG_MEM_LOCAL |
++ DRM_BO_FLAG_CACHED |
++ DRM_BO_FLAG_WRITE |
++ PSB_BO_FLAG_FEEDBACK,
++ DRM_BO_MASK_MEM |
++ DRM_BO_FLAG_CACHED |
++ DRM_BO_FLAG_WRITE |
++ PSB_BO_FLAG_FEEDBACK, 0, 0, NULL, &bo);
++ if (ret)
++ return ret;
+
-+ dst_cache->dst_page = drm_bmo_virtual(&dst_cache->dst_kmap,
-+ &dst_cache->dst_is_iomem);
-+ dst_cache->dst_offset = dst_offset & PAGE_MASK;
-+ dst_cache->dst_page_offset = dst_cache->dst_offset >> 2;
++ page_no = offset >> PAGE_SHIFT;
++ if (page_no >= bo->num_pages) {
++ ret = -EINVAL;
++ DRM_ERROR("Illegal feedback buffer offset.\n");
++ goto out_unref;
++ }
++
++ if (bo->ttm == NULL) {
++ ret = -EINVAL;
++ DRM_ERROR("Vistest buffer without TTM.\n");
++ goto out_unref;
++ }
++
++ page = drm_ttm_get_page(bo->ttm, page_no);
++ if (!page) {
++ ret = -ENOMEM;
++ goto out_unref;
+ }
++
++ feedback->page = page;
++ feedback->bo = bo;
++ feedback->offset = page_offset;
+ return 0;
++
++ out_unref:
++ drm_bo_usage_deref_unlocked(&bo);
++ return ret;
+}
+
-+static int psb_apply_reloc(struct drm_psb_private *dev_priv,
-+ uint32_t fence_class,
-+ const struct drm_psb_reloc *reloc,
-+ struct psb_buflist_item *buffers,
-+ int num_buffers,
-+ struct psb_dstbuf_cache *dst_cache,
-+ int no_wait, int interruptible)
++int psb_cmdbuf_ioctl(struct drm_device *dev, void *data,
++ struct drm_file *file_priv)
+{
-+ int reg;
-+ uint32_t val;
-+ uint32_t background;
-+ unsigned int index;
-+ int ret;
-+ unsigned int shift;
-+ unsigned int align_shift;
-+ uint32_t fence_type;
-+ struct drm_buffer_object *reloc_bo;
-+
-+ PSB_DEBUG_RELOC("Reloc type %d\n"
-+ "\t where 0x%04x\n"
-+ "\t buffer 0x%04x\n"
-+ "\t mask 0x%08x\n"
-+ "\t shift 0x%08x\n"
-+ "\t pre_add 0x%08x\n"
-+ "\t background 0x%08x\n"
-+ "\t dst_buffer 0x%08x\n"
-+ "\t arg0 0x%08x\n"
-+ "\t arg1 0x%08x\n",
-+ reloc->reloc_op,
-+ reloc->where,
-+ reloc->buffer,
-+ reloc->mask,
-+ reloc->shift,
-+ reloc->pre_add,
-+ reloc->background,
-+ reloc->dst_buffer, reloc->arg0, reloc->arg1);
++ drm_psb_cmdbuf_arg_t *arg = data;
++ int ret = 0;
++ unsigned num_buffers;
++ struct drm_buffer_object *cmd_buffer = NULL;
++ struct drm_buffer_object *ta_buffer = NULL;
++ struct drm_buffer_object *oom_buffer = NULL;
++ struct drm_fence_arg fence_arg;
++ struct drm_psb_scene user_scene;
++ struct psb_scene_pool *pool = NULL;
++ struct psb_scene *scene = NULL;
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)file_priv->minor->dev->dev_private;
++ int engine;
++ struct psb_feedback_info feedback;
+
-+ if (unlikely(reloc->buffer >= num_buffers)) {
-+ DRM_ERROR("Illegal relocation buffer %d.\n", reloc->buffer);
++ if (!dev_priv)
+ return -EINVAL;
-+ }
+
-+ if (buffers[reloc->buffer].presumed_offset_correct)
-+ return 0;
++ ret = drm_bo_read_lock(&dev->bm.bm_lock);
++ if (ret)
++ return ret;
+
-+ if (unlikely(reloc->dst_buffer >= num_buffers)) {
-+ DRM_ERROR("Illegal destination buffer for relocation %d.\n",
-+ reloc->dst_buffer);
-+ return -EINVAL;
++ num_buffers = PSB_NUM_VALIDATE_BUFFERS;
++
++ ret = mutex_lock_interruptible(&dev_priv->cmdbuf_mutex);
++ if (ret) {
++ drm_bo_read_unlock(&dev->bm.bm_lock);
++ return -EAGAIN;
++ }
++ if (unlikely(dev_priv->buffers == NULL)) {
++ dev_priv->buffers = vmalloc(PSB_NUM_VALIDATE_BUFFERS *
++ sizeof(*dev_priv->buffers));
++ if (dev_priv->buffers == NULL) {
++ drm_bo_read_unlock(&dev->bm.bm_lock);
++ return -ENOMEM;
++ }
+ }
+
-+ ret = psb_update_dstbuf_cache(dst_cache, buffers, reloc->dst_buffer,
-+ reloc->where << 2);
++
++ engine = (arg->engine == PSB_ENGINE_RASTERIZER) ?
++ PSB_ENGINE_TA : arg->engine;
++
++ ret =
++ psb_validate_buffer_list(file_priv, engine,
++ (unsigned long)arg->buffer_list,
++ dev_priv->buffers, &num_buffers);
+ if (ret)
-+ return ret;
++ goto out_err0;
+
-+ reloc_bo = buffers[reloc->buffer].bo;
++ ret = psb_fixup_relocs(file_priv, engine, arg->num_relocs,
++ arg->reloc_offset, arg->reloc_handle,
++ dev_priv->buffers, num_buffers, 0, 1);
++ if (ret)
++ goto out_err0;
+
-+ if (unlikely(reloc->pre_add > (reloc_bo->num_pages << PAGE_SHIFT))) {
-+ DRM_ERROR("Illegal relocation offset add.\n");
-+ return -EINVAL;
++ mutex_lock(&dev->struct_mutex);
++ cmd_buffer = drm_lookup_buffer_object(file_priv, arg->cmdbuf_handle, 1);
++ mutex_unlock(&dev->struct_mutex);
++ if (!cmd_buffer) {
++ ret = -EINVAL;
++ goto out_err0;
+ }
+
-+ switch (reloc->reloc_op) {
-+ case PSB_RELOC_OP_OFFSET:
-+ val = reloc_bo->offset + reloc->pre_add;
-+ break;
-+ case PSB_RELOC_OP_2D_OFFSET:
-+ val = reloc_bo->offset + reloc->pre_add -
-+ dev_priv->mmu_2d_offset;
-+ if (unlikely(val >= PSB_2D_SIZE)) {
-+ DRM_ERROR("2D relocation out of bounds\n");
-+ return -EINVAL;
-+ }
++ switch (arg->engine) {
++ case PSB_ENGINE_2D:
++ ret = psb_cmdbuf_2d(file_priv, arg, cmd_buffer, &fence_arg);
++ if (ret)
++ goto out_err0;
+ break;
-+ case PSB_RELOC_OP_PDS_OFFSET:
-+ val = reloc_bo->offset + reloc->pre_add - PSB_MEM_PDS_START;
-+ if (unlikely(val >= (PSB_MEM_MMU_START - PSB_MEM_PDS_START))) {
-+ DRM_ERROR("PDS relocation out of bounds\n");
-+ return -EINVAL;
-+ }
++ case PSB_ENGINE_VIDEO:
++ ret =
++ psb_cmdbuf_video(file_priv, arg, num_buffers, cmd_buffer,
++ &fence_arg);
++ if (ret)
++ goto out_err0;
+ break;
-+ case PSB_RELOC_OP_USE_OFFSET:
-+ case PSB_RELOC_OP_USE_REG:
++ case PSB_ENGINE_RASTERIZER:
++ ret = psb_cmdbuf_raster(file_priv, arg, cmd_buffer, &fence_arg);
++ if (ret)
++ goto out_err0;
++ break;
++ case PSB_ENGINE_TA:
++ if (arg->ta_handle == arg->cmdbuf_handle) {
++ mutex_lock(&dev->struct_mutex);
++ atomic_inc(&cmd_buffer->usage);
++ ta_buffer = cmd_buffer;
++ mutex_unlock(&dev->struct_mutex);
++ } else {
++ mutex_lock(&dev->struct_mutex);
++ ta_buffer =
++ drm_lookup_buffer_object(file_priv,
++ arg->ta_handle, 1);
++ mutex_unlock(&dev->struct_mutex);
++ if (!ta_buffer) {
++ ret = -EINVAL;
++ goto out_err0;
++ }
++ }
++ if (arg->oom_size != 0) {
++ if (arg->oom_handle == arg->cmdbuf_handle) {
++ mutex_lock(&dev->struct_mutex);
++ atomic_inc(&cmd_buffer->usage);
++ oom_buffer = cmd_buffer;
++ mutex_unlock(&dev->struct_mutex);
++ } else {
++ mutex_lock(&dev->struct_mutex);
++ oom_buffer =
++ drm_lookup_buffer_object(file_priv,
++ arg->oom_handle,
++ 1);
++ mutex_unlock(&dev->struct_mutex);
++ if (!oom_buffer) {
++ ret = -EINVAL;
++ goto out_err0;
++ }
++ }
++ }
+
-+ /*
-+ * Security:
-+ * Only allow VERTEX or PIXEL data masters, as
-+ * shaders run under other data masters may in theory
-+ * alter MMU mappings.
-+ */
++ ret = copy_from_user(&user_scene, (void __user *)
++ ((unsigned long)arg->scene_arg),
++ sizeof(user_scene));
++ if (ret)
++ goto out_err0;
+
-+ if (unlikely(reloc->arg1 != _PSB_CUC_DM_PIXEL &&
-+ reloc->arg1 != _PSB_CUC_DM_VERTEX)) {
-+ DRM_ERROR("Invalid data master in relocation. %d\n",
-+ reloc->arg1);
-+ return -EPERM;
++ if (!user_scene.handle_valid) {
++ pool = psb_scene_pool_alloc(file_priv, 0,
++ user_scene.num_buffers,
++ user_scene.w, user_scene.h);
++ if (!pool) {
++ ret = -ENOMEM;
++ goto out_err0;
++ }
++
++ user_scene.handle = psb_scene_pool_handle(pool);
++ user_scene.handle_valid = 1;
++ ret = copy_to_user((void __user *)
++ ((unsigned long)arg->scene_arg),
++ &user_scene, sizeof(user_scene));
++
++ if (ret)
++ goto out_err0;
++ } else {
++ mutex_lock(&dev->struct_mutex);
++ pool = psb_scene_pool_lookup_devlocked(file_priv,
++ user_scene.
++ handle, 1);
++ mutex_unlock(&dev->struct_mutex);
++ if (!pool) {
++ ret = -EINVAL;
++ goto out_err0;
++ }
+ }
+
-+ fence_type = reloc_bo->fence_type;
-+ ret = psb_grab_use_base(dev_priv,
-+ reloc_bo->offset +
-+ reloc->pre_add, reloc->arg0,
-+ reloc->arg1, fence_class,
-+ fence_type, no_wait,
-+ interruptible, ®, &val);
++ mutex_lock(&dev_priv->reset_mutex);
++ ret = psb_validate_scene_pool(pool, 0, 0, 0,
++ user_scene.w,
++ user_scene.h,
++ arg->ta_flags &
++ PSB_TA_FLAG_LASTPASS, &scene);
++ mutex_unlock(&dev_priv->reset_mutex);
++
+ if (ret)
-+ return ret;
++ goto out_err0;
+
-+ val = (reloc->reloc_op == PSB_RELOC_OP_USE_REG) ? reg : val;
++ memset(&feedback, 0, sizeof(feedback));
++ if (arg->feedback_ops) {
++ ret = psb_feedback_buf(file_priv,
++ arg->feedback_ops,
++ arg->feedback_handle,
++ arg->feedback_offset,
++ arg->feedback_breakpoints,
++ arg->feedback_size, &feedback);
++ if (ret)
++ goto out_err0;
++ }
++ ret = psb_cmdbuf_ta(file_priv, arg, cmd_buffer, ta_buffer,
++ oom_buffer, scene, &feedback, &fence_arg);
++ if (ret)
++ goto out_err0;
+ break;
+ default:
-+ DRM_ERROR("Unimplemented relocation.\n");
-+ return -EINVAL;
++ DRM_ERROR("Unimplemented command submission mechanism (%x).\n",
++ arg->engine);
++ ret = -EINVAL;
++ goto out_err0;
+ }
+
-+ shift = (reloc->shift & PSB_RELOC_SHIFT_MASK) >> PSB_RELOC_SHIFT_SHIFT;
-+ align_shift = (reloc->shift & PSB_RELOC_ALSHIFT_MASK) >>
-+ PSB_RELOC_ALSHIFT_SHIFT;
-+
-+ val = ((val >> align_shift) << shift);
-+ index = reloc->where - dst_cache->dst_page_offset;
-+
-+ background = reloc->background;
-+
-+ if (reloc->reloc_op == PSB_RELOC_OP_USE_OFFSET) {
-+ if (dst_cache->use_page == dst_cache->dst_page &&
-+ dst_cache->use_index == index)
-+ background = dst_cache->use_background;
-+ else
-+ background = dst_cache->dst_page[index];
++ if (!(arg->fence_flags & DRM_FENCE_FLAG_NO_USER)) {
++ ret = copy_to_user((void __user *)
++ ((unsigned long)arg->fence_arg),
++ &fence_arg, sizeof(fence_arg));
+ }
-+#if 0
-+ if (dst_cache->dst_page[index] != PSB_RELOC_MAGIC &&
-+ reloc->reloc_op != PSB_RELOC_OP_USE_OFFSET)
-+ DRM_ERROR("Inconsistent relocation 0x%08lx.\n",
-+ (unsigned long)dst_cache->dst_page[index]);
-+#endif
-+
-+ val = (background & ~reloc->mask) | (val & reloc->mask);
-+ dst_cache->dst_page[index] = val;
+
-+ if (reloc->reloc_op == PSB_RELOC_OP_USE_OFFSET ||
-+ reloc->reloc_op == PSB_RELOC_OP_USE_REG) {
-+ dst_cache->use_page = dst_cache->dst_page;
-+ dst_cache->use_index = index;
-+ dst_cache->use_background = val;
-+ }
++ out_err0:
++ ret =
++ psb_handle_copyback(dev, dev_priv->buffers, num_buffers, ret, data);
++ mutex_lock(&dev->struct_mutex);
++ if (scene)
++ psb_scene_unref_devlocked(&scene);
++ if (pool)
++ psb_scene_pool_unref_devlocked(&pool);
++ if (cmd_buffer)
++ drm_bo_usage_deref_locked(&cmd_buffer);
++ if (ta_buffer)
++ drm_bo_usage_deref_locked(&ta_buffer);
++ if (oom_buffer)
++ drm_bo_usage_deref_locked(&oom_buffer);
+
-+ PSB_DEBUG_RELOC("Reloc buffer %d index 0x%08x, value 0x%08x\n",
-+ reloc->dst_buffer, index, dst_cache->dst_page[index]);
++ psb_dereference_buffers_locked(dev_priv->buffers, num_buffers);
++ mutex_unlock(&dev->struct_mutex);
++ mutex_unlock(&dev_priv->cmdbuf_mutex);
+
-+ return 0;
++ drm_bo_read_unlock(&dev->bm.bm_lock);
++ return ret;
+}
+Index: linux-2.6.28/drivers/gpu/drm/psb/psb_xhw.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.28/drivers/gpu/drm/psb/psb_xhw.c 2009-02-12 09:14:42.000000000 +0000
+@@ -0,0 +1,614 @@
++/**************************************************************************
++ * Copyright (c) 2007, Intel Corporation.
++ * All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
++ *
++ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
++ * develop this driver.
++ *
++ **************************************************************************/
++/*
++ * Make calls into closed source X server code.
++ */
+
-+static int psb_ok_to_map_reloc(struct drm_psb_private *dev_priv,
-+ unsigned int num_pages)
++#include "drmP.h"
++#include "psb_drv.h"
++
++void
++psb_xhw_clean_buf(struct drm_psb_private *dev_priv, struct psb_xhw_buf *buf)
+{
-+ int ret = 0;
++ unsigned long irq_flags;
+
-+ spin_lock(&dev_priv->reloc_lock);
-+ if (dev_priv->rel_mapped_pages + num_pages <= PSB_MAX_RELOC_PAGES) {
-+ dev_priv->rel_mapped_pages += num_pages;
-+ ret = 1;
-+ }
-+ spin_unlock(&dev_priv->reloc_lock);
-+ return ret;
++ spin_lock_irqsave(&dev_priv->xhw_lock, irq_flags);
++ list_del_init(&buf->head);
++ if (dev_priv->xhw_cur_buf == buf)
++ dev_priv->xhw_cur_buf = NULL;
++ atomic_set(&buf->done, 1);
++ spin_unlock_irqrestore(&dev_priv->xhw_lock, irq_flags);
+}
+
-+static int psb_fixup_relocs(struct drm_file *file_priv,
-+ uint32_t fence_class,
-+ unsigned int num_relocs,
-+ unsigned int reloc_offset,
-+ uint32_t reloc_handle,
-+ struct psb_buflist_item *buffers,
-+ unsigned int num_buffers,
-+ int no_wait, int interruptible)
++static inline int psb_xhw_add(struct drm_psb_private *dev_priv,
++ struct psb_xhw_buf *buf)
+{
-+ struct drm_device *dev = file_priv->minor->dev;
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
-+ struct drm_buffer_object *reloc_buffer = NULL;
-+ unsigned int reloc_num_pages;
-+ unsigned int reloc_first_page;
-+ unsigned int reloc_last_page;
-+ struct psb_dstbuf_cache dst_cache;
-+ struct drm_psb_reloc *reloc;
-+ struct drm_bo_kmap_obj reloc_kmap;
-+ int reloc_is_iomem;
-+ int count;
-+ int ret = 0;
-+ int registered = 0;
-+ int short_circuit = 1;
-+ int i;
-+
-+ if (num_relocs == 0)
-+ return 0;
++ unsigned long irq_flags;
+
-+ for (i=0; i<num_buffers; ++i) {
-+ if (!buffers[i].presumed_offset_correct) {
-+ short_circuit = 0;
-+ break;
-+ }
++ spin_lock_irqsave(&dev_priv->xhw_lock, irq_flags);
++ atomic_set(&buf->done, 0);
++ if (unlikely(!dev_priv->xhw_submit_ok)) {
++ spin_unlock_irqrestore(&dev_priv->xhw_lock, irq_flags);
++ DRM_ERROR("No Xpsb 3D extension available.\n");
++ return -EINVAL;
++ }
++ if (!list_empty(&buf->head)) {
++ DRM_ERROR("Recursive list adding.\n");
++ goto out;
+ }
++ list_add_tail(&buf->head, &dev_priv->xhw_in);
++ wake_up_interruptible(&dev_priv->xhw_queue);
++ out:
++ spin_unlock_irqrestore(&dev_priv->xhw_lock, irq_flags);
++ return 0;
++}
+
-+ if (short_circuit)
-+ return 0;
++int psb_xhw_scene_info(struct drm_psb_private *dev_priv,
++ struct psb_xhw_buf *buf,
++ uint32_t w,
++ uint32_t h,
++ uint32_t * hw_cookie,
++ uint32_t * bo_size,
++ uint32_t * clear_p_start, uint32_t * clear_num_pages)
++{
++ struct drm_psb_xhw_arg *xa = &buf->arg;
++ int ret;
+
-+ memset(&dst_cache, 0, sizeof(dst_cache));
-+ memset(&reloc_kmap, 0, sizeof(reloc_kmap));
++ buf->copy_back = 1;
++ xa->op = PSB_XHW_SCENE_INFO;
++ xa->irq_op = 0;
++ xa->issue_irq = 0;
++ xa->arg.si.w = w;
++ xa->arg.si.h = h;
+
-+ mutex_lock(&dev->struct_mutex);
-+ reloc_buffer = drm_lookup_buffer_object(file_priv, reloc_handle, 1);
-+ mutex_unlock(&dev->struct_mutex);
-+ if (!reloc_buffer)
-+ goto out;
++ ret = psb_xhw_add(dev_priv, buf);
++ if (ret)
++ return ret;
+
-+ reloc_first_page = reloc_offset >> PAGE_SHIFT;
-+ reloc_last_page =
-+ (reloc_offset +
-+ num_relocs * sizeof(struct drm_psb_reloc)) >> PAGE_SHIFT;
-+ reloc_num_pages = reloc_last_page - reloc_first_page + 1;
-+ reloc_offset &= ~PAGE_MASK;
++ (void)wait_event_timeout(dev_priv->xhw_caller_queue,
++ atomic_read(&buf->done), DRM_HZ);
+
-+ if (reloc_num_pages > PSB_MAX_RELOC_PAGES) {
-+ DRM_ERROR("Relocation buffer is too large\n");
-+ ret = -EINVAL;
-+ goto out;
++ if (!atomic_read(&buf->done)) {
++ psb_xhw_clean_buf(dev_priv, buf);
++ return -EBUSY;
+ }
+
-+ DRM_WAIT_ON(ret, dev_priv->rel_mapped_queue, 3 * DRM_HZ,
-+ (registered =
-+ psb_ok_to_map_reloc(dev_priv, reloc_num_pages)));
-+
-+ if (ret == -EINTR) {
-+ ret = -EAGAIN;
-+ goto out;
-+ }
-+ if (ret) {
-+ DRM_ERROR("Error waiting for space to map "
-+ "relocation buffer.\n");
-+ goto out;
++ if (!xa->ret) {
++ memcpy(hw_cookie, xa->cookie, sizeof(xa->cookie));
++ *bo_size = xa->arg.si.size;
++ *clear_p_start = xa->arg.si.clear_p_start;
++ *clear_num_pages = xa->arg.si.clear_num_pages;
+ }
++ return xa->ret;
++}
+
-+ ret = drm_bo_kmap(reloc_buffer, reloc_first_page,
-+ reloc_num_pages, &reloc_kmap);
++int psb_xhw_fire_raster(struct drm_psb_private *dev_priv,
++ struct psb_xhw_buf *buf, uint32_t fire_flags)
++{
++ struct drm_psb_xhw_arg *xa = &buf->arg;
+
-+ if (ret) {
-+ DRM_ERROR("Could not map relocation buffer.\n"
-+ "\tReloc buffer id 0x%08x.\n"
-+ "\tReloc first page %d.\n"
-+ "\tReloc num pages %d.\n",
-+ reloc_handle, reloc_first_page, reloc_num_pages);
-+ goto out;
-+ }
++ buf->copy_back = 0;
++ xa->op = PSB_XHW_FIRE_RASTER;
++ xa->issue_irq = 0;
++ xa->arg.sb.fire_flags = 0;
+
-+ reloc = (struct drm_psb_reloc *)
-+ ((unsigned long)drm_bmo_virtual(&reloc_kmap, &reloc_is_iomem) +
-+ reloc_offset);
++ return psb_xhw_add(dev_priv, buf);
++}
+
-+ for (count = 0; count < num_relocs; ++count) {
-+ ret = psb_apply_reloc(dev_priv, fence_class,
-+ reloc, buffers,
-+ num_buffers, &dst_cache,
-+ no_wait, interruptible);
-+ if (ret)
-+ goto out1;
-+ reloc++;
-+ }
++int psb_xhw_vistest(struct drm_psb_private *dev_priv, struct psb_xhw_buf *buf)
++{
++ struct drm_psb_xhw_arg *xa = &buf->arg;
+
-+ out1:
-+ drm_bo_kunmap(&reloc_kmap);
-+ out:
-+ if (registered) {
-+ spin_lock(&dev_priv->reloc_lock);
-+ dev_priv->rel_mapped_pages -= reloc_num_pages;
-+ spin_unlock(&dev_priv->reloc_lock);
-+ DRM_WAKEUP(&dev_priv->rel_mapped_queue);
-+ }
++ buf->copy_back = 1;
++ xa->op = PSB_XHW_VISTEST;
++ /*
++ * Could perhaps decrease latency somewhat by
++ * issuing an irq in this case.
++ */
++ xa->issue_irq = 0;
++ xa->irq_op = PSB_UIRQ_VISTEST;
++ return psb_xhw_add(dev_priv, buf);
++}
+
-+ psb_clear_dstbuf_cache(&dst_cache);
-+ if (reloc_buffer)
-+ drm_bo_usage_deref_unlocked(&reloc_buffer);
-+ return ret;
++int psb_xhw_scene_bind_fire(struct drm_psb_private *dev_priv,
++ struct psb_xhw_buf *buf,
++ uint32_t fire_flags,
++ uint32_t hw_context,
++ uint32_t * cookie,
++ uint32_t * oom_cmds,
++ uint32_t num_oom_cmds,
++ uint32_t offset, uint32_t engine, uint32_t flags)
++{
++ struct drm_psb_xhw_arg *xa = &buf->arg;
++
++ buf->copy_back = (fire_flags & PSB_FIRE_FLAG_XHW_OOM);
++ xa->op = PSB_XHW_SCENE_BIND_FIRE;
++ xa->issue_irq = (buf->copy_back) ? 1 : 0;
++ if (unlikely(buf->copy_back))
++ xa->irq_op = (engine == PSB_SCENE_ENGINE_TA) ?
++ PSB_UIRQ_FIRE_TA_REPLY : PSB_UIRQ_FIRE_RASTER_REPLY;
++ else
++ xa->irq_op = 0;
++ xa->arg.sb.fire_flags = fire_flags;
++ xa->arg.sb.hw_context = hw_context;
++ xa->arg.sb.offset = offset;
++ xa->arg.sb.engine = engine;
++ xa->arg.sb.flags = flags;
++ xa->arg.sb.num_oom_cmds = num_oom_cmds;
++ memcpy(xa->cookie, cookie, sizeof(xa->cookie));
++ if (num_oom_cmds)
++ memcpy(xa->arg.sb.oom_cmds, oom_cmds,
++ sizeof(uint32_t) * num_oom_cmds);
++ return psb_xhw_add(dev_priv, buf);
+}
+
-+static int psb_cmdbuf_2d(struct drm_file *priv,
-+ struct drm_psb_cmdbuf_arg *arg,
-+ struct drm_buffer_object *cmd_buffer,
-+ struct drm_fence_arg *fence_arg)
++int psb_xhw_reset_dpm(struct drm_psb_private *dev_priv, struct psb_xhw_buf *buf)
+{
-+ struct drm_device *dev = priv->minor->dev;
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
++ struct drm_psb_xhw_arg *xa = &buf->arg;
+ int ret;
+
-+ ret = mutex_lock_interruptible(&dev_priv->reset_mutex);
-+ if (ret)
-+ return -EAGAIN;
++ buf->copy_back = 1;
++ xa->op = PSB_XHW_RESET_DPM;
++ xa->issue_irq = 0;
++ xa->irq_op = 0;
+
-+ ret = psb_submit_copy_cmdbuf(dev, cmd_buffer, arg->cmdbuf_offset,
-+ arg->cmdbuf_size, PSB_ENGINE_2D, NULL);
++ ret = psb_xhw_add(dev_priv, buf);
+ if (ret)
-+ goto out_unlock;
++ return ret;
+
-+ psb_fence_or_sync(priv, PSB_ENGINE_2D, arg, fence_arg, NULL);
++ (void)wait_event_timeout(dev_priv->xhw_caller_queue,
++ atomic_read(&buf->done), 3 * DRM_HZ);
+
-+ mutex_lock(&cmd_buffer->mutex);
-+ if (cmd_buffer->fence != NULL)
-+ drm_fence_usage_deref_unlocked(&cmd_buffer->fence);
-+ mutex_unlock(&cmd_buffer->mutex);
-+ out_unlock:
-+ mutex_unlock(&dev_priv->reset_mutex);
-+ return ret;
++ if (!atomic_read(&buf->done)) {
++ psb_xhw_clean_buf(dev_priv, buf);
++ return -EBUSY;
++ }
++
++ return xa->ret;
+}
+
-+#if 0
-+static int psb_dump_page(struct drm_buffer_object *bo,
-+ unsigned int page_offset, unsigned int num)
++int psb_xhw_check_lockup(struct drm_psb_private *dev_priv,
++ struct psb_xhw_buf *buf, uint32_t * value)
+{
-+ struct drm_bo_kmap_obj kmobj;
-+ int is_iomem;
-+ uint32_t *p;
++ struct drm_psb_xhw_arg *xa = &buf->arg;
+ int ret;
-+ unsigned int i;
+
-+ ret = drm_bo_kmap(bo, page_offset, 1, &kmobj);
-+ if (ret)
-+ return ret;
-+
-+ p = drm_bmo_virtual(&kmobj, &is_iomem);
-+ for (i = 0; i < num; ++i)
-+ PSB_DEBUG_GENERAL("0x%04x: 0x%08x\n", i, *p++);
++ *value = 0;
+
-+ drm_bo_kunmap(&kmobj);
-+ return 0;
++ buf->copy_back = 1;
++ xa->op = PSB_XHW_CHECK_LOCKUP;
++ xa->issue_irq = 0;
++ xa->irq_op = 0;
++
++ ret = psb_xhw_add(dev_priv, buf);
++ if (ret)
++ return ret;
++
++ (void)wait_event_timeout(dev_priv->xhw_caller_queue,
++ atomic_read(&buf->done), DRM_HZ * 3);
++
++ if (!atomic_read(&buf->done)) {
++ psb_xhw_clean_buf(dev_priv, buf);
++ return -EBUSY;
++ }
++
++ if (!xa->ret)
++ *value = xa->arg.cl.value;
++
++ return xa->ret;
+}
-+#endif
+
-+static void psb_idle_engine(struct drm_device *dev, int engine)
++static int psb_xhw_terminate(struct drm_psb_private *dev_priv,
++ struct psb_xhw_buf *buf)
+{
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
-+ uint32_t dummy;
-+
-+ switch (engine) {
-+ case PSB_ENGINE_2D:
++ struct drm_psb_xhw_arg *xa = &buf->arg;
++ unsigned long irq_flags;
+
-+ /*
-+ * Make sure we flush 2D properly using a dummy
-+ * fence sequence emit.
-+ */
++ buf->copy_back = 0;
++ xa->op = PSB_XHW_TERMINATE;
++ xa->issue_irq = 0;
+
-+ (void)psb_fence_emit_sequence(dev, PSB_ENGINE_2D, 0,
-+ &dummy, &dummy);
-+ psb_2d_lock(dev_priv);
-+ (void)psb_idle_2d(dev);
-+ psb_2d_unlock(dev_priv);
-+ break;
-+ case PSB_ENGINE_TA:
-+ case PSB_ENGINE_RASTERIZER:
-+ case PSB_ENGINE_HPRAST:
-+ (void)psb_idle_3d(dev);
-+ break;
-+ default:
++ spin_lock_irqsave(&dev_priv->xhw_lock, irq_flags);
++ dev_priv->xhw_submit_ok = 0;
++ atomic_set(&buf->done, 0);
++ if (!list_empty(&buf->head)) {
++ DRM_ERROR("Recursive list adding.\n");
++ goto out;
++ }
++ list_add_tail(&buf->head, &dev_priv->xhw_in);
++ out:
++ spin_unlock_irqrestore(&dev_priv->xhw_lock, irq_flags);
++ wake_up_interruptible(&dev_priv->xhw_queue);
+
-+ /*
-+ * FIXME: Insert video engine idle command here.
-+ */
++ (void)wait_event_timeout(dev_priv->xhw_caller_queue,
++ atomic_read(&buf->done), DRM_HZ / 10);
+
-+ break;
++ if (!atomic_read(&buf->done)) {
++ DRM_ERROR("Xpsb terminate timeout.\n");
++ psb_xhw_clean_buf(dev_priv, buf);
++ return -EBUSY;
+ }
++
++ return 0;
+}
+
-+void psb_fence_or_sync(struct drm_file *priv,
-+ int engine,
-+ struct drm_psb_cmdbuf_arg *arg,
-+ struct drm_fence_arg *fence_arg,
-+ struct drm_fence_object **fence_p)
++int psb_xhw_ta_mem_info(struct drm_psb_private *dev_priv,
++ struct psb_xhw_buf *buf,
++ uint32_t pages, uint32_t * hw_cookie, uint32_t * size)
+{
-+ struct drm_device *dev = priv->minor->dev;
++ struct drm_psb_xhw_arg *xa = &buf->arg;
+ int ret;
-+ struct drm_fence_object *fence;
+
-+ ret = drm_fence_buffer_objects(dev, NULL, arg->fence_flags,
-+ NULL, &fence);
++ buf->copy_back = 1;
++ xa->op = PSB_XHW_TA_MEM_INFO;
++ xa->issue_irq = 0;
++ xa->irq_op = 0;
++ xa->arg.bi.pages = pages;
+
-+ if (ret) {
++ ret = psb_xhw_add(dev_priv, buf);
++ if (ret)
++ return ret;
+
-+ /*
-+ * Fence creation failed.
-+ * Fall back to synchronous operation and idle the engine.
-+ */
++ (void)wait_event_timeout(dev_priv->xhw_caller_queue,
++ atomic_read(&buf->done), DRM_HZ);
+
-+ psb_idle_engine(dev, engine);
-+ if (!(arg->fence_flags & DRM_FENCE_FLAG_NO_USER)) {
++ if (!atomic_read(&buf->done)) {
++ psb_xhw_clean_buf(dev_priv, buf);
++ return -EBUSY;
++ }
+
-+ /*
-+ * Communicate to user-space that
-+ * fence creation has failed and that
-+ * the engine is idle.
-+ */
++ if (!xa->ret)
++ memcpy(hw_cookie, xa->cookie, sizeof(xa->cookie));
+
-+ fence_arg->handle = ~0;
-+ fence_arg->error = ret;
-+ }
++ *size = xa->arg.bi.size;
++ return xa->ret;
++}
+
-+ drm_putback_buffer_objects(dev);
-+ if (fence_p)
-+ *fence_p = NULL;
-+ return;
-+ }
++int psb_xhw_ta_mem_load(struct drm_psb_private *dev_priv,
++ struct psb_xhw_buf *buf,
++ uint32_t flags,
++ uint32_t param_offset,
++ uint32_t pt_offset, uint32_t * hw_cookie)
++{
++ struct drm_psb_xhw_arg *xa = &buf->arg;
++ int ret;
+
-+ if (!(arg->fence_flags & DRM_FENCE_FLAG_NO_USER)) {
++ buf->copy_back = 1;
++ xa->op = PSB_XHW_TA_MEM_LOAD;
++ xa->issue_irq = 0;
++ xa->irq_op = 0;
++ xa->arg.bl.flags = flags;
++ xa->arg.bl.param_offset = param_offset;
++ xa->arg.bl.pt_offset = pt_offset;
++ memcpy(xa->cookie, hw_cookie, sizeof(xa->cookie));
+
-+ ret = drm_fence_add_user_object(priv, fence,
-+ arg->fence_flags &
-+ DRM_FENCE_FLAG_SHAREABLE);
-+ if (!ret)
-+ drm_fence_fill_arg(fence, fence_arg);
-+ else {
-+ /*
-+ * Fence user object creation failed.
-+ * We must idle the engine here as well, as user-
-+ * space expects a fence object to wait on. Since we
-+ * have a fence object we wait for it to signal
-+ * to indicate engine "sufficiently" idle.
-+ */
++ ret = psb_xhw_add(dev_priv, buf);
++ if (ret)
++ return ret;
+
-+ (void)drm_fence_object_wait(fence, 0, 1, fence->type);
-+ drm_fence_usage_deref_unlocked(&fence);
-+ fence_arg->handle = ~0;
-+ fence_arg->error = ret;
-+ }
++ (void)wait_event_timeout(dev_priv->xhw_caller_queue,
++ atomic_read(&buf->done), 3 * DRM_HZ);
++
++ if (!atomic_read(&buf->done)) {
++ psb_xhw_clean_buf(dev_priv, buf);
++ return -EBUSY;
+ }
+
-+ if (fence_p)
-+ *fence_p = fence;
-+ else if (fence)
-+ drm_fence_usage_deref_unlocked(&fence);
++ if (!xa->ret)
++ memcpy(hw_cookie, xa->cookie, sizeof(xa->cookie));
++
++ return xa->ret;
+}
+
-+int psb_handle_copyback(struct drm_device *dev,
-+ struct psb_buflist_item *buffers,
-+ unsigned int num_buffers, int ret, void *data)
++int psb_xhw_ta_oom(struct drm_psb_private *dev_priv,
++ struct psb_xhw_buf *buf, uint32_t * cookie)
+{
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
-+ struct drm_bo_op_arg arg;
-+ struct psb_buflist_item *item = buffers;
-+ struct drm_buffer_object *bo;
-+ int err = ret;
-+ int i;
++ struct drm_psb_xhw_arg *xa = &buf->arg;
+
+ /*
-+ * Clear the unfenced use base register lists and buffer lists.
++ * This calls the extensive closed source
++ * OOM handler, which resolves the condition and
++ * sends a reply telling the scheduler what to do
++ * with the task.
+ */
+
-+ if (ret) {
-+ drm_regs_fence(&dev_priv->use_manager, NULL);
-+ drm_putback_buffer_objects(dev);
-+ }
-+
-+ if (ret != -EAGAIN) {
-+ for (i = 0; i < num_buffers; ++i) {
-+ arg.handled = 1;
-+ arg.d.rep.ret = item->ret;
-+ bo = item->bo;
-+ mutex_lock(&bo->mutex);
-+ drm_bo_fill_rep_arg(bo, &arg.d.rep.bo_info);
-+ mutex_unlock(&bo->mutex);
-+ if (copy_to_user(item->data, &arg, sizeof(arg)))
-+ err = -EFAULT;
-+ ++item;
-+ }
-+ }
++ buf->copy_back = 1;
++ xa->op = PSB_XHW_OOM;
++ xa->issue_irq = 1;
++ xa->irq_op = PSB_UIRQ_OOM_REPLY;
++ memcpy(xa->cookie, cookie, sizeof(xa->cookie));
+
-+ return err;
++ return psb_xhw_add(dev_priv, buf);
+}
+
-+static int psb_cmdbuf_video(struct drm_file *priv,
-+ struct drm_psb_cmdbuf_arg *arg,
-+ unsigned int num_buffers,
-+ struct drm_buffer_object *cmd_buffer,
-+ struct drm_fence_arg *fence_arg)
++void psb_xhw_ta_oom_reply(struct drm_psb_private *dev_priv,
++ struct psb_xhw_buf *buf,
++ uint32_t * cookie,
++ uint32_t * bca, uint32_t * rca, uint32_t * flags)
+{
-+ struct drm_device *dev = priv->minor->dev;
-+ struct drm_fence_object *fence;
-+ int ret;
++ struct drm_psb_xhw_arg *xa = &buf->arg;
+
+ /*
-+ * Check this. Doesn't seem right. Have fencing done AFTER command
-+ * submission and make sure drm_psb_idle idles the MSVDX completely.
++ * Get info about how to schedule an OOM task.
+ */
+
-+ psb_fence_or_sync(priv, PSB_ENGINE_VIDEO, arg, fence_arg, &fence);
-+ ret = psb_submit_video_cmdbuf(dev, cmd_buffer, arg->cmdbuf_offset,
-+ arg->cmdbuf_size, fence);
++ memcpy(cookie, xa->cookie, sizeof(xa->cookie));
++ *bca = xa->arg.oom.bca;
++ *rca = xa->arg.oom.rca;
++ *flags = xa->arg.oom.flags;
++}
+
-+ if (ret)
-+ return ret;
++void psb_xhw_fire_reply(struct drm_psb_private *dev_priv,
++ struct psb_xhw_buf *buf, uint32_t * cookie)
++{
++ struct drm_psb_xhw_arg *xa = &buf->arg;
++
++ memcpy(cookie, xa->cookie, sizeof(xa->cookie));
++}
++
++int psb_xhw_resume(struct drm_psb_private *dev_priv, struct psb_xhw_buf *buf)
++{
++ struct drm_psb_xhw_arg *xa = &buf->arg;
++
++ buf->copy_back = 0;
++ xa->op = PSB_XHW_RESUME;
++ xa->issue_irq = 0;
++ xa->irq_op = 0;
++ return psb_xhw_add(dev_priv, buf);
++}
++
++void psb_xhw_takedown(struct drm_psb_private *dev_priv)
++{
++}
++
++int psb_xhw_init(struct drm_device *dev)
++{
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
++ unsigned long irq_flags;
++
++ INIT_LIST_HEAD(&dev_priv->xhw_in);
++ dev_priv->xhw_lock = SPIN_LOCK_UNLOCKED;
++ atomic_set(&dev_priv->xhw_client, 0);
++ init_waitqueue_head(&dev_priv->xhw_queue);
++ init_waitqueue_head(&dev_priv->xhw_caller_queue);
++ mutex_init(&dev_priv->xhw_mutex);
++ spin_lock_irqsave(&dev_priv->xhw_lock, irq_flags);
++ dev_priv->xhw_on = 0;
++ spin_unlock_irqrestore(&dev_priv->xhw_lock, irq_flags);
+
-+ drm_fence_usage_deref_unlocked(&fence);
-+ mutex_lock(&cmd_buffer->mutex);
-+ if (cmd_buffer->fence != NULL)
-+ drm_fence_usage_deref_unlocked(&cmd_buffer->fence);
-+ mutex_unlock(&cmd_buffer->mutex);
+ return 0;
+}
+
-+int psb_feedback_buf(struct drm_file *file_priv,
-+ uint32_t feedback_ops,
-+ uint32_t handle,
-+ uint32_t offset,
-+ uint32_t feedback_breakpoints,
-+ uint32_t feedback_size, struct psb_feedback_info *feedback)
++static int psb_xhw_init_init(struct drm_device *dev,
++ struct drm_file *file_priv,
++ struct drm_psb_xhw_init_arg *arg)
+{
-+ struct drm_buffer_object *bo;
-+ struct page *page;
-+ uint32_t page_no;
-+ uint32_t page_offset;
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
+ int ret;
++ int is_iomem;
+
-+ if (feedback_ops & ~PSB_FEEDBACK_OP_VISTEST) {
-+ DRM_ERROR("Illegal feedback op.\n");
-+ return -EINVAL;
-+ }
++ if (atomic_add_unless(&dev_priv->xhw_client, 1, 1)) {
++ unsigned long irq_flags;
+
-+ if (feedback_breakpoints != 0) {
-+ DRM_ERROR("Feedback breakpoints not implemented yet.\n");
-+ return -EINVAL;
-+ }
++ mutex_lock(&dev->struct_mutex);
++ dev_priv->xhw_bo =
++ drm_lookup_buffer_object(file_priv, arg->buffer_handle, 1);
++ mutex_unlock(&dev->struct_mutex);
++ if (!dev_priv->xhw_bo) {
++ ret = -EINVAL;
++ goto out_err;
++ }
++ ret = drm_bo_kmap(dev_priv->xhw_bo, 0,
++ dev_priv->xhw_bo->num_pages,
++ &dev_priv->xhw_kmap);
++ if (ret) {
++ DRM_ERROR("Failed mapping X server "
++ "communications buffer.\n");
++ goto out_err0;
++ }
++ dev_priv->xhw = drm_bmo_virtual(&dev_priv->xhw_kmap, &is_iomem);
++ if (is_iomem) {
++ DRM_ERROR("X server communications buffer"
++ "is in device memory.\n");
++ ret = -EINVAL;
++ goto out_err1;
++ }
++ dev_priv->xhw_file = file_priv;
+
-+ if (feedback_size < PSB_HW_FEEDBACK_SIZE * sizeof(uint32_t)) {
-+ DRM_ERROR("Feedback buffer size too small.\n");
-+ return -EINVAL;
++ spin_lock_irqsave(&dev_priv->xhw_lock, irq_flags);
++ dev_priv->xhw_on = 1;
++ dev_priv->xhw_submit_ok = 1;
++ spin_unlock_irqrestore(&dev_priv->xhw_lock, irq_flags);
++ return 0;
++ } else {
++ DRM_ERROR("Xhw is already initialized.\n");
++ return -EBUSY;
+ }
++ out_err1:
++ dev_priv->xhw = NULL;
++ drm_bo_kunmap(&dev_priv->xhw_kmap);
++ out_err0:
++ drm_bo_usage_deref_unlocked(&dev_priv->xhw_bo);
++ out_err:
++ atomic_dec(&dev_priv->xhw_client);
++ return ret;
++}
+
-+ page_offset = offset & ~PAGE_MASK;
-+ if ((PAGE_SIZE - PSB_HW_FEEDBACK_SIZE * sizeof(uint32_t))
-+ < page_offset) {
-+ DRM_ERROR("Illegal feedback buffer alignment.\n");
-+ return -EINVAL;
-+ }
++static void psb_xhw_queue_empty(struct drm_psb_private *dev_priv)
++{
++ struct psb_xhw_buf *cur_buf, *next;
++ unsigned long irq_flags;
+
-+ ret = drm_bo_handle_validate(file_priv,
-+ handle,
-+ PSB_ENGINE_TA,
-+ DRM_BO_FLAG_MEM_LOCAL |
-+ DRM_BO_FLAG_CACHED |
-+ DRM_BO_FLAG_WRITE |
-+ PSB_BO_FLAG_FEEDBACK,
-+ DRM_BO_MASK_MEM |
-+ DRM_BO_FLAG_CACHED |
-+ DRM_BO_FLAG_WRITE |
-+ PSB_BO_FLAG_FEEDBACK, 0, 0, NULL, &bo);
-+ if (ret)
-+ return ret;
++ spin_lock_irqsave(&dev_priv->xhw_lock, irq_flags);
++ dev_priv->xhw_submit_ok = 0;
+
-+ page_no = offset >> PAGE_SHIFT;
-+ if (page_no >= bo->num_pages) {
-+ ret = -EINVAL;
-+ DRM_ERROR("Illegal feedback buffer offset.\n");
-+ goto out_unref;
++ list_for_each_entry_safe(cur_buf, next, &dev_priv->xhw_in, head) {
++ list_del_init(&cur_buf->head);
++ if (cur_buf->copy_back) {
++ cur_buf->arg.ret = -EINVAL;
++ }
++ atomic_set(&cur_buf->done, 1);
+ }
++ spin_unlock_irqrestore(&dev_priv->xhw_lock, irq_flags);
++ wake_up(&dev_priv->xhw_caller_queue);
++}
+
-+ if (bo->ttm == NULL) {
-+ ret = -EINVAL;
-+ DRM_ERROR("Vistest buffer without TTM.\n");
-+ goto out_unref;
-+ }
++void psb_xhw_init_takedown(struct drm_psb_private *dev_priv,
++ struct drm_file *file_priv, int closing)
++{
+
-+ page = drm_ttm_get_page(bo->ttm, page_no);
-+ if (!page) {
-+ ret = -ENOMEM;
-+ goto out_unref;
-+ }
++ if (dev_priv->xhw_file == file_priv &&
++ atomic_add_unless(&dev_priv->xhw_client, -1, 0)) {
+
-+ feedback->page = page;
-+ feedback->bo = bo;
-+ feedback->offset = page_offset;
-+ return 0;
++ if (closing)
++ psb_xhw_queue_empty(dev_priv);
++ else {
++ struct psb_xhw_buf buf;
++ INIT_LIST_HEAD(&buf.head);
+
-+ out_unref:
-+ drm_bo_usage_deref_unlocked(&bo);
-+ return ret;
++ psb_xhw_terminate(dev_priv, &buf);
++ psb_xhw_queue_empty(dev_priv);
++ }
++
++ dev_priv->xhw = NULL;
++ drm_bo_kunmap(&dev_priv->xhw_kmap);
++ drm_bo_usage_deref_unlocked(&dev_priv->xhw_bo);
++ dev_priv->xhw_file = NULL;
++ }
+}
+
-+int psb_cmdbuf_ioctl(struct drm_device *dev, void *data,
-+ struct drm_file *file_priv)
++int psb_xhw_init_ioctl(struct drm_device *dev, void *data,
++ struct drm_file *file_priv)
+{
-+ drm_psb_cmdbuf_arg_t *arg = data;
-+ int ret = 0;
-+ unsigned num_buffers;
-+ struct drm_buffer_object *cmd_buffer = NULL;
-+ struct drm_buffer_object *ta_buffer = NULL;
-+ struct drm_buffer_object *oom_buffer = NULL;
-+ struct drm_fence_arg fence_arg;
-+ struct drm_psb_scene user_scene;
-+ struct psb_scene_pool *pool = NULL;
-+ struct psb_scene *scene = NULL;
++ struct drm_psb_xhw_init_arg *arg = (struct drm_psb_xhw_init_arg *)data;
+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)file_priv->minor->dev->dev_private;
-+ int engine;
-+ struct psb_feedback_info feedback;
-+
-+ if (!dev_priv)
-+ return -EINVAL;
++ (struct drm_psb_private *)dev->dev_private;
+
-+ ret = drm_bo_read_lock(&dev->bm.bm_lock);
-+ if (ret)
-+ return ret;
++ switch (arg->operation) {
++ case PSB_XHW_INIT:
++ return psb_xhw_init_init(dev, file_priv, arg);
++ case PSB_XHW_TAKEDOWN:
++ psb_xhw_init_takedown(dev_priv, file_priv, 0);
++ }
++ return 0;
++}
+
-+ num_buffers = PSB_NUM_VALIDATE_BUFFERS;
++static int psb_xhw_in_empty(struct drm_psb_private *dev_priv)
++{
++ int empty;
++ unsigned long irq_flags;
+
-+ ret = mutex_lock_interruptible(&dev_priv->cmdbuf_mutex);
-+ if (ret) {
-+ drm_bo_read_unlock(&dev->bm.bm_lock);
-+ return -EAGAIN;
-+ }
-+ if (unlikely(dev_priv->buffers == NULL)) {
-+ dev_priv->buffers = vmalloc(PSB_NUM_VALIDATE_BUFFERS *
-+ sizeof(*dev_priv->buffers));
-+ if (dev_priv->buffers == NULL) {
-+ drm_bo_read_unlock(&dev->bm.bm_lock);
-+ return -ENOMEM;
-+ }
-+ }
++ spin_lock_irqsave(&dev_priv->xhw_lock, irq_flags);
++ empty = list_empty(&dev_priv->xhw_in);
++ spin_unlock_irqrestore(&dev_priv->xhw_lock, irq_flags);
++ return empty;
++}
+
++int psb_xhw_handler(struct drm_psb_private *dev_priv)
++{
++ unsigned long irq_flags;
++ struct drm_psb_xhw_arg *xa;
++ struct psb_xhw_buf *buf;
+
-+ engine = (arg->engine == PSB_ENGINE_RASTERIZER) ?
-+ PSB_ENGINE_TA : arg->engine;
++ spin_lock_irqsave(&dev_priv->xhw_lock, irq_flags);
+
-+ ret =
-+ psb_validate_buffer_list(file_priv, engine,
-+ (unsigned long)arg->buffer_list,
-+ dev_priv->buffers, &num_buffers);
-+ if (ret)
-+ goto out_err0;
++ if (!dev_priv->xhw_on) {
++ spin_unlock_irqrestore(&dev_priv->xhw_lock, irq_flags);
++ return -EINVAL;
++ }
+
-+ ret = psb_fixup_relocs(file_priv, engine, arg->num_relocs,
-+ arg->reloc_offset, arg->reloc_handle,
-+ dev_priv->buffers, num_buffers, 0, 1);
-+ if (ret)
-+ goto out_err0;
++ buf = dev_priv->xhw_cur_buf;
++ if (buf && buf->copy_back) {
++ xa = &buf->arg;
++ memcpy(xa, dev_priv->xhw, sizeof(*xa));
++ dev_priv->comm[PSB_COMM_USER_IRQ] = xa->irq_op;
++ atomic_set(&buf->done, 1);
++ wake_up(&dev_priv->xhw_caller_queue);
++ } else
++ dev_priv->comm[PSB_COMM_USER_IRQ] = 0;
+
-+ mutex_lock(&dev->struct_mutex);
-+ cmd_buffer = drm_lookup_buffer_object(file_priv, arg->cmdbuf_handle, 1);
-+ mutex_unlock(&dev->struct_mutex);
-+ if (!cmd_buffer) {
-+ ret = -EINVAL;
-+ goto out_err0;
-+ }
++ dev_priv->xhw_cur_buf = 0;
++ spin_unlock_irqrestore(&dev_priv->xhw_lock, irq_flags);
++ return 0;
++}
+
-+ switch (arg->engine) {
-+ case PSB_ENGINE_2D:
-+ ret = psb_cmdbuf_2d(file_priv, arg, cmd_buffer, &fence_arg);
-+ if (ret)
-+ goto out_err0;
-+ break;
-+ case PSB_ENGINE_VIDEO:
-+ ret =
-+ psb_cmdbuf_video(file_priv, arg, num_buffers, cmd_buffer,
-+ &fence_arg);
-+ if (ret)
-+ goto out_err0;
-+ break;
-+ case PSB_ENGINE_RASTERIZER:
-+ ret = psb_cmdbuf_raster(file_priv, arg, cmd_buffer, &fence_arg);
-+ if (ret)
-+ goto out_err0;
-+ break;
-+ case PSB_ENGINE_TA:
-+ if (arg->ta_handle == arg->cmdbuf_handle) {
-+ mutex_lock(&dev->struct_mutex);
-+ atomic_inc(&cmd_buffer->usage);
-+ ta_buffer = cmd_buffer;
-+ mutex_unlock(&dev->struct_mutex);
-+ } else {
-+ mutex_lock(&dev->struct_mutex);
-+ ta_buffer =
-+ drm_lookup_buffer_object(file_priv,
-+ arg->ta_handle, 1);
-+ mutex_unlock(&dev->struct_mutex);
-+ if (!ta_buffer) {
-+ ret = -EINVAL;
-+ goto out_err0;
-+ }
-+ }
-+ if (arg->oom_size != 0) {
-+ if (arg->oom_handle == arg->cmdbuf_handle) {
-+ mutex_lock(&dev->struct_mutex);
-+ atomic_inc(&cmd_buffer->usage);
-+ oom_buffer = cmd_buffer;
-+ mutex_unlock(&dev->struct_mutex);
-+ } else {
-+ mutex_lock(&dev->struct_mutex);
-+ oom_buffer =
-+ drm_lookup_buffer_object(file_priv,
-+ arg->oom_handle,
-+ 1);
-+ mutex_unlock(&dev->struct_mutex);
-+ if (!oom_buffer) {
-+ ret = -EINVAL;
-+ goto out_err0;
-+ }
-+ }
-+ }
++int psb_xhw_ioctl(struct drm_device *dev, void *data,
++ struct drm_file *file_priv)
++{
++ struct drm_psb_private *dev_priv =
++ (struct drm_psb_private *)dev->dev_private;
++ unsigned long irq_flags;
++ struct drm_psb_xhw_arg *xa;
++ int ret;
++ struct list_head *list;
++ struct psb_xhw_buf *buf;
+
-+ ret = copy_from_user(&user_scene, (void __user *)
-+ ((unsigned long)arg->scene_arg),
-+ sizeof(user_scene));
-+ if (ret)
-+ goto out_err0;
++ if (!dev_priv)
++ return -EINVAL;
+
-+ if (!user_scene.handle_valid) {
-+ pool = psb_scene_pool_alloc(file_priv, 0,
-+ user_scene.num_buffers,
-+ user_scene.w, user_scene.h);
-+ if (!pool) {
-+ ret = -ENOMEM;
-+ goto out_err0;
-+ }
++ if (mutex_lock_interruptible(&dev_priv->xhw_mutex))
++ return -EAGAIN;
+
-+ user_scene.handle = psb_scene_pool_handle(pool);
-+ user_scene.handle_valid = 1;
-+ ret = copy_to_user((void __user *)
-+ ((unsigned long)arg->scene_arg),
-+ &user_scene, sizeof(user_scene));
++ if (psb_forced_user_interrupt(dev_priv)) {
++ mutex_unlock(&dev_priv->xhw_mutex);
++ return -EINVAL;
++ }
+
-+ if (ret)
-+ goto out_err0;
-+ } else {
-+ mutex_lock(&dev->struct_mutex);
-+ pool = psb_scene_pool_lookup_devlocked(file_priv,
-+ user_scene.
-+ handle, 1);
-+ mutex_unlock(&dev->struct_mutex);
-+ if (!pool) {
-+ ret = -EINVAL;
-+ goto out_err0;
-+ }
++ spin_lock_irqsave(&dev_priv->xhw_lock, irq_flags);
++ while (list_empty(&dev_priv->xhw_in)) {
++ spin_unlock_irqrestore(&dev_priv->xhw_lock, irq_flags);
++ ret = wait_event_interruptible_timeout(dev_priv->xhw_queue,
++ !psb_xhw_in_empty
++ (dev_priv), DRM_HZ);
++ if (ret == -ERESTARTSYS || ret == 0) {
++ mutex_unlock(&dev_priv->xhw_mutex);
++ return -EAGAIN;
+ }
++ spin_lock_irqsave(&dev_priv->xhw_lock, irq_flags);
++ }
+
-+ mutex_lock(&dev_priv->reset_mutex);
-+ ret = psb_validate_scene_pool(pool, 0, 0, 0,
-+ user_scene.w,
-+ user_scene.h,
-+ arg->ta_flags &
-+ PSB_TA_FLAG_LASTPASS, &scene);
-+ mutex_unlock(&dev_priv->reset_mutex);
++ list = dev_priv->xhw_in.next;
++ list_del_init(list);
+
-+ if (ret)
-+ goto out_err0;
++ buf = list_entry(list, struct psb_xhw_buf, head);
++ xa = &buf->arg;
++ memcpy(dev_priv->xhw, xa, sizeof(*xa));
+
-+ memset(&feedback, 0, sizeof(feedback));
-+ if (arg->feedback_ops) {
-+ ret = psb_feedback_buf(file_priv,
-+ arg->feedback_ops,
-+ arg->feedback_handle,
-+ arg->feedback_offset,
-+ arg->feedback_breakpoints,
-+ arg->feedback_size, &feedback);
-+ if (ret)
-+ goto out_err0;
-+ }
-+ ret = psb_cmdbuf_ta(file_priv, arg, cmd_buffer, ta_buffer,
-+ oom_buffer, scene, &feedback, &fence_arg);
-+ if (ret)
-+ goto out_err0;
-+ break;
-+ default:
-+ DRM_ERROR("Unimplemented command submission mechanism (%x).\n",
-+ arg->engine);
-+ ret = -EINVAL;
-+ goto out_err0;
++ if (unlikely(buf->copy_back))
++ dev_priv->xhw_cur_buf = buf;
++ else {
++ atomic_set(&buf->done, 1);
++ dev_priv->xhw_cur_buf = NULL;
+ }
+
-+ if (!(arg->fence_flags & DRM_FENCE_FLAG_NO_USER)) {
-+ ret = copy_to_user((void __user *)
-+ ((unsigned long)arg->fence_arg),
-+ &fence_arg, sizeof(fence_arg));
++ if (xa->op == PSB_XHW_TERMINATE) {
++ dev_priv->xhw_on = 0;
++ wake_up(&dev_priv->xhw_caller_queue);
+ }
++ spin_unlock_irqrestore(&dev_priv->xhw_lock, irq_flags);
+
-+ out_err0:
-+ ret =
-+ psb_handle_copyback(dev, dev_priv->buffers, num_buffers, ret, data);
-+ mutex_lock(&dev->struct_mutex);
-+ if (scene)
-+ psb_scene_unref_devlocked(&scene);
-+ if (pool)
-+ psb_scene_pool_unref_devlocked(&pool);
-+ if (cmd_buffer)
-+ drm_bo_usage_deref_locked(&cmd_buffer);
-+ if (ta_buffer)
-+ drm_bo_usage_deref_locked(&ta_buffer);
-+ if (oom_buffer)
-+ drm_bo_usage_deref_locked(&oom_buffer);
-+
-+ psb_dereference_buffers_locked(dev_priv->buffers, num_buffers);
-+ mutex_unlock(&dev->struct_mutex);
-+ mutex_unlock(&dev_priv->cmdbuf_mutex);
++ mutex_unlock(&dev_priv->xhw_mutex);
+
-+ drm_bo_read_unlock(&dev->bm.bm_lock);
-+ return ret;
++ return 0;
+}
-Index: linux-2.6.28/drivers/gpu/drm/psb/psb_xhw.c
+Index: linux-2.6.28/drivers/gpu/drm/Kconfig
+===================================================================
+--- linux-2.6.28.orig/drivers/gpu/drm/Kconfig 2009-02-12 09:14:37.000000000 +0000
++++ linux-2.6.28/drivers/gpu/drm/Kconfig 2009-02-12 09:14:42.000000000 +0000
+@@ -123,3 +123,9 @@
+ help
+ Choose this option if you have a Savage3D/4/SuperSavage/Pro/Twister
+ chipset. If M is selected the module will be called savage.
++
++config DRM_PSB
++ tristate "Intel Poulsbo"
++ depends on DRM && PCI && I2C_ALGOBIT
++ help
++ Choose this option if you have an Intel Poulsbo chipset.
+Index: linux-2.6.28/include/drm/drm_objects.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/psb/psb_xhw.c 2009-02-12 09:14:42.000000000 +0000
-@@ -0,0 +1,614 @@
++++ linux-2.6.28/include/drm/drm_objects.h 2009-02-12 09:14:42.000000000 +0000
+@@ -0,0 +1,717 @@
+/**************************************************************************
-+ * Copyright (c) 2007, Intel Corporation.
-+ * All Rights Reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms and conditions of the GNU General Public License,
-+ * version 2, as published by the Free Software Foundation.
+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
++ * Copyright (c) 2006-2007 Tungsten Graphics, Inc., Cedar Park, TX., USA
++ * All Rights Reserved.
+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
+ *
-+ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
-+ * develop this driver.
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
+ *
-+ **************************************************************************/
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
++ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
++ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ **************************************************************************/
+/*
-+ * Make calls into closed source X server code.
++ * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
+ */
+
-+#include "drmP.h"
-+#include "psb_drv.h"
-+
-+void
-+psb_xhw_clean_buf(struct drm_psb_private *dev_priv, struct psb_xhw_buf *buf)
-+{
-+ unsigned long irq_flags;
++#ifndef _DRM_OBJECTS_H
++#define _DRM_OBJECTS_H
+
-+ spin_lock_irqsave(&dev_priv->xhw_lock, irq_flags);
-+ list_del_init(&buf->head);
-+ if (dev_priv->xhw_cur_buf == buf)
-+ dev_priv->xhw_cur_buf = NULL;
-+ atomic_set(&buf->done, 1);
-+ spin_unlock_irqrestore(&dev_priv->xhw_lock, irq_flags);
-+}
++struct drm_device;
++struct drm_bo_mem_reg;
+
-+static inline int psb_xhw_add(struct drm_psb_private *dev_priv,
-+ struct psb_xhw_buf *buf)
-+{
-+ unsigned long irq_flags;
++/***************************************************
++ * User space objects. (drm_object.c)
++ */
+
-+ spin_lock_irqsave(&dev_priv->xhw_lock, irq_flags);
-+ atomic_set(&buf->done, 0);
-+ if (unlikely(!dev_priv->xhw_submit_ok)) {
-+ spin_unlock_irqrestore(&dev_priv->xhw_lock, irq_flags);
-+ DRM_ERROR("No Xpsb 3D extension available.\n");
-+ return -EINVAL;
-+ }
-+ if (!list_empty(&buf->head)) {
-+ DRM_ERROR("Recursive list adding.\n");
-+ goto out;
-+ }
-+ list_add_tail(&buf->head, &dev_priv->xhw_in);
-+ wake_up_interruptible(&dev_priv->xhw_queue);
-+ out:
-+ spin_unlock_irqrestore(&dev_priv->xhw_lock, irq_flags);
-+ return 0;
-+}
++#define drm_user_object_entry(_ptr, _type, _member) container_of(_ptr, _type, _member)
+
-+int psb_xhw_scene_info(struct drm_psb_private *dev_priv,
-+ struct psb_xhw_buf *buf,
-+ uint32_t w,
-+ uint32_t h,
-+ uint32_t * hw_cookie,
-+ uint32_t * bo_size,
-+ uint32_t * clear_p_start, uint32_t * clear_num_pages)
-+{
-+ struct drm_psb_xhw_arg *xa = &buf->arg;
-+ int ret;
++enum drm_object_type {
++ drm_fence_type,
++ drm_buffer_type,
++ drm_lock_type,
++ /*
++ * Add other user space object types here.
++ */
++ drm_driver_type0 = 256,
++ drm_driver_type1,
++ drm_driver_type2,
++ drm_driver_type3,
++ drm_driver_type4
++};
+
-+ buf->copy_back = 1;
-+ xa->op = PSB_XHW_SCENE_INFO;
-+ xa->irq_op = 0;
-+ xa->issue_irq = 0;
-+ xa->arg.si.w = w;
-+ xa->arg.si.h = h;
++/*
++ * A user object is a structure that helps the drm give out user handles
++ * to kernel internal objects and to keep track of these objects so that
++ * they can be destroyed, for example when the user space process exits.
++ * Designed to be accessible using a user space 32-bit handle.
++ */
+
-+ ret = psb_xhw_add(dev_priv, buf);
-+ if (ret)
-+ return ret;
++struct drm_user_object {
++ struct drm_hash_item hash;
++ struct list_head list;
++ enum drm_object_type type;
++ atomic_t refcount;
++ int shareable;
++ struct drm_file *owner;
++ void (*ref_struct_locked) (struct drm_file *priv,
++ struct drm_user_object *obj,
++ enum drm_ref_type ref_action);
++ void (*unref) (struct drm_file *priv, struct drm_user_object *obj,
++ enum drm_ref_type unref_action);
++ void (*remove) (struct drm_file *priv, struct drm_user_object *obj);
++};
+
-+ (void)wait_event_timeout(dev_priv->xhw_caller_queue,
-+ atomic_read(&buf->done), DRM_HZ);
++/*
++ * A ref object is a structure which is used to
++ * keep track of references to user objects and to keep track of these
++ * references so that they can be destroyed for example when the user space
++ * process exits. Designed to be accessible using a pointer to the _user_ object.
++ */
+
-+ if (!atomic_read(&buf->done)) {
-+ psb_xhw_clean_buf(dev_priv, buf);
-+ return -EBUSY;
-+ }
++struct drm_ref_object {
++ struct drm_hash_item hash;
++ struct list_head list;
++ atomic_t refcount;
++ enum drm_ref_type unref_action;
++};
+
-+ if (!xa->ret) {
-+ memcpy(hw_cookie, xa->cookie, sizeof(xa->cookie));
-+ *bo_size = xa->arg.si.size;
-+ *clear_p_start = xa->arg.si.clear_p_start;
-+ *clear_num_pages = xa->arg.si.clear_num_pages;
-+ }
-+ return xa->ret;
-+}
++/**
++ * Must be called with the struct_mutex held.
++ */
+
-+int psb_xhw_fire_raster(struct drm_psb_private *dev_priv,
-+ struct psb_xhw_buf *buf, uint32_t fire_flags)
-+{
-+ struct drm_psb_xhw_arg *xa = &buf->arg;
++extern int drm_add_user_object(struct drm_file *priv, struct drm_user_object *item,
++ int shareable);
++/**
++ * Must be called with the struct_mutex held.
++ */
+
-+ buf->copy_back = 0;
-+ xa->op = PSB_XHW_FIRE_RASTER;
-+ xa->issue_irq = 0;
-+ xa->arg.sb.fire_flags = 0;
++extern struct drm_user_object *drm_lookup_user_object(struct drm_file *priv,
++ uint32_t key);
+
-+ return psb_xhw_add(dev_priv, buf);
-+}
++/*
++ * Must be called with the struct_mutex held. May temporarily release it.
++ */
+
-+int psb_xhw_vistest(struct drm_psb_private *dev_priv, struct psb_xhw_buf *buf)
-+{
-+ struct drm_psb_xhw_arg *xa = &buf->arg;
++extern int drm_add_ref_object(struct drm_file *priv,
++ struct drm_user_object *referenced_object,
++ enum drm_ref_type ref_action);
+
-+ buf->copy_back = 1;
-+ xa->op = PSB_XHW_VISTEST;
-+ /*
-+ * Could perhaps decrease latency somewhat by
-+ * issuing an irq in this case.
-+ */
-+ xa->issue_irq = 0;
-+ xa->irq_op = PSB_UIRQ_VISTEST;
-+ return psb_xhw_add(dev_priv, buf);
-+}
++/*
++ * Must be called with the struct_mutex held.
++ */
+
-+int psb_xhw_scene_bind_fire(struct drm_psb_private *dev_priv,
-+ struct psb_xhw_buf *buf,
-+ uint32_t fire_flags,
-+ uint32_t hw_context,
-+ uint32_t * cookie,
-+ uint32_t * oom_cmds,
-+ uint32_t num_oom_cmds,
-+ uint32_t offset, uint32_t engine, uint32_t flags)
-+{
-+ struct drm_psb_xhw_arg *xa = &buf->arg;
++struct drm_ref_object *drm_lookup_ref_object(struct drm_file *priv,
++ struct drm_user_object *referenced_object,
++ enum drm_ref_type ref_action);
++/*
++ * Must be called with the struct_mutex held.
++ * If "item" has been obtained by a call to drm_lookup_ref_object. You may not
++ * release the struct_mutex before calling drm_remove_ref_object.
++ * This function may temporarily release the struct_mutex.
++ */
+
-+ buf->copy_back = (fire_flags & PSB_FIRE_FLAG_XHW_OOM);
-+ xa->op = PSB_XHW_SCENE_BIND_FIRE;
-+ xa->issue_irq = (buf->copy_back) ? 1 : 0;
-+ if (unlikely(buf->copy_back))
-+ xa->irq_op = (engine == PSB_SCENE_ENGINE_TA) ?
-+ PSB_UIRQ_FIRE_TA_REPLY : PSB_UIRQ_FIRE_RASTER_REPLY;
-+ else
-+ xa->irq_op = 0;
-+ xa->arg.sb.fire_flags = fire_flags;
-+ xa->arg.sb.hw_context = hw_context;
-+ xa->arg.sb.offset = offset;
-+ xa->arg.sb.engine = engine;
-+ xa->arg.sb.flags = flags;
-+ xa->arg.sb.num_oom_cmds = num_oom_cmds;
-+ memcpy(xa->cookie, cookie, sizeof(xa->cookie));
-+ if (num_oom_cmds)
-+ memcpy(xa->arg.sb.oom_cmds, oom_cmds,
-+ sizeof(uint32_t) * num_oom_cmds);
-+ return psb_xhw_add(dev_priv, buf);
-+}
++extern void drm_remove_ref_object(struct drm_file *priv, struct drm_ref_object *item);
++extern int drm_user_object_ref(struct drm_file *priv, uint32_t user_token,
++ enum drm_object_type type,
++ struct drm_user_object **object);
++extern int drm_user_object_unref(struct drm_file *priv, uint32_t user_token,
++ enum drm_object_type type);
+
-+int psb_xhw_reset_dpm(struct drm_psb_private *dev_priv, struct psb_xhw_buf *buf)
-+{
-+ struct drm_psb_xhw_arg *xa = &buf->arg;
-+ int ret;
++/***************************************************
++ * Fence objects. (drm_fence.c)
++ */
+
-+ buf->copy_back = 1;
-+ xa->op = PSB_XHW_RESET_DPM;
-+ xa->issue_irq = 0;
-+ xa->irq_op = 0;
++struct drm_fence_object {
++ struct drm_user_object base;
++ struct drm_device *dev;
++ atomic_t usage;
+
-+ ret = psb_xhw_add(dev_priv, buf);
-+ if (ret)
-+ return ret;
++ /*
++ * The below three fields are protected by the fence manager spinlock.
++ */
+
-+ (void)wait_event_timeout(dev_priv->xhw_caller_queue,
-+ atomic_read(&buf->done), 3 * DRM_HZ);
++ struct list_head ring;
++ int fence_class;
++ uint32_t native_types;
++ uint32_t type;
++ uint32_t signaled_types;
++ uint32_t sequence;
++ uint32_t waiting_types;
++ uint32_t error;
++};
+
-+ if (!atomic_read(&buf->done)) {
-+ psb_xhw_clean_buf(dev_priv, buf);
-+ return -EBUSY;
-+ }
++#define _DRM_FENCE_CLASSES 8
+
-+ return xa->ret;
-+}
++struct drm_fence_class_manager {
++ struct list_head ring;
++ uint32_t pending_flush;
++ uint32_t waiting_types;
++ wait_queue_head_t fence_queue;
++ uint32_t highest_waiting_sequence;
++ uint32_t latest_queued_sequence;
++};
+
-+int psb_xhw_check_lockup(struct drm_psb_private *dev_priv,
-+ struct psb_xhw_buf *buf, uint32_t * value)
-+{
-+ struct drm_psb_xhw_arg *xa = &buf->arg;
-+ int ret;
++struct drm_fence_manager {
++ int initialized;
++ rwlock_t lock;
++ struct drm_fence_class_manager fence_class[_DRM_FENCE_CLASSES];
++ uint32_t num_classes;
++ atomic_t count;
++};
+
-+ *value = 0;
++struct drm_fence_driver {
++ unsigned long *waiting_jiffies;
++ uint32_t num_classes;
++ uint32_t wrap_diff;
++ uint32_t flush_diff;
++ uint32_t sequence_mask;
+
-+ buf->copy_back = 1;
-+ xa->op = PSB_XHW_CHECK_LOCKUP;
-+ xa->issue_irq = 0;
-+ xa->irq_op = 0;
++ /*
++ * Driver implemented functions:
++ * has_irq() : 1 if the hardware can update the indicated type_flags using an
++ * irq handler. 0 if polling is required.
++ *
++ * emit() : Emit a sequence number to the command stream.
++ * Return the sequence number.
++ *
++ * flush() : Make sure the flags indicated in fc->pending_flush will eventually
++ * signal for fc->highest_received_sequence and all preceding sequences.
++ * Acknowledge by clearing the flags fc->pending_flush.
++ *
++ * poll() : Call drm_fence_handler with any new information.
++ *
++ * needed_flush() : Given the current state of the fence->type flags and previusly
++ * executed or queued flushes, return the type_flags that need flushing.
++ *
++ * wait(): Wait for the "mask" flags to signal on a given fence, performing
++ * whatever's necessary to make this happen.
++ */
+
-+ ret = psb_xhw_add(dev_priv, buf);
-+ if (ret)
-+ return ret;
++ int (*has_irq) (struct drm_device *dev, uint32_t fence_class,
++ uint32_t flags);
++ int (*emit) (struct drm_device *dev, uint32_t fence_class,
++ uint32_t flags, uint32_t *breadcrumb,
++ uint32_t *native_type);
++ void (*flush) (struct drm_device *dev, uint32_t fence_class);
++ void (*poll) (struct drm_device *dev, uint32_t fence_class,
++ uint32_t types);
++ uint32_t (*needed_flush) (struct drm_fence_object *fence);
++ int (*wait) (struct drm_fence_object *fence, int lazy,
++ int interruptible, uint32_t mask);
++};
+
-+ (void)wait_event_timeout(dev_priv->xhw_caller_queue,
-+ atomic_read(&buf->done), DRM_HZ * 3);
++extern int drm_fence_wait_polling(struct drm_fence_object *fence, int lazy,
++ int interruptible, uint32_t mask,
++ unsigned long end_jiffies);
++extern void drm_fence_handler(struct drm_device *dev, uint32_t fence_class,
++ uint32_t sequence, uint32_t type,
++ uint32_t error);
++extern void drm_fence_manager_init(struct drm_device *dev);
++extern void drm_fence_manager_takedown(struct drm_device *dev);
++extern void drm_fence_flush_old(struct drm_device *dev, uint32_t fence_class,
++ uint32_t sequence);
++extern int drm_fence_object_flush(struct drm_fence_object *fence,
++ uint32_t type);
++extern int drm_fence_object_signaled(struct drm_fence_object *fence,
++ uint32_t type);
++extern void drm_fence_usage_deref_locked(struct drm_fence_object **fence);
++extern void drm_fence_usage_deref_unlocked(struct drm_fence_object **fence);
++extern struct drm_fence_object *drm_fence_reference_locked(struct drm_fence_object *src);
++extern void drm_fence_reference_unlocked(struct drm_fence_object **dst,
++ struct drm_fence_object *src);
++extern int drm_fence_object_wait(struct drm_fence_object *fence,
++ int lazy, int ignore_signals, uint32_t mask);
++extern int drm_fence_object_create(struct drm_device *dev, uint32_t type,
++ uint32_t fence_flags, uint32_t fence_class,
++ struct drm_fence_object **c_fence);
++extern int drm_fence_object_emit(struct drm_fence_object *fence,
++ uint32_t fence_flags, uint32_t class,
++ uint32_t type);
++extern void drm_fence_fill_arg(struct drm_fence_object *fence,
++ struct drm_fence_arg *arg);
+
-+ if (!atomic_read(&buf->done)) {
-+ psb_xhw_clean_buf(dev_priv, buf);
-+ return -EBUSY;
-+ }
++extern int drm_fence_add_user_object(struct drm_file *priv,
++ struct drm_fence_object *fence,
++ int shareable);
+
-+ if (!xa->ret)
-+ *value = xa->arg.cl.value;
++extern int drm_fence_create_ioctl(struct drm_device *dev, void *data,
++ struct drm_file *file_priv);
++extern int drm_fence_destroy_ioctl(struct drm_device *dev, void *data,
++ struct drm_file *file_priv);
++extern int drm_fence_reference_ioctl(struct drm_device *dev, void *data,
++ struct drm_file *file_priv);
++extern int drm_fence_unreference_ioctl(struct drm_device *dev, void *data,
++ struct drm_file *file_priv);
++extern int drm_fence_signaled_ioctl(struct drm_device *dev, void *data,
++ struct drm_file *file_priv);
++extern int drm_fence_flush_ioctl(struct drm_device *dev, void *data,
++ struct drm_file *file_priv);
++extern int drm_fence_wait_ioctl(struct drm_device *dev, void *data,
++ struct drm_file *file_priv);
++extern int drm_fence_emit_ioctl(struct drm_device *dev, void *data,
++ struct drm_file *file_priv);
++extern int drm_fence_buffers_ioctl(struct drm_device *dev, void *data,
++ struct drm_file *file_priv);
++/**************************************************
++ *TTMs
++ */
+
-+ return xa->ret;
-+}
++/*
++ * The ttm backend GTT interface. (In our case AGP).
++ * Any similar type of device (PCIE?)
++ * needs only to implement these functions to be usable with the TTM interface.
++ * The AGP backend implementation lives in drm_agpsupport.c
++ * basically maps these calls to available functions in agpgart.
++ * Each drm device driver gets an
++ * additional function pointer that creates these types,
++ * so that the device can choose the correct aperture.
++ * (Multiple AGP apertures, etc.)
++ * Most device drivers will let this point to the standard AGP implementation.
++ */
+
-+static int psb_xhw_terminate(struct drm_psb_private *dev_priv,
-+ struct psb_xhw_buf *buf)
-+{
-+ struct drm_psb_xhw_arg *xa = &buf->arg;
-+ unsigned long irq_flags;
++#define DRM_BE_FLAG_NEEDS_FREE 0x00000001
++#define DRM_BE_FLAG_BOUND_CACHED 0x00000002
+
-+ buf->copy_back = 0;
-+ xa->op = PSB_XHW_TERMINATE;
-+ xa->issue_irq = 0;
++struct drm_ttm_backend;
++struct drm_ttm_backend_func {
++ int (*needs_ub_cache_adjust) (struct drm_ttm_backend *backend);
++ int (*populate) (struct drm_ttm_backend *backend,
++ unsigned long num_pages, struct page **pages);
++ void (*clear) (struct drm_ttm_backend *backend);
++ int (*bind) (struct drm_ttm_backend *backend,
++ struct drm_bo_mem_reg *bo_mem);
++ int (*unbind) (struct drm_ttm_backend *backend);
++ void (*destroy) (struct drm_ttm_backend *backend);
++};
+
-+ spin_lock_irqsave(&dev_priv->xhw_lock, irq_flags);
-+ dev_priv->xhw_submit_ok = 0;
-+ atomic_set(&buf->done, 0);
-+ if (!list_empty(&buf->head)) {
-+ DRM_ERROR("Recursive list adding.\n");
-+ goto out;
-+ }
-+ list_add_tail(&buf->head, &dev_priv->xhw_in);
-+ out:
-+ spin_unlock_irqrestore(&dev_priv->xhw_lock, irq_flags);
-+ wake_up_interruptible(&dev_priv->xhw_queue);
+
-+ (void)wait_event_timeout(dev_priv->xhw_caller_queue,
-+ atomic_read(&buf->done), DRM_HZ / 10);
++struct drm_ttm_backend {
++ struct drm_device *dev;
++ uint32_t flags;
++ struct drm_ttm_backend_func *func;
++};
+
-+ if (!atomic_read(&buf->done)) {
-+ DRM_ERROR("Xpsb terminate timeout.\n");
-+ psb_xhw_clean_buf(dev_priv, buf);
-+ return -EBUSY;
-+ }
++struct drm_ttm {
++ struct page *dummy_read_page;
++ struct page **pages;
++ uint32_t page_flags;
++ unsigned long num_pages;
++ atomic_t vma_count;
++ struct drm_device *dev;
++ int destroy;
++ uint32_t mapping_offset;
++ struct drm_ttm_backend *be;
++ enum {
++ ttm_bound,
++ ttm_evicted,
++ ttm_unbound,
++ ttm_unpopulated,
++ } state;
+
-+ return 0;
-+}
++};
+
-+int psb_xhw_ta_mem_info(struct drm_psb_private *dev_priv,
-+ struct psb_xhw_buf *buf,
-+ uint32_t pages, uint32_t * hw_cookie, uint32_t * size)
-+{
-+ struct drm_psb_xhw_arg *xa = &buf->arg;
-+ int ret;
++extern struct drm_ttm *drm_ttm_init(struct drm_device *dev, unsigned long size);
++extern int drm_bind_ttm(struct drm_ttm *ttm, struct drm_bo_mem_reg *bo_mem);
++extern void drm_ttm_unbind(struct drm_ttm *ttm);
++extern void drm_ttm_evict(struct drm_ttm *ttm);
++extern void drm_ttm_fixup_caching(struct drm_ttm *ttm);
++extern struct page *drm_ttm_get_page(struct drm_ttm *ttm, int index);
++extern void drm_ttm_cache_flush(void);
++extern int drm_ttm_populate(struct drm_ttm *ttm);
++extern int drm_ttm_set_user(struct drm_ttm *ttm,
++ struct task_struct *tsk,
++ int write,
++ unsigned long start,
++ unsigned long num_pages,
++ struct page *dummy_read_page);
++unsigned long drm_ttm_size(struct drm_device *dev,
++ unsigned long num_pages,
++ int user_bo);
+
-+ buf->copy_back = 1;
-+ xa->op = PSB_XHW_TA_MEM_INFO;
-+ xa->issue_irq = 0;
-+ xa->irq_op = 0;
-+ xa->arg.bi.pages = pages;
+
-+ ret = psb_xhw_add(dev_priv, buf);
-+ if (ret)
-+ return ret;
++/*
++ * Destroy a ttm. The user normally calls drmRmMap or a similar IOCTL to do
++ * this which calls this function iff there are no vmas referencing it anymore.
++ * Otherwise it is called when the last vma exits.
++ */
+
-+ (void)wait_event_timeout(dev_priv->xhw_caller_queue,
-+ atomic_read(&buf->done), DRM_HZ);
++extern int drm_destroy_ttm(struct drm_ttm *ttm);
+
-+ if (!atomic_read(&buf->done)) {
-+ psb_xhw_clean_buf(dev_priv, buf);
-+ return -EBUSY;
-+ }
++#define DRM_FLAG_MASKED(_old, _new, _mask) {\
++(_old) ^= (((_old) ^ (_new)) & (_mask)); \
++}
+
-+ if (!xa->ret)
-+ memcpy(hw_cookie, xa->cookie, sizeof(xa->cookie));
++#define DRM_TTM_MASK_FLAGS ((1 << PAGE_SHIFT) - 1)
++#define DRM_TTM_MASK_PFN (0xFFFFFFFFU - DRM_TTM_MASK_FLAGS)
+
-+ *size = xa->arg.bi.size;
-+ return xa->ret;
-+}
-+
-+int psb_xhw_ta_mem_load(struct drm_psb_private *dev_priv,
-+ struct psb_xhw_buf *buf,
-+ uint32_t flags,
-+ uint32_t param_offset,
-+ uint32_t pt_offset, uint32_t * hw_cookie)
-+{
-+ struct drm_psb_xhw_arg *xa = &buf->arg;
-+ int ret;
-+
-+ buf->copy_back = 1;
-+ xa->op = PSB_XHW_TA_MEM_LOAD;
-+ xa->issue_irq = 0;
-+ xa->irq_op = 0;
-+ xa->arg.bl.flags = flags;
-+ xa->arg.bl.param_offset = param_offset;
-+ xa->arg.bl.pt_offset = pt_offset;
-+ memcpy(xa->cookie, hw_cookie, sizeof(xa->cookie));
-+
-+ ret = psb_xhw_add(dev_priv, buf);
-+ if (ret)
-+ return ret;
++/*
++ * Page flags.
++ */
+
-+ (void)wait_event_timeout(dev_priv->xhw_caller_queue,
-+ atomic_read(&buf->done), 3 * DRM_HZ);
++#define DRM_TTM_PAGE_UNCACHED (1 << 0)
++#define DRM_TTM_PAGE_USED (1 << 1)
++#define DRM_TTM_PAGE_BOUND (1 << 2)
++#define DRM_TTM_PAGE_PRESENT (1 << 3)
++#define DRM_TTM_PAGE_VMALLOC (1 << 4)
++#define DRM_TTM_PAGE_USER (1 << 5)
++#define DRM_TTM_PAGE_USER_WRITE (1 << 6)
++#define DRM_TTM_PAGE_USER_DIRTY (1 << 7)
++#define DRM_TTM_PAGE_USER_DMA (1 << 8)
+
-+ if (!atomic_read(&buf->done)) {
-+ psb_xhw_clean_buf(dev_priv, buf);
-+ return -EBUSY;
-+ }
++/***************************************************
++ * Buffer objects. (drm_bo.c, drm_bo_move.c)
++ */
+
-+ if (!xa->ret)
-+ memcpy(hw_cookie, xa->cookie, sizeof(xa->cookie));
++struct drm_bo_mem_reg {
++ struct drm_mm_node *mm_node;
++ unsigned long size;
++ unsigned long num_pages;
++ uint32_t page_alignment;
++ uint32_t mem_type;
++ uint64_t flags;
++ uint64_t mask;
++ uint32_t desired_tile_stride;
++ uint32_t hw_tile_stride;
++};
+
-+ return xa->ret;
-+}
++enum drm_bo_type {
++ drm_bo_type_dc,
++ drm_bo_type_user,
++ drm_bo_type_kernel, /* for initial kernel allocations */
++};
+
-+int psb_xhw_ta_oom(struct drm_psb_private *dev_priv,
-+ struct psb_xhw_buf *buf, uint32_t * cookie)
-+{
-+ struct drm_psb_xhw_arg *xa = &buf->arg;
++struct drm_buffer_object {
++ struct drm_device *dev;
++ struct drm_user_object base;
+
+ /*
-+ * This calls the extensive closed source
-+ * OOM handler, which resolves the condition and
-+ * sends a reply telling the scheduler what to do
-+ * with the task.
++ * If there is a possibility that the usage variable is zero,
++ * then dev->struct_mutext should be locked before incrementing it.
+ */
+
-+ buf->copy_back = 1;
-+ xa->op = PSB_XHW_OOM;
-+ xa->issue_irq = 1;
-+ xa->irq_op = PSB_UIRQ_OOM_REPLY;
-+ memcpy(xa->cookie, cookie, sizeof(xa->cookie));
-+
-+ return psb_xhw_add(dev_priv, buf);
-+}
-+
-+void psb_xhw_ta_oom_reply(struct drm_psb_private *dev_priv,
-+ struct psb_xhw_buf *buf,
-+ uint32_t * cookie,
-+ uint32_t * bca, uint32_t * rca, uint32_t * flags)
-+{
-+ struct drm_psb_xhw_arg *xa = &buf->arg;
++ atomic_t usage;
++ unsigned long buffer_start;
++ enum drm_bo_type type;
++ unsigned long offset;
++ atomic_t mapped;
++ struct drm_bo_mem_reg mem;
+
-+ /*
-+ * Get info about how to schedule an OOM task.
-+ */
++ struct list_head lru;
++ struct list_head ddestroy;
+
-+ memcpy(cookie, xa->cookie, sizeof(xa->cookie));
-+ *bca = xa->arg.oom.bca;
-+ *rca = xa->arg.oom.rca;
-+ *flags = xa->arg.oom.flags;
-+}
++ uint32_t fence_type;
++ uint32_t fence_class;
++ uint32_t new_fence_type;
++ uint32_t new_fence_class;
++ struct drm_fence_object *fence;
++ uint32_t priv_flags;
++ wait_queue_head_t event_queue;
++ struct mutex mutex;
++ unsigned long num_pages;
++ unsigned long reserved_size;
+
-+void psb_xhw_fire_reply(struct drm_psb_private *dev_priv,
-+ struct psb_xhw_buf *buf, uint32_t * cookie)
-+{
-+ struct drm_psb_xhw_arg *xa = &buf->arg;
++ /* For pinned buffers */
++ struct drm_mm_node *pinned_node;
++ uint32_t pinned_mem_type;
++ struct list_head pinned_lru;
+
-+ memcpy(cookie, xa->cookie, sizeof(xa->cookie));
-+}
++ /* For vm */
++ struct drm_ttm *ttm;
++ struct drm_map_list map_list;
++ uint32_t memory_type;
++ unsigned long bus_offset;
++ uint32_t vm_flags;
++ void *iomap;
+
-+int psb_xhw_resume(struct drm_psb_private *dev_priv, struct psb_xhw_buf *buf)
-+{
-+ struct drm_psb_xhw_arg *xa = &buf->arg;
++#ifdef DRM_ODD_MM_COMPAT
++ /* dev->struct_mutex only protected. */
++ struct list_head vma_list;
++ struct list_head p_mm_list;
++#endif
+
-+ buf->copy_back = 0;
-+ xa->op = PSB_XHW_RESUME;
-+ xa->issue_irq = 0;
-+ xa->irq_op = 0;
-+ return psb_xhw_add(dev_priv, buf);
-+}
++};
+
-+void psb_xhw_takedown(struct drm_psb_private *dev_priv)
-+{
-+}
++#define _DRM_BO_FLAG_UNFENCED 0x00000001
++#define _DRM_BO_FLAG_EVICTED 0x00000002
+
-+int psb_xhw_init(struct drm_device *dev)
-+{
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
-+ unsigned long irq_flags;
++struct drm_mem_type_manager {
++ int has_type;
++ int use_type;
++ struct drm_mm manager;
++ struct list_head lru;
++ struct list_head pinned;
++ uint32_t flags;
++ uint32_t drm_bus_maptype;
++ unsigned long gpu_offset;
++ unsigned long io_offset;
++ unsigned long io_size;
++ void *io_addr;
++};
+
-+ INIT_LIST_HEAD(&dev_priv->xhw_in);
-+ dev_priv->xhw_lock = SPIN_LOCK_UNLOCKED;
-+ atomic_set(&dev_priv->xhw_client, 0);
-+ init_waitqueue_head(&dev_priv->xhw_queue);
-+ init_waitqueue_head(&dev_priv->xhw_caller_queue);
-+ mutex_init(&dev_priv->xhw_mutex);
-+ spin_lock_irqsave(&dev_priv->xhw_lock, irq_flags);
-+ dev_priv->xhw_on = 0;
-+ spin_unlock_irqrestore(&dev_priv->xhw_lock, irq_flags);
++struct drm_bo_lock {
++ struct drm_user_object base;
++ wait_queue_head_t queue;
++ atomic_t write_lock_pending;
++ atomic_t readers;
++};
+
-+ return 0;
-+}
++#define _DRM_FLAG_MEMTYPE_FIXED 0x00000001 /* Fixed (on-card) PCI memory */
++#define _DRM_FLAG_MEMTYPE_MAPPABLE 0x00000002 /* Memory mappable */
++#define _DRM_FLAG_MEMTYPE_CACHED 0x00000004 /* Cached binding */
++#define _DRM_FLAG_NEEDS_IOREMAP 0x00000008 /* Fixed memory needs ioremap
++ before kernel access. */
++#define _DRM_FLAG_MEMTYPE_CMA 0x00000010 /* Can't map aperture */
++#define _DRM_FLAG_MEMTYPE_CSELECT 0x00000020 /* Select caching */
+
-+static int psb_xhw_init_init(struct drm_device *dev,
-+ struct drm_file *file_priv,
-+ struct drm_psb_xhw_init_arg *arg)
-+{
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
-+ int ret;
-+ int is_iomem;
++struct drm_buffer_manager {
++ struct drm_bo_lock bm_lock;
++ struct mutex evict_mutex;
++ int nice_mode;
++ int initialized;
++ struct drm_file *last_to_validate;
++ struct drm_mem_type_manager man[DRM_BO_MEM_TYPES];
++ struct list_head unfenced;
++ struct list_head ddestroy;
++ struct delayed_work wq;
++ uint32_t fence_type;
++ unsigned long cur_pages;
++ atomic_t count;
++ struct page *dummy_read_page;
++};
+
-+ if (atomic_add_unless(&dev_priv->xhw_client, 1, 1)) {
-+ unsigned long irq_flags;
++struct drm_bo_driver {
++ const uint32_t *mem_type_prio;
++ const uint32_t *mem_busy_prio;
++ uint32_t num_mem_type_prio;
++ uint32_t num_mem_busy_prio;
++ struct drm_ttm_backend *(*create_ttm_backend_entry)
++ (struct drm_device *dev);
++ int (*backend_size) (struct drm_device *dev,
++ unsigned long num_pages);
++ int (*fence_type) (struct drm_buffer_object *bo, uint32_t *fclass,
++ uint32_t *type);
++ int (*invalidate_caches) (struct drm_device *dev, uint64_t flags);
++ int (*init_mem_type) (struct drm_device *dev, uint32_t type,
++ struct drm_mem_type_manager *man);
++ uint32_t(*evict_mask) (struct drm_buffer_object *bo);
++ int (*move) (struct drm_buffer_object *bo,
++ int evict, int no_wait, struct drm_bo_mem_reg *new_mem);
++ void (*ttm_cache_flush)(struct drm_ttm *ttm);
+
-+ mutex_lock(&dev->struct_mutex);
-+ dev_priv->xhw_bo =
-+ drm_lookup_buffer_object(file_priv, arg->buffer_handle, 1);
-+ mutex_unlock(&dev->struct_mutex);
-+ if (!dev_priv->xhw_bo) {
-+ ret = -EINVAL;
-+ goto out_err;
-+ }
-+ ret = drm_bo_kmap(dev_priv->xhw_bo, 0,
-+ dev_priv->xhw_bo->num_pages,
-+ &dev_priv->xhw_kmap);
-+ if (ret) {
-+ DRM_ERROR("Failed mapping X server "
-+ "communications buffer.\n");
-+ goto out_err0;
-+ }
-+ dev_priv->xhw = drm_bmo_virtual(&dev_priv->xhw_kmap, &is_iomem);
-+ if (is_iomem) {
-+ DRM_ERROR("X server communications buffer"
-+ "is in device memory.\n");
-+ ret = -EINVAL;
-+ goto out_err1;
-+ }
-+ dev_priv->xhw_file = file_priv;
-+
-+ spin_lock_irqsave(&dev_priv->xhw_lock, irq_flags);
-+ dev_priv->xhw_on = 1;
-+ dev_priv->xhw_submit_ok = 1;
-+ spin_unlock_irqrestore(&dev_priv->xhw_lock, irq_flags);
-+ return 0;
-+ } else {
-+ DRM_ERROR("Xhw is already initialized.\n");
-+ return -EBUSY;
-+ }
-+ out_err1:
-+ dev_priv->xhw = NULL;
-+ drm_bo_kunmap(&dev_priv->xhw_kmap);
-+ out_err0:
-+ drm_bo_usage_deref_unlocked(&dev_priv->xhw_bo);
-+ out_err:
-+ atomic_dec(&dev_priv->xhw_client);
-+ return ret;
-+}
-+
-+static void psb_xhw_queue_empty(struct drm_psb_private *dev_priv)
-+{
-+ struct psb_xhw_buf *cur_buf, *next;
-+ unsigned long irq_flags;
-+
-+ spin_lock_irqsave(&dev_priv->xhw_lock, irq_flags);
-+ dev_priv->xhw_submit_ok = 0;
++ /*
++ * command_stream_barrier
++ *
++ * @dev: The drm device.
++ *
++ * @bo: The buffer object to validate.
++ *
++ * @new_fence_class: The new fence class for the buffer object.
++ *
++ * @new_fence_type: The new fence type for the buffer object.
++ *
++ * @no_wait: whether this should give up and return -EBUSY
++ * if this operation would require sleeping
++ *
++ * Insert a command stream barrier that makes sure that the
++ * buffer is idle once the commands associated with the
++ * current validation are starting to execute. If an error
++ * condition is returned, or the function pointer is NULL,
++ * the drm core will force buffer idle
++ * during validation.
++ */
+
-+ list_for_each_entry_safe(cur_buf, next, &dev_priv->xhw_in, head) {
-+ list_del_init(&cur_buf->head);
-+ if (cur_buf->copy_back) {
-+ cur_buf->arg.ret = -EINVAL;
-+ }
-+ atomic_set(&cur_buf->done, 1);
-+ }
-+ spin_unlock_irqrestore(&dev_priv->xhw_lock, irq_flags);
-+ wake_up(&dev_priv->xhw_caller_queue);
-+}
++ int (*command_stream_barrier) (struct drm_buffer_object *bo,
++ uint32_t new_fence_class,
++ uint32_t new_fence_type,
++ int no_wait);
++};
+
-+void psb_xhw_init_takedown(struct drm_psb_private *dev_priv,
-+ struct drm_file *file_priv, int closing)
-+{
++/*
++ * buffer objects (drm_bo.c)
++ */
++extern int drm_bo_create_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
++extern int drm_bo_destroy_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
++extern int drm_bo_map_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
++extern int drm_bo_unmap_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
++extern int drm_bo_reference_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
++extern int drm_bo_set_pin(struct drm_device *dev, struct drm_buffer_object *bo, int pin);
++extern int drm_bo_unreference_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
++extern int drm_bo_wait_idle_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
++extern int drm_bo_info_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
++extern int drm_bo_setstatus_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
++extern int drm_mm_init_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
++extern int drm_mm_takedown_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
++extern int drm_mm_lock_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
++extern int drm_mm_unlock_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
++extern int drm_bo_version_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
++extern int drm_bo_driver_finish(struct drm_device *dev);
++extern int drm_bo_driver_init(struct drm_device *dev);
++extern int drm_bo_pci_offset(struct drm_device *dev,
++ struct drm_bo_mem_reg *mem,
++ unsigned long *bus_base,
++ unsigned long *bus_offset,
++ unsigned long *bus_size);
++extern int drm_mem_reg_is_pci(struct drm_device *dev, struct drm_bo_mem_reg *mem);
+
-+ if (dev_priv->xhw_file == file_priv &&
-+ atomic_add_unless(&dev_priv->xhw_client, -1, 0)) {
++extern void drm_bo_usage_deref_locked(struct drm_buffer_object **bo);
++extern void drm_bo_usage_deref_unlocked(struct drm_buffer_object **bo);
++extern void drm_putback_buffer_objects(struct drm_device *dev);
++extern int drm_fence_buffer_objects(struct drm_device *dev,
++ struct list_head *list,
++ uint32_t fence_flags,
++ struct drm_fence_object *fence,
++ struct drm_fence_object **used_fence);
++extern void drm_bo_add_to_lru(struct drm_buffer_object *bo);
++extern int drm_buffer_object_create(struct drm_device *dev, unsigned long size,
++ enum drm_bo_type type, uint64_t mask,
++ uint32_t hint, uint32_t page_alignment,
++ unsigned long buffer_start,
++ struct drm_buffer_object **bo);
++extern int drm_bo_wait(struct drm_buffer_object *bo, int lazy, int ignore_signals,
++ int no_wait);
++extern int drm_bo_mem_space(struct drm_buffer_object *bo,
++ struct drm_bo_mem_reg *mem, int no_wait);
++extern int drm_bo_move_buffer(struct drm_buffer_object *bo,
++ uint64_t new_mem_flags,
++ int no_wait, int move_unfenced);
++extern int drm_bo_clean_mm(struct drm_device *dev, unsigned mem_type);
++extern int drm_bo_init_mm(struct drm_device *dev, unsigned type,
++ unsigned long p_offset, unsigned long p_size);
++extern int drm_bo_handle_validate(struct drm_file *file_priv, uint32_t handle,
++ uint32_t fence_class, uint64_t flags,
++ uint64_t mask, uint32_t hint,
++ int use_old_fence_class,
++ struct drm_bo_info_rep *rep,
++ struct drm_buffer_object **bo_rep);
++extern struct drm_buffer_object *drm_lookup_buffer_object(struct drm_file *file_priv,
++ uint32_t handle,
++ int check_owner);
++extern int drm_bo_do_validate(struct drm_buffer_object *bo,
++ uint64_t flags, uint64_t mask, uint32_t hint,
++ uint32_t fence_class,
++ int no_wait,
++ struct drm_bo_info_rep *rep);
++extern void drm_bo_fill_rep_arg(struct drm_buffer_object *bo,
++ struct drm_bo_info_rep *rep);
++/*
++ * Buffer object memory move- and map helpers.
++ * drm_bo_move.c
++ */
+
-+ if (closing)
-+ psb_xhw_queue_empty(dev_priv);
-+ else {
-+ struct psb_xhw_buf buf;
-+ INIT_LIST_HEAD(&buf.head);
++extern int drm_bo_move_ttm(struct drm_buffer_object *bo,
++ int evict, int no_wait,
++ struct drm_bo_mem_reg *new_mem);
++extern int drm_bo_move_memcpy(struct drm_buffer_object *bo,
++ int evict,
++ int no_wait, struct drm_bo_mem_reg *new_mem);
++extern int drm_bo_move_accel_cleanup(struct drm_buffer_object *bo,
++ int evict, int no_wait,
++ uint32_t fence_class, uint32_t fence_type,
++ uint32_t fence_flags,
++ struct drm_bo_mem_reg *new_mem);
++extern int drm_bo_same_page(unsigned long offset, unsigned long offset2);
++extern unsigned long drm_bo_offset_end(unsigned long offset,
++ unsigned long end);
+
-+ psb_xhw_terminate(dev_priv, &buf);
-+ psb_xhw_queue_empty(dev_priv);
-+ }
++struct drm_bo_kmap_obj {
++ void *virtual;
++ struct page *page;
++ enum {
++ bo_map_iomap,
++ bo_map_vmap,
++ bo_map_kmap,
++ bo_map_premapped,
++ } bo_kmap_type;
++};
+
-+ dev_priv->xhw = NULL;
-+ drm_bo_kunmap(&dev_priv->xhw_kmap);
-+ drm_bo_usage_deref_unlocked(&dev_priv->xhw_bo);
-+ dev_priv->xhw_file = NULL;
-+ }
++static inline void *drm_bmo_virtual(struct drm_bo_kmap_obj *map, int *is_iomem)
++{
++ *is_iomem = (map->bo_kmap_type == bo_map_iomap ||
++ map->bo_kmap_type == bo_map_premapped);
++ return map->virtual;
+}
++extern void drm_bo_kunmap(struct drm_bo_kmap_obj *map);
++extern int drm_bo_kmap(struct drm_buffer_object *bo, unsigned long start_page,
++ unsigned long num_pages, struct drm_bo_kmap_obj *map);
+
-+int psb_xhw_init_ioctl(struct drm_device *dev, void *data,
-+ struct drm_file *file_priv)
-+{
-+ struct drm_psb_xhw_init_arg *arg = (struct drm_psb_xhw_init_arg *)data;
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
+
-+ switch (arg->operation) {
-+ case PSB_XHW_INIT:
-+ return psb_xhw_init_init(dev, file_priv, arg);
-+ case PSB_XHW_TAKEDOWN:
-+ psb_xhw_init_takedown(dev_priv, file_priv, 0);
-+ }
-+ return 0;
-+}
++/*
++ * drm_regman.c
++ */
+
-+static int psb_xhw_in_empty(struct drm_psb_private *dev_priv)
-+{
-+ int empty;
-+ unsigned long irq_flags;
++struct drm_reg {
++ struct list_head head;
++ struct drm_fence_object *fence;
++ uint32_t fence_type;
++ uint32_t new_fence_type;
++};
+
-+ spin_lock_irqsave(&dev_priv->xhw_lock, irq_flags);
-+ empty = list_empty(&dev_priv->xhw_in);
-+ spin_unlock_irqrestore(&dev_priv->xhw_lock, irq_flags);
-+ return empty;
-+}
++struct drm_reg_manager {
++ struct list_head free;
++ struct list_head lru;
++ struct list_head unfenced;
+
-+int psb_xhw_handler(struct drm_psb_private *dev_priv)
-+{
-+ unsigned long irq_flags;
-+ struct drm_psb_xhw_arg *xa;
-+ struct psb_xhw_buf *buf;
++ int (*reg_reusable)(const struct drm_reg *reg, const void *data);
++ void (*reg_destroy)(struct drm_reg *reg);
++};
+
-+ spin_lock_irqsave(&dev_priv->xhw_lock, irq_flags);
++extern int drm_regs_alloc(struct drm_reg_manager *manager,
++ const void *data,
++ uint32_t fence_class,
++ uint32_t fence_type,
++ int interruptible,
++ int no_wait,
++ struct drm_reg **reg);
+
-+ if (!dev_priv->xhw_on) {
-+ spin_unlock_irqrestore(&dev_priv->xhw_lock, irq_flags);
-+ return -EINVAL;
-+ }
++extern void drm_regs_fence(struct drm_reg_manager *regs,
++ struct drm_fence_object *fence);
+
-+ buf = dev_priv->xhw_cur_buf;
-+ if (buf && buf->copy_back) {
-+ xa = &buf->arg;
-+ memcpy(xa, dev_priv->xhw, sizeof(*xa));
-+ dev_priv->comm[PSB_COMM_USER_IRQ] = xa->irq_op;
-+ atomic_set(&buf->done, 1);
-+ wake_up(&dev_priv->xhw_caller_queue);
-+ } else
-+ dev_priv->comm[PSB_COMM_USER_IRQ] = 0;
++extern void drm_regs_free(struct drm_reg_manager *manager);
++extern void drm_regs_add(struct drm_reg_manager *manager, struct drm_reg *reg);
++extern void drm_regs_init(struct drm_reg_manager *manager,
++ int (*reg_reusable)(const struct drm_reg *,
++ const void *),
++ void (*reg_destroy)(struct drm_reg *));
+
-+ dev_priv->xhw_cur_buf = 0;
-+ spin_unlock_irqrestore(&dev_priv->xhw_lock, irq_flags);
-+ return 0;
-+}
++extern int drm_mem_reg_ioremap(struct drm_device *dev, struct drm_bo_mem_reg * mem,
++ void **virtual);
++extern void drm_mem_reg_iounmap(struct drm_device *dev, struct drm_bo_mem_reg * mem,
++ void *virtual);
++/*
++ * drm_bo_lock.c
++ * Simple replacement for the hardware lock on buffer manager init and clean.
++ */
+
-+int psb_xhw_ioctl(struct drm_device *dev, void *data,
-+ struct drm_file *file_priv)
++
++extern void drm_bo_init_lock(struct drm_bo_lock *lock);
++extern void drm_bo_read_unlock(struct drm_bo_lock *lock);
++extern int drm_bo_read_lock(struct drm_bo_lock *lock);
++extern int drm_bo_write_lock(struct drm_bo_lock *lock,
++ struct drm_file *file_priv);
++
++extern int drm_bo_write_unlock(struct drm_bo_lock *lock,
++ struct drm_file *file_priv);
++
++#ifdef CONFIG_DEBUG_MUTEXES
++#define DRM_ASSERT_LOCKED(_mutex) \
++ BUG_ON(!mutex_is_locked(_mutex) || \
++ ((_mutex)->owner != current_thread_info()))
++#else
++#define DRM_ASSERT_LOCKED(_mutex)
++#endif
++#endif
+Index: linux-2.6.28/drivers/gpu/drm/drm_proc.c
+===================================================================
+--- linux-2.6.28.orig/drivers/gpu/drm/drm_proc.c 2009-02-12 09:14:37.000000000 +0000
++++ linux-2.6.28/drivers/gpu/drm/drm_proc.c 2009-02-12 09:14:42.000000000 +0000
+@@ -489,13 +489,13 @@
+
+ for (crtc = 0; crtc < dev->num_crtcs; crtc++) {
+ DRM_PROC_PRINT("CRTC %d enable: %d\n",
+- crtc, atomic_read(&dev->vblank_refcount[crtc]));
++ crtc, 1);
+ DRM_PROC_PRINT("CRTC %d counter: %d\n",
+- crtc, drm_vblank_count(dev, crtc));
++ crtc, 1);
+ DRM_PROC_PRINT("CRTC %d last wait: %d\n",
+- crtc, dev->last_vblank_wait[crtc]);
++ crtc, 1);
+ DRM_PROC_PRINT("CRTC %d in modeset: %d\n",
+- crtc, dev->vblank_inmodeset[crtc]);
++ crtc, 1);
+ }
+
+ if (len > request + offset)
+Index: linux-2.6.28/drivers/gpu/drm/drm_crtc.c
+===================================================================
+--- linux-2.6.28.orig/drivers/gpu/drm/drm_crtc.c 2009-02-12 09:14:37.000000000 +0000
++++ linux-2.6.28/drivers/gpu/drm/drm_crtc.c 2009-02-12 09:14:42.000000000 +0000
+@@ -807,6 +807,53 @@
+ }
+ EXPORT_SYMBOL(drm_mode_config_init);
+
++/**
++ * drm_get_buffer_object - find the buffer object for a given handle
++ * @dev: DRM device
++ * @bo: pointer to caller's buffer_object pointer
++ * @handle: handle to lookup
++ *
++ * LOCKING:
++ * Must take @dev's struct_mutex to protect buffer object lookup.
++ *
++ * Given @handle, lookup the buffer object in @dev and put it in the caller's
++ * @bo pointer.
++ *
++ * RETURNS:
++ * Zero on success, -EINVAL if the handle couldn't be found.
++ */
++static int drm_get_buffer_object(struct drm_device *dev, struct drm_buffer_object **bo, unsigned long handle)
+{
-+ struct drm_psb_private *dev_priv =
-+ (struct drm_psb_private *)dev->dev_private;
-+ unsigned long irq_flags;
-+ struct drm_psb_xhw_arg *xa;
++ struct drm_user_object *uo;
++ struct drm_hash_item *hash;
+ int ret;
-+ struct list_head *list;
-+ struct psb_xhw_buf *buf;
+
-+ if (!dev_priv)
-+ return -EINVAL;
-+
-+ if (mutex_lock_interruptible(&dev_priv->xhw_mutex))
-+ return -EAGAIN;
++ *bo = NULL;
+
-+ if (psb_forced_user_interrupt(dev_priv)) {
-+ mutex_unlock(&dev_priv->xhw_mutex);
-+ return -EINVAL;
++ mutex_lock(&dev->struct_mutex);
++ ret = drm_ht_find_item(&dev->object_hash, handle, &hash);
++ if (ret) {
++ DRM_ERROR("Couldn't find handle.\n");
++ ret = -EINVAL;
++ goto out_err;
+ }
+
-+ spin_lock_irqsave(&dev_priv->xhw_lock, irq_flags);
-+ while (list_empty(&dev_priv->xhw_in)) {
-+ spin_unlock_irqrestore(&dev_priv->xhw_lock, irq_flags);
-+ ret = wait_event_interruptible_timeout(dev_priv->xhw_queue,
-+ !psb_xhw_in_empty
-+ (dev_priv), DRM_HZ);
-+ if (ret == -ERESTARTSYS || ret == 0) {
-+ mutex_unlock(&dev_priv->xhw_mutex);
-+ return -EAGAIN;
-+ }
-+ spin_lock_irqsave(&dev_priv->xhw_lock, irq_flags);
++ uo = drm_hash_entry(hash, struct drm_user_object, hash);
++ if (uo->type != drm_buffer_type) {
++ ret = -EINVAL;
++ goto out_err;
+ }
+
-+ list = dev_priv->xhw_in.next;
-+ list_del_init(list);
++ *bo = drm_user_object_entry(uo, struct drm_buffer_object, base);
++ ret = 0;
++out_err:
++ mutex_unlock(&dev->struct_mutex);
++ return ret;
++}
+
-+ buf = list_entry(list, struct psb_xhw_buf, head);
-+ xa = &buf->arg;
-+ memcpy(dev_priv->xhw, xa, sizeof(*xa));
++char drm_init_mode[32];
++EXPORT_SYMBOL(drm_init_mode);
+
-+ if (unlikely(buf->copy_back))
-+ dev_priv->xhw_cur_buf = buf;
-+ else {
-+ atomic_set(&buf->done, 1);
-+ dev_priv->xhw_cur_buf = NULL;
+ int drm_mode_group_init(struct drm_device *dev, struct drm_mode_group *group)
+ {
+ uint32_t total_objects = 0;
+@@ -1588,6 +1635,8 @@
+ struct drm_mode_fb_cmd *r = data;
+ struct drm_mode_config *config = &dev->mode_config;
+ struct drm_framebuffer *fb;
++ struct drm_buffer_object *bo;
++ struct drm_crtc *crtc;
+ int ret = 0;
+
+ if ((config->min_width > r->width) || (r->width > config->max_width)) {
+@@ -1600,20 +1649,46 @@
+ }
+
+ mutex_lock(&dev->mode_config.mutex);
++ /* TODO check limits are okay */
++ ret = drm_get_buffer_object(dev, &bo, r->handle);
++ if (ret || !bo) {
++ ret = -EINVAL;
++ goto out;
+ }
-+
-+ if (xa->op == PSB_XHW_TERMINATE) {
-+ dev_priv->xhw_on = 0;
-+ wake_up(&dev_priv->xhw_caller_queue);
+
+ /* TODO check buffer is sufficently large */
+ /* TODO setup destructor callback */
+
+- fb = dev->mode_config.funcs->fb_create(dev, file_priv, r);
++ fb = kzalloc(sizeof(struct drm_framebuffer), GFP_KERNEL);
++ if (!fb) {
++ ret = -ENOMEM;
++ goto out;
+ }
-+ spin_unlock_irqrestore(&dev_priv->xhw_lock, irq_flags);
+
-+ mutex_unlock(&dev_priv->xhw_mutex);
++ drm_framebuffer_init(dev, fb, NULL);
+ if (!fb) {
+ DRM_ERROR("could not create framebuffer\n");
+ ret = -EINVAL;
+ goto out;
+ }
+
++ fb->width = r->width;
++ fb->height = r->height;
++ fb->pitch = r->pitch;
++ fb->bits_per_pixel = r->bpp;
++ fb->depth = r->depth;
++ fb->offset = bo->offset;
++ fb->bo = bo;
+
-+ return 0;
-+}
-Index: linux-2.6.28/drivers/gpu/drm/Kconfig
-===================================================================
---- linux-2.6.28.orig/drivers/gpu/drm/Kconfig 2009-02-12 09:14:37.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/Kconfig 2009-02-12 09:14:42.000000000 +0000
-@@ -123,3 +123,9 @@
- help
- Choose this option if you have a Savage3D/4/SuperSavage/Pro/Twister
- chipset. If M is selected the module will be called savage.
+ r->fb_id = fb->base.id;
+ list_add(&fb->filp_head, &file_priv->fbs);
+
++ /* FIXME: bind the fb to the right crtc */
++ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
++ crtc->fb = fb;
++ dev->driver->fb_probe(dev, crtc);
++ }
+
-+config DRM_PSB
-+ tristate "Intel Poulsbo"
-+ depends on DRM && PCI && I2C_ALGOBIT
-+ help
-+ Choose this option if you have an Intel Poulsbo chipset.
-Index: linux-2.6.28/include/drm/drm_objects.h
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.28/include/drm/drm_objects.h 2009-02-12 09:14:42.000000000 +0000
-@@ -0,0 +1,717 @@
-+/**************************************************************************
-+ *
-+ * Copyright (c) 2006-2007 Tungsten Graphics, Inc., Cedar Park, TX., USA
-+ * All Rights Reserved.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the
-+ * "Software"), to deal in the Software without restriction, including
-+ * without limitation the rights to use, copy, modify, merge, publish,
-+ * distribute, sub license, and/or sell copies of the Software, and to
-+ * permit persons to whom the Software is furnished to do so, subject to
-+ * the following conditions:
-+ *
-+ * The above copyright notice and this permission notice (including the
-+ * next paragraph) shall be included in all copies or substantial portions
-+ * of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
-+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ **************************************************************************/
-+/*
-+ * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
-+ */
-+
-+#ifndef _DRM_OBJECTS_H
-+#define _DRM_OBJECTS_H
-+
-+struct drm_device;
-+struct drm_bo_mem_reg;
-+
-+/***************************************************
-+ * User space objects. (drm_object.c)
-+ */
-+
-+#define drm_user_object_entry(_ptr, _type, _member) container_of(_ptr, _type, _member)
-+
-+enum drm_object_type {
-+ drm_fence_type,
-+ drm_buffer_type,
-+ drm_lock_type,
-+ /*
-+ * Add other user space object types here.
-+ */
-+ drm_driver_type0 = 256,
-+ drm_driver_type1,
-+ drm_driver_type2,
-+ drm_driver_type3,
-+ drm_driver_type4
-+};
-+
-+/*
-+ * A user object is a structure that helps the drm give out user handles
-+ * to kernel internal objects and to keep track of these objects so that
-+ * they can be destroyed, for example when the user space process exits.
-+ * Designed to be accessible using a user space 32-bit handle.
-+ */
-+
-+struct drm_user_object {
-+ struct drm_hash_item hash;
-+ struct list_head list;
-+ enum drm_object_type type;
-+ atomic_t refcount;
-+ int shareable;
-+ struct drm_file *owner;
-+ void (*ref_struct_locked) (struct drm_file *priv,
-+ struct drm_user_object *obj,
-+ enum drm_ref_type ref_action);
-+ void (*unref) (struct drm_file *priv, struct drm_user_object *obj,
-+ enum drm_ref_type unref_action);
-+ void (*remove) (struct drm_file *priv, struct drm_user_object *obj);
-+};
-+
-+/*
-+ * A ref object is a structure which is used to
-+ * keep track of references to user objects and to keep track of these
-+ * references so that they can be destroyed for example when the user space
-+ * process exits. Designed to be accessible using a pointer to the _user_ object.
-+ */
-+
-+struct drm_ref_object {
-+ struct drm_hash_item hash;
-+ struct list_head list;
-+ atomic_t refcount;
-+ enum drm_ref_type unref_action;
-+};
-+
-+/**
-+ * Must be called with the struct_mutex held.
-+ */
-+
-+extern int drm_add_user_object(struct drm_file *priv, struct drm_user_object *item,
-+ int shareable);
-+/**
-+ * Must be called with the struct_mutex held.
-+ */
-+
-+extern struct drm_user_object *drm_lookup_user_object(struct drm_file *priv,
-+ uint32_t key);
-+
-+/*
-+ * Must be called with the struct_mutex held. May temporarily release it.
-+ */
-+
-+extern int drm_add_ref_object(struct drm_file *priv,
-+ struct drm_user_object *referenced_object,
-+ enum drm_ref_type ref_action);
-+
-+/*
-+ * Must be called with the struct_mutex held.
-+ */
-+
-+struct drm_ref_object *drm_lookup_ref_object(struct drm_file *priv,
-+ struct drm_user_object *referenced_object,
-+ enum drm_ref_type ref_action);
-+/*
-+ * Must be called with the struct_mutex held.
-+ * If "item" has been obtained by a call to drm_lookup_ref_object. You may not
-+ * release the struct_mutex before calling drm_remove_ref_object.
-+ * This function may temporarily release the struct_mutex.
-+ */
-+
-+extern void drm_remove_ref_object(struct drm_file *priv, struct drm_ref_object *item);
-+extern int drm_user_object_ref(struct drm_file *priv, uint32_t user_token,
-+ enum drm_object_type type,
-+ struct drm_user_object **object);
-+extern int drm_user_object_unref(struct drm_file *priv, uint32_t user_token,
-+ enum drm_object_type type);
-+
-+/***************************************************
-+ * Fence objects. (drm_fence.c)
-+ */
-+
-+struct drm_fence_object {
-+ struct drm_user_object base;
-+ struct drm_device *dev;
-+ atomic_t usage;
-+
-+ /*
-+ * The below three fields are protected by the fence manager spinlock.
-+ */
-+
-+ struct list_head ring;
-+ int fence_class;
-+ uint32_t native_types;
-+ uint32_t type;
-+ uint32_t signaled_types;
-+ uint32_t sequence;
-+ uint32_t waiting_types;
-+ uint32_t error;
-+};
-+
-+#define _DRM_FENCE_CLASSES 8
-+
-+struct drm_fence_class_manager {
-+ struct list_head ring;
-+ uint32_t pending_flush;
-+ uint32_t waiting_types;
-+ wait_queue_head_t fence_queue;
-+ uint32_t highest_waiting_sequence;
-+ uint32_t latest_queued_sequence;
-+};
-+
-+struct drm_fence_manager {
-+ int initialized;
-+ rwlock_t lock;
-+ struct drm_fence_class_manager fence_class[_DRM_FENCE_CLASSES];
-+ uint32_t num_classes;
-+ atomic_t count;
-+};
-+
-+struct drm_fence_driver {
-+ unsigned long *waiting_jiffies;
-+ uint32_t num_classes;
-+ uint32_t wrap_diff;
-+ uint32_t flush_diff;
-+ uint32_t sequence_mask;
-+
-+ /*
-+ * Driver implemented functions:
-+ * has_irq() : 1 if the hardware can update the indicated type_flags using an
-+ * irq handler. 0 if polling is required.
-+ *
-+ * emit() : Emit a sequence number to the command stream.
-+ * Return the sequence number.
-+ *
-+ * flush() : Make sure the flags indicated in fc->pending_flush will eventually
-+ * signal for fc->highest_received_sequence and all preceding sequences.
-+ * Acknowledge by clearing the flags fc->pending_flush.
-+ *
-+ * poll() : Call drm_fence_handler with any new information.
-+ *
-+ * needed_flush() : Given the current state of the fence->type flags and previusly
-+ * executed or queued flushes, return the type_flags that need flushing.
-+ *
-+ * wait(): Wait for the "mask" flags to signal on a given fence, performing
-+ * whatever's necessary to make this happen.
-+ */
-+
-+ int (*has_irq) (struct drm_device *dev, uint32_t fence_class,
-+ uint32_t flags);
-+ int (*emit) (struct drm_device *dev, uint32_t fence_class,
-+ uint32_t flags, uint32_t *breadcrumb,
-+ uint32_t *native_type);
-+ void (*flush) (struct drm_device *dev, uint32_t fence_class);
-+ void (*poll) (struct drm_device *dev, uint32_t fence_class,
-+ uint32_t types);
-+ uint32_t (*needed_flush) (struct drm_fence_object *fence);
-+ int (*wait) (struct drm_fence_object *fence, int lazy,
-+ int interruptible, uint32_t mask);
-+};
-+
-+extern int drm_fence_wait_polling(struct drm_fence_object *fence, int lazy,
-+ int interruptible, uint32_t mask,
-+ unsigned long end_jiffies);
-+extern void drm_fence_handler(struct drm_device *dev, uint32_t fence_class,
-+ uint32_t sequence, uint32_t type,
-+ uint32_t error);
-+extern void drm_fence_manager_init(struct drm_device *dev);
-+extern void drm_fence_manager_takedown(struct drm_device *dev);
-+extern void drm_fence_flush_old(struct drm_device *dev, uint32_t fence_class,
-+ uint32_t sequence);
-+extern int drm_fence_object_flush(struct drm_fence_object *fence,
-+ uint32_t type);
-+extern int drm_fence_object_signaled(struct drm_fence_object *fence,
-+ uint32_t type);
-+extern void drm_fence_usage_deref_locked(struct drm_fence_object **fence);
-+extern void drm_fence_usage_deref_unlocked(struct drm_fence_object **fence);
-+extern struct drm_fence_object *drm_fence_reference_locked(struct drm_fence_object *src);
-+extern void drm_fence_reference_unlocked(struct drm_fence_object **dst,
-+ struct drm_fence_object *src);
-+extern int drm_fence_object_wait(struct drm_fence_object *fence,
-+ int lazy, int ignore_signals, uint32_t mask);
-+extern int drm_fence_object_create(struct drm_device *dev, uint32_t type,
-+ uint32_t fence_flags, uint32_t fence_class,
-+ struct drm_fence_object **c_fence);
-+extern int drm_fence_object_emit(struct drm_fence_object *fence,
-+ uint32_t fence_flags, uint32_t class,
-+ uint32_t type);
-+extern void drm_fence_fill_arg(struct drm_fence_object *fence,
-+ struct drm_fence_arg *arg);
-+
-+extern int drm_fence_add_user_object(struct drm_file *priv,
-+ struct drm_fence_object *fence,
-+ int shareable);
-+
-+extern int drm_fence_create_ioctl(struct drm_device *dev, void *data,
-+ struct drm_file *file_priv);
-+extern int drm_fence_destroy_ioctl(struct drm_device *dev, void *data,
-+ struct drm_file *file_priv);
-+extern int drm_fence_reference_ioctl(struct drm_device *dev, void *data,
-+ struct drm_file *file_priv);
-+extern int drm_fence_unreference_ioctl(struct drm_device *dev, void *data,
-+ struct drm_file *file_priv);
-+extern int drm_fence_signaled_ioctl(struct drm_device *dev, void *data,
-+ struct drm_file *file_priv);
-+extern int drm_fence_flush_ioctl(struct drm_device *dev, void *data,
-+ struct drm_file *file_priv);
-+extern int drm_fence_wait_ioctl(struct drm_device *dev, void *data,
-+ struct drm_file *file_priv);
-+extern int drm_fence_emit_ioctl(struct drm_device *dev, void *data,
-+ struct drm_file *file_priv);
-+extern int drm_fence_buffers_ioctl(struct drm_device *dev, void *data,
-+ struct drm_file *file_priv);
-+/**************************************************
-+ *TTMs
-+ */
-+
-+/*
-+ * The ttm backend GTT interface. (In our case AGP).
-+ * Any similar type of device (PCIE?)
-+ * needs only to implement these functions to be usable with the TTM interface.
-+ * The AGP backend implementation lives in drm_agpsupport.c
-+ * basically maps these calls to available functions in agpgart.
-+ * Each drm device driver gets an
-+ * additional function pointer that creates these types,
-+ * so that the device can choose the correct aperture.
-+ * (Multiple AGP apertures, etc.)
-+ * Most device drivers will let this point to the standard AGP implementation.
-+ */
-+
-+#define DRM_BE_FLAG_NEEDS_FREE 0x00000001
-+#define DRM_BE_FLAG_BOUND_CACHED 0x00000002
-+
-+struct drm_ttm_backend;
-+struct drm_ttm_backend_func {
-+ int (*needs_ub_cache_adjust) (struct drm_ttm_backend *backend);
-+ int (*populate) (struct drm_ttm_backend *backend,
-+ unsigned long num_pages, struct page **pages);
-+ void (*clear) (struct drm_ttm_backend *backend);
-+ int (*bind) (struct drm_ttm_backend *backend,
-+ struct drm_bo_mem_reg *bo_mem);
-+ int (*unbind) (struct drm_ttm_backend *backend);
-+ void (*destroy) (struct drm_ttm_backend *backend);
-+};
-+
-+
-+struct drm_ttm_backend {
-+ struct drm_device *dev;
-+ uint32_t flags;
-+ struct drm_ttm_backend_func *func;
-+};
-+
-+struct drm_ttm {
-+ struct page *dummy_read_page;
-+ struct page **pages;
-+ uint32_t page_flags;
-+ unsigned long num_pages;
-+ atomic_t vma_count;
-+ struct drm_device *dev;
-+ int destroy;
-+ uint32_t mapping_offset;
-+ struct drm_ttm_backend *be;
-+ enum {
-+ ttm_bound,
-+ ttm_evicted,
-+ ttm_unbound,
-+ ttm_unpopulated,
-+ } state;
-+
-+};
-+
-+extern struct drm_ttm *drm_ttm_init(struct drm_device *dev, unsigned long size);
-+extern int drm_bind_ttm(struct drm_ttm *ttm, struct drm_bo_mem_reg *bo_mem);
-+extern void drm_ttm_unbind(struct drm_ttm *ttm);
-+extern void drm_ttm_evict(struct drm_ttm *ttm);
-+extern void drm_ttm_fixup_caching(struct drm_ttm *ttm);
-+extern struct page *drm_ttm_get_page(struct drm_ttm *ttm, int index);
-+extern void drm_ttm_cache_flush(void);
-+extern int drm_ttm_populate(struct drm_ttm *ttm);
-+extern int drm_ttm_set_user(struct drm_ttm *ttm,
-+ struct task_struct *tsk,
-+ int write,
-+ unsigned long start,
-+ unsigned long num_pages,
-+ struct page *dummy_read_page);
-+unsigned long drm_ttm_size(struct drm_device *dev,
-+ unsigned long num_pages,
-+ int user_bo);
-+
-+
-+/*
-+ * Destroy a ttm. The user normally calls drmRmMap or a similar IOCTL to do
-+ * this which calls this function iff there are no vmas referencing it anymore.
-+ * Otherwise it is called when the last vma exits.
-+ */
-+
-+extern int drm_destroy_ttm(struct drm_ttm *ttm);
-+
-+#define DRM_FLAG_MASKED(_old, _new, _mask) {\
-+(_old) ^= (((_old) ^ (_new)) & (_mask)); \
-+}
-+
-+#define DRM_TTM_MASK_FLAGS ((1 << PAGE_SHIFT) - 1)
-+#define DRM_TTM_MASK_PFN (0xFFFFFFFFU - DRM_TTM_MASK_FLAGS)
-+
-+/*
-+ * Page flags.
-+ */
-+
-+#define DRM_TTM_PAGE_UNCACHED (1 << 0)
-+#define DRM_TTM_PAGE_USED (1 << 1)
-+#define DRM_TTM_PAGE_BOUND (1 << 2)
-+#define DRM_TTM_PAGE_PRESENT (1 << 3)
-+#define DRM_TTM_PAGE_VMALLOC (1 << 4)
-+#define DRM_TTM_PAGE_USER (1 << 5)
-+#define DRM_TTM_PAGE_USER_WRITE (1 << 6)
-+#define DRM_TTM_PAGE_USER_DIRTY (1 << 7)
-+#define DRM_TTM_PAGE_USER_DMA (1 << 8)
-+
-+/***************************************************
-+ * Buffer objects. (drm_bo.c, drm_bo_move.c)
-+ */
-+
-+struct drm_bo_mem_reg {
-+ struct drm_mm_node *mm_node;
-+ unsigned long size;
-+ unsigned long num_pages;
-+ uint32_t page_alignment;
-+ uint32_t mem_type;
-+ uint64_t flags;
-+ uint64_t mask;
-+ uint32_t desired_tile_stride;
-+ uint32_t hw_tile_stride;
-+};
-+
-+enum drm_bo_type {
-+ drm_bo_type_dc,
-+ drm_bo_type_user,
-+ drm_bo_type_kernel, /* for initial kernel allocations */
-+};
-+
-+struct drm_buffer_object {
-+ struct drm_device *dev;
-+ struct drm_user_object base;
-+
-+ /*
-+ * If there is a possibility that the usage variable is zero,
-+ * then dev->struct_mutext should be locked before incrementing it.
-+ */
-+
-+ atomic_t usage;
-+ unsigned long buffer_start;
-+ enum drm_bo_type type;
-+ unsigned long offset;
-+ atomic_t mapped;
-+ struct drm_bo_mem_reg mem;
-+
-+ struct list_head lru;
-+ struct list_head ddestroy;
-+
-+ uint32_t fence_type;
-+ uint32_t fence_class;
-+ uint32_t new_fence_type;
-+ uint32_t new_fence_class;
-+ struct drm_fence_object *fence;
-+ uint32_t priv_flags;
-+ wait_queue_head_t event_queue;
-+ struct mutex mutex;
-+ unsigned long num_pages;
-+ unsigned long reserved_size;
-+
-+ /* For pinned buffers */
-+ struct drm_mm_node *pinned_node;
-+ uint32_t pinned_mem_type;
-+ struct list_head pinned_lru;
-+
-+ /* For vm */
-+ struct drm_ttm *ttm;
-+ struct drm_map_list map_list;
-+ uint32_t memory_type;
-+ unsigned long bus_offset;
-+ uint32_t vm_flags;
-+ void *iomap;
-+
-+#ifdef DRM_ODD_MM_COMPAT
-+ /* dev->struct_mutex only protected. */
-+ struct list_head vma_list;
-+ struct list_head p_mm_list;
-+#endif
-+
-+};
-+
-+#define _DRM_BO_FLAG_UNFENCED 0x00000001
-+#define _DRM_BO_FLAG_EVICTED 0x00000002
-+
-+struct drm_mem_type_manager {
-+ int has_type;
-+ int use_type;
-+ struct drm_mm manager;
-+ struct list_head lru;
-+ struct list_head pinned;
-+ uint32_t flags;
-+ uint32_t drm_bus_maptype;
-+ unsigned long gpu_offset;
-+ unsigned long io_offset;
-+ unsigned long io_size;
-+ void *io_addr;
-+};
-+
-+struct drm_bo_lock {
-+ struct drm_user_object base;
-+ wait_queue_head_t queue;
-+ atomic_t write_lock_pending;
-+ atomic_t readers;
-+};
-+
-+#define _DRM_FLAG_MEMTYPE_FIXED 0x00000001 /* Fixed (on-card) PCI memory */
-+#define _DRM_FLAG_MEMTYPE_MAPPABLE 0x00000002 /* Memory mappable */
-+#define _DRM_FLAG_MEMTYPE_CACHED 0x00000004 /* Cached binding */
-+#define _DRM_FLAG_NEEDS_IOREMAP 0x00000008 /* Fixed memory needs ioremap
-+ before kernel access. */
-+#define _DRM_FLAG_MEMTYPE_CMA 0x00000010 /* Can't map aperture */
-+#define _DRM_FLAG_MEMTYPE_CSELECT 0x00000020 /* Select caching */
-+
-+struct drm_buffer_manager {
-+ struct drm_bo_lock bm_lock;
-+ struct mutex evict_mutex;
-+ int nice_mode;
-+ int initialized;
-+ struct drm_file *last_to_validate;
-+ struct drm_mem_type_manager man[DRM_BO_MEM_TYPES];
-+ struct list_head unfenced;
-+ struct list_head ddestroy;
-+ struct delayed_work wq;
-+ uint32_t fence_type;
-+ unsigned long cur_pages;
-+ atomic_t count;
-+ struct page *dummy_read_page;
-+};
-+
-+struct drm_bo_driver {
-+ const uint32_t *mem_type_prio;
-+ const uint32_t *mem_busy_prio;
-+ uint32_t num_mem_type_prio;
-+ uint32_t num_mem_busy_prio;
-+ struct drm_ttm_backend *(*create_ttm_backend_entry)
-+ (struct drm_device *dev);
-+ int (*backend_size) (struct drm_device *dev,
-+ unsigned long num_pages);
-+ int (*fence_type) (struct drm_buffer_object *bo, uint32_t *fclass,
-+ uint32_t *type);
-+ int (*invalidate_caches) (struct drm_device *dev, uint64_t flags);
-+ int (*init_mem_type) (struct drm_device *dev, uint32_t type,
-+ struct drm_mem_type_manager *man);
-+ uint32_t(*evict_mask) (struct drm_buffer_object *bo);
-+ int (*move) (struct drm_buffer_object *bo,
-+ int evict, int no_wait, struct drm_bo_mem_reg *new_mem);
-+ void (*ttm_cache_flush)(struct drm_ttm *ttm);
-+
-+ /*
-+ * command_stream_barrier
-+ *
-+ * @dev: The drm device.
-+ *
-+ * @bo: The buffer object to validate.
-+ *
-+ * @new_fence_class: The new fence class for the buffer object.
-+ *
-+ * @new_fence_type: The new fence type for the buffer object.
-+ *
-+ * @no_wait: whether this should give up and return -EBUSY
-+ * if this operation would require sleeping
-+ *
-+ * Insert a command stream barrier that makes sure that the
-+ * buffer is idle once the commands associated with the
-+ * current validation are starting to execute. If an error
-+ * condition is returned, or the function pointer is NULL,
-+ * the drm core will force buffer idle
-+ * during validation.
-+ */
-+
-+ int (*command_stream_barrier) (struct drm_buffer_object *bo,
-+ uint32_t new_fence_class,
-+ uint32_t new_fence_type,
-+ int no_wait);
-+};
-+
-+/*
-+ * buffer objects (drm_bo.c)
-+ */
-+extern int drm_bo_create_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
-+extern int drm_bo_destroy_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
-+extern int drm_bo_map_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
-+extern int drm_bo_unmap_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
-+extern int drm_bo_reference_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
-+extern int drm_bo_set_pin(struct drm_device *dev, struct drm_buffer_object *bo, int pin);
-+extern int drm_bo_unreference_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
-+extern int drm_bo_wait_idle_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
-+extern int drm_bo_info_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
-+extern int drm_bo_setstatus_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
-+extern int drm_mm_init_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
-+extern int drm_mm_takedown_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
-+extern int drm_mm_lock_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
-+extern int drm_mm_unlock_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
-+extern int drm_bo_version_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
-+extern int drm_bo_driver_finish(struct drm_device *dev);
-+extern int drm_bo_driver_init(struct drm_device *dev);
-+extern int drm_bo_pci_offset(struct drm_device *dev,
-+ struct drm_bo_mem_reg *mem,
-+ unsigned long *bus_base,
-+ unsigned long *bus_offset,
-+ unsigned long *bus_size);
-+extern int drm_mem_reg_is_pci(struct drm_device *dev, struct drm_bo_mem_reg *mem);
-+
-+extern void drm_bo_usage_deref_locked(struct drm_buffer_object **bo);
-+extern void drm_bo_usage_deref_unlocked(struct drm_buffer_object **bo);
-+extern void drm_putback_buffer_objects(struct drm_device *dev);
-+extern int drm_fence_buffer_objects(struct drm_device *dev,
-+ struct list_head *list,
-+ uint32_t fence_flags,
-+ struct drm_fence_object *fence,
-+ struct drm_fence_object **used_fence);
-+extern void drm_bo_add_to_lru(struct drm_buffer_object *bo);
-+extern int drm_buffer_object_create(struct drm_device *dev, unsigned long size,
-+ enum drm_bo_type type, uint64_t mask,
-+ uint32_t hint, uint32_t page_alignment,
-+ unsigned long buffer_start,
-+ struct drm_buffer_object **bo);
-+extern int drm_bo_wait(struct drm_buffer_object *bo, int lazy, int ignore_signals,
-+ int no_wait);
-+extern int drm_bo_mem_space(struct drm_buffer_object *bo,
-+ struct drm_bo_mem_reg *mem, int no_wait);
-+extern int drm_bo_move_buffer(struct drm_buffer_object *bo,
-+ uint64_t new_mem_flags,
-+ int no_wait, int move_unfenced);
-+extern int drm_bo_clean_mm(struct drm_device *dev, unsigned mem_type);
-+extern int drm_bo_init_mm(struct drm_device *dev, unsigned type,
-+ unsigned long p_offset, unsigned long p_size);
-+extern int drm_bo_handle_validate(struct drm_file *file_priv, uint32_t handle,
-+ uint32_t fence_class, uint64_t flags,
-+ uint64_t mask, uint32_t hint,
-+ int use_old_fence_class,
-+ struct drm_bo_info_rep *rep,
-+ struct drm_buffer_object **bo_rep);
-+extern struct drm_buffer_object *drm_lookup_buffer_object(struct drm_file *file_priv,
-+ uint32_t handle,
-+ int check_owner);
-+extern int drm_bo_do_validate(struct drm_buffer_object *bo,
-+ uint64_t flags, uint64_t mask, uint32_t hint,
-+ uint32_t fence_class,
-+ int no_wait,
-+ struct drm_bo_info_rep *rep);
-+extern void drm_bo_fill_rep_arg(struct drm_buffer_object *bo,
-+ struct drm_bo_info_rep *rep);
-+/*
-+ * Buffer object memory move- and map helpers.
-+ * drm_bo_move.c
-+ */
-+
-+extern int drm_bo_move_ttm(struct drm_buffer_object *bo,
-+ int evict, int no_wait,
-+ struct drm_bo_mem_reg *new_mem);
-+extern int drm_bo_move_memcpy(struct drm_buffer_object *bo,
-+ int evict,
-+ int no_wait, struct drm_bo_mem_reg *new_mem);
-+extern int drm_bo_move_accel_cleanup(struct drm_buffer_object *bo,
-+ int evict, int no_wait,
-+ uint32_t fence_class, uint32_t fence_type,
-+ uint32_t fence_flags,
-+ struct drm_bo_mem_reg *new_mem);
-+extern int drm_bo_same_page(unsigned long offset, unsigned long offset2);
-+extern unsigned long drm_bo_offset_end(unsigned long offset,
-+ unsigned long end);
-+
-+struct drm_bo_kmap_obj {
-+ void *virtual;
-+ struct page *page;
-+ enum {
-+ bo_map_iomap,
-+ bo_map_vmap,
-+ bo_map_kmap,
-+ bo_map_premapped,
-+ } bo_kmap_type;
-+};
-+
-+static inline void *drm_bmo_virtual(struct drm_bo_kmap_obj *map, int *is_iomem)
-+{
-+ *is_iomem = (map->bo_kmap_type == bo_map_iomap ||
-+ map->bo_kmap_type == bo_map_premapped);
-+ return map->virtual;
-+}
-+extern void drm_bo_kunmap(struct drm_bo_kmap_obj *map);
-+extern int drm_bo_kmap(struct drm_buffer_object *bo, unsigned long start_page,
-+ unsigned long num_pages, struct drm_bo_kmap_obj *map);
-+
-+
-+/*
-+ * drm_regman.c
-+ */
-+
-+struct drm_reg {
-+ struct list_head head;
-+ struct drm_fence_object *fence;
-+ uint32_t fence_type;
-+ uint32_t new_fence_type;
-+};
-+
-+struct drm_reg_manager {
-+ struct list_head free;
-+ struct list_head lru;
-+ struct list_head unfenced;
-+
-+ int (*reg_reusable)(const struct drm_reg *reg, const void *data);
-+ void (*reg_destroy)(struct drm_reg *reg);
-+};
-+
-+extern int drm_regs_alloc(struct drm_reg_manager *manager,
-+ const void *data,
-+ uint32_t fence_class,
-+ uint32_t fence_type,
-+ int interruptible,
-+ int no_wait,
-+ struct drm_reg **reg);
-+
-+extern void drm_regs_fence(struct drm_reg_manager *regs,
-+ struct drm_fence_object *fence);
-+
-+extern void drm_regs_free(struct drm_reg_manager *manager);
-+extern void drm_regs_add(struct drm_reg_manager *manager, struct drm_reg *reg);
-+extern void drm_regs_init(struct drm_reg_manager *manager,
-+ int (*reg_reusable)(const struct drm_reg *,
-+ const void *),
-+ void (*reg_destroy)(struct drm_reg *));
-+
-+extern int drm_mem_reg_ioremap(struct drm_device *dev, struct drm_bo_mem_reg * mem,
-+ void **virtual);
-+extern void drm_mem_reg_iounmap(struct drm_device *dev, struct drm_bo_mem_reg * mem,
-+ void *virtual);
-+/*
-+ * drm_bo_lock.c
-+ * Simple replacement for the hardware lock on buffer manager init and clean.
-+ */
-+
-+
-+extern void drm_bo_init_lock(struct drm_bo_lock *lock);
-+extern void drm_bo_read_unlock(struct drm_bo_lock *lock);
-+extern int drm_bo_read_lock(struct drm_bo_lock *lock);
-+extern int drm_bo_write_lock(struct drm_bo_lock *lock,
-+ struct drm_file *file_priv);
-+
-+extern int drm_bo_write_unlock(struct drm_bo_lock *lock,
-+ struct drm_file *file_priv);
-+
-+#ifdef CONFIG_DEBUG_MUTEXES
-+#define DRM_ASSERT_LOCKED(_mutex) \
-+ BUG_ON(!mutex_is_locked(_mutex) || \
-+ ((_mutex)->owner != current_thread_info()))
-+#else
-+#define DRM_ASSERT_LOCKED(_mutex)
-+#endif
-+#endif
-Index: linux-2.6.28/drivers/gpu/drm/drm_proc.c
-===================================================================
---- linux-2.6.28.orig/drivers/gpu/drm/drm_proc.c 2009-02-12 09:14:37.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/drm_proc.c 2009-02-12 09:14:42.000000000 +0000
-@@ -489,13 +489,13 @@
-
- for (crtc = 0; crtc < dev->num_crtcs; crtc++) {
- DRM_PROC_PRINT("CRTC %d enable: %d\n",
-- crtc, atomic_read(&dev->vblank_refcount[crtc]));
-+ crtc, 1);
- DRM_PROC_PRINT("CRTC %d counter: %d\n",
-- crtc, drm_vblank_count(dev, crtc));
-+ crtc, 1);
- DRM_PROC_PRINT("CRTC %d last wait: %d\n",
-- crtc, dev->last_vblank_wait[crtc]);
-+ crtc, 1);
- DRM_PROC_PRINT("CRTC %d in modeset: %d\n",
-- crtc, dev->vblank_inmodeset[crtc]);
-+ crtc, 1);
- }
-
- if (len > request + offset)
-Index: linux-2.6.28/drivers/gpu/drm/drm_crtc.c
-===================================================================
---- linux-2.6.28.orig/drivers/gpu/drm/drm_crtc.c 2009-02-12 09:14:37.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/drm_crtc.c 2009-02-12 09:14:42.000000000 +0000
-@@ -807,6 +807,53 @@
- }
- EXPORT_SYMBOL(drm_mode_config_init);
-
-+/**
-+ * drm_get_buffer_object - find the buffer object for a given handle
-+ * @dev: DRM device
-+ * @bo: pointer to caller's buffer_object pointer
-+ * @handle: handle to lookup
-+ *
-+ * LOCKING:
-+ * Must take @dev's struct_mutex to protect buffer object lookup.
-+ *
-+ * Given @handle, lookup the buffer object in @dev and put it in the caller's
-+ * @bo pointer.
-+ *
-+ * RETURNS:
-+ * Zero on success, -EINVAL if the handle couldn't be found.
-+ */
-+static int drm_get_buffer_object(struct drm_device *dev, struct drm_buffer_object **bo, unsigned long handle)
-+{
-+ struct drm_user_object *uo;
-+ struct drm_hash_item *hash;
-+ int ret;
-+
-+ *bo = NULL;
-+
-+ mutex_lock(&dev->struct_mutex);
-+ ret = drm_ht_find_item(&dev->object_hash, handle, &hash);
-+ if (ret) {
-+ DRM_ERROR("Couldn't find handle.\n");
-+ ret = -EINVAL;
-+ goto out_err;
-+ }
-+
-+ uo = drm_hash_entry(hash, struct drm_user_object, hash);
-+ if (uo->type != drm_buffer_type) {
-+ ret = -EINVAL;
-+ goto out_err;
-+ }
-+
-+ *bo = drm_user_object_entry(uo, struct drm_buffer_object, base);
-+ ret = 0;
-+out_err:
-+ mutex_unlock(&dev->struct_mutex);
-+ return ret;
-+}
-+
-+char drm_init_mode[32];
-+EXPORT_SYMBOL(drm_init_mode);
-+
- int drm_mode_group_init(struct drm_device *dev, struct drm_mode_group *group)
- {
- uint32_t total_objects = 0;
-@@ -1588,6 +1635,8 @@
- struct drm_mode_fb_cmd *r = data;
- struct drm_mode_config *config = &dev->mode_config;
- struct drm_framebuffer *fb;
-+ struct drm_buffer_object *bo;
-+ struct drm_crtc *crtc;
- int ret = 0;
-
- if ((config->min_width > r->width) || (r->width > config->max_width)) {
-@@ -1600,20 +1649,46 @@
- }
-
- mutex_lock(&dev->mode_config.mutex);
-+ /* TODO check limits are okay */
-+ ret = drm_get_buffer_object(dev, &bo, r->handle);
-+ if (ret || !bo) {
-+ ret = -EINVAL;
-+ goto out;
-+ }
-
- /* TODO check buffer is sufficently large */
- /* TODO setup destructor callback */
-
-- fb = dev->mode_config.funcs->fb_create(dev, file_priv, r);
-+ fb = kzalloc(sizeof(struct drm_framebuffer), GFP_KERNEL);
-+ if (!fb) {
-+ ret = -ENOMEM;
-+ goto out;
-+ }
-+
-+ drm_framebuffer_init(dev, fb, NULL);
- if (!fb) {
- DRM_ERROR("could not create framebuffer\n");
- ret = -EINVAL;
- goto out;
- }
-
-+ fb->width = r->width;
-+ fb->height = r->height;
-+ fb->pitch = r->pitch;
-+ fb->bits_per_pixel = r->bpp;
-+ fb->depth = r->depth;
-+ fb->offset = bo->offset;
-+ fb->bo = bo;
-+
- r->fb_id = fb->base.id;
- list_add(&fb->filp_head, &file_priv->fbs);
-
-+ /* FIXME: bind the fb to the right crtc */
-+ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-+ crtc->fb = fb;
-+ dev->driver->fb_probe(dev, crtc);
-+ }
-+
- out:
- mutex_unlock(&dev->mode_config.mutex);
- return ret;
-@@ -1669,8 +1744,10 @@
- /* TODO release all crtc connected to the framebuffer */
- /* TODO unhock the destructor from the buffer object */
-
-- list_del(&fb->filp_head);
-- fb->funcs->destroy(fb);
-+ if (fb->bo->type != drm_bo_type_kernel)
-+ drm_framebuffer_cleanup(fb);
-+ else
-+ dev->driver->fb_remove(dev, drm_crtc_from_fb(dev, fb));
-
- out:
- mutex_unlock(&dev->mode_config.mutex);
-@@ -1716,7 +1793,7 @@
- r->depth = fb->depth;
- r->bpp = fb->bits_per_pixel;
- r->pitch = fb->pitch;
-- fb->funcs->create_handle(fb, file_priv, &r->handle);
-+ r->handle = fb->bo->base.hash.key;
-
- out:
- mutex_unlock(&dev->mode_config.mutex);
-@@ -1746,7 +1823,10 @@
- mutex_lock(&dev->mode_config.mutex);
- list_for_each_entry_safe(fb, tfb, &priv->fbs, filp_head) {
- list_del(&fb->filp_head);
-- fb->funcs->destroy(fb);
-+ if (fb->bo->type != drm_bo_type_kernel)
-+ drm_framebuffer_cleanup(fb);
-+ else
-+ dev->driver->fb_remove(dev, drm_crtc_from_fb(dev, fb));
- }
- mutex_unlock(&dev->mode_config.mutex);
- }
-Index: linux-2.6.28/drivers/gpu/drm/drm_sysfs.c
-===================================================================
---- linux-2.6.28.orig/drivers/gpu/drm/drm_sysfs.c 2009-02-12 09:14:37.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/drm_sysfs.c 2009-02-12 09:14:42.000000000 +0000
-@@ -156,8 +156,9 @@
- enum drm_connector_status status;
-
- status = connector->funcs->detect(connector);
-- return snprintf(buf, PAGE_SIZE, "%s",
-- drm_get_connector_status_name(status));
-+ return 0;
-+ //return snprintf(buf, PAGE_SIZE, "%s",
-+ // drm_get_connector_status_name(status));
- }
-
- static ssize_t dpms_show(struct device *device,
-Index: linux-2.6.28/include/drm/drm_crtc.h
+ out:
+ mutex_unlock(&dev->mode_config.mutex);
+ return ret;
+@@ -1669,8 +1744,10 @@
+ /* TODO release all crtc connected to the framebuffer */
+ /* TODO unhock the destructor from the buffer object */
+
+- list_del(&fb->filp_head);
+- fb->funcs->destroy(fb);
++ if (fb->bo->type != drm_bo_type_kernel)
++ drm_framebuffer_cleanup(fb);
++ else
++ dev->driver->fb_remove(dev, drm_crtc_from_fb(dev, fb));
+
+ out:
+ mutex_unlock(&dev->mode_config.mutex);
+@@ -1716,7 +1793,7 @@
+ r->depth = fb->depth;
+ r->bpp = fb->bits_per_pixel;
+ r->pitch = fb->pitch;
+- fb->funcs->create_handle(fb, file_priv, &r->handle);
++ r->handle = fb->bo->base.hash.key;
+
+ out:
+ mutex_unlock(&dev->mode_config.mutex);
+@@ -1746,7 +1823,10 @@
+ mutex_lock(&dev->mode_config.mutex);
+ list_for_each_entry_safe(fb, tfb, &priv->fbs, filp_head) {
+ list_del(&fb->filp_head);
+- fb->funcs->destroy(fb);
++ if (fb->bo->type != drm_bo_type_kernel)
++ drm_framebuffer_cleanup(fb);
++ else
++ dev->driver->fb_remove(dev, drm_crtc_from_fb(dev, fb));
+ }
+ mutex_unlock(&dev->mode_config.mutex);
+ }
+Index: linux-2.6.28/include/drm/drm_crtc.h
===================================================================
--- linux-2.6.28.orig/include/drm/drm_crtc.h 2009-02-12 09:14:40.000000000 +0000
+++ linux-2.6.28/include/drm/drm_crtc.h 2009-02-12 09:14:42.000000000 +0000
Index: linux-2.6.28/drivers/gpu/drm/i915/intel_crt.c
===================================================================
--- linux-2.6.28.orig/drivers/gpu/drm/i915/intel_crt.c 2009-02-12 09:14:37.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/i915/intel_crt.c 2009-02-12 09:14:42.000000000 +0000
++++ linux-2.6.28/drivers/gpu/drm/i915/intel_crt.c 2009-02-12 16:12:38.000000000 +0000
@@ -36,7 +36,7 @@
static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
{
if (intel_crt_detect_hotplug(connector))
return connector_status_connected;
else
-@@ -189,7 +189,7 @@
- struct intel_output *intel_output = to_intel_output(connector);
-
- intel_i2c_destroy(intel_output->ddc_bus);
-- drm_sysfs_connector_remove(connector);
-+ //drm_sysfs_connector_remove(connector);
- drm_connector_cleanup(connector);
- kfree(connector);
- }
-@@ -280,5 +280,5 @@
- drm_encoder_helper_add(&intel_output->enc, &intel_crt_helper_funcs);
- drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
-
-- drm_sysfs_connector_add(connector);
-+ //drm_sysfs_connector_add(connector);
- }
Index: linux-2.6.28/drivers/gpu/drm/i915/intel_lvds.c
===================================================================
--- linux-2.6.28.orig/drivers/gpu/drm/i915/intel_lvds.c 2009-02-12 09:14:37.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/i915/intel_lvds.c 2009-02-12 09:14:42.000000000 +0000
++++ linux-2.6.28/drivers/gpu/drm/i915/intel_lvds.c 2009-02-12 16:13:08.000000000 +0000
@@ -36,6 +36,259 @@
#include "i915_drm.h"
#include "i915_drv.h"
if (ret)
return ret;
-@@ -333,9 +637,12 @@
+@@ -333,8 +637,11 @@
{
struct intel_output *intel_output = to_intel_output(connector);
+ iounmap(dev_OpRegion);
if (intel_output->ddc_bus)
intel_i2c_destroy(intel_output->ddc_bus);
-- drm_sysfs_connector_remove(connector);
+ intel_i2c_destroy(lvds_i2c_bus);
-+ //drm_sysfs_connector_remove(connector);
+ drm_sysfs_connector_remove(connector);
drm_connector_cleanup(connector);
kfree(connector);
- }
@@ -373,7 +680,45 @@
};
- }
- }
-
- /*
- * If we didn't get EDID, try checking if the panel is already turned
- * on. If so, assume that whatever is currently programmed is the
-@@ -520,7 +1001,7 @@
-
-
- out:
-- drm_sysfs_connector_add(connector);
-+ //drm_sysfs_connector_add(connector);
- return;
-
- failed:
+ /*
+ * If we didn't get EDID, try checking if the panel is already turned
+ * on. If so, assume that whatever is currently programmed is the
Index: linux-2.6.28/drivers/gpu/drm/i915/intel_sdvo.c
===================================================================
--- linux-2.6.28.orig/drivers/gpu/drm/i915/intel_sdvo.c 2009-02-12 09:14:37.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/i915/intel_sdvo.c 2009-02-12 09:14:42.000000000 +0000
++++ linux-2.6.28/drivers/gpu/drm/i915/intel_sdvo.c 2009-02-12 16:12:58.000000000 +0000
@@ -37,6 +37,14 @@
#undef SDVO_DEBUG
struct intel_output *intel_output = to_intel_output(connector);
struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
int o;
-@@ -941,7 +949,7 @@
-
- if (intel_output->i2c_bus)
- intel_i2c_destroy(intel_output->i2c_bus);
-- drm_sysfs_connector_remove(connector);
-+ //drm_sysfs_connector_remove(connector);
- drm_connector_cleanup(connector);
- kfree(intel_output);
- }
@@ -988,6 +996,32 @@
u8 ch[0x40];
int i;
intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
if (!intel_output) {
-@@ -1087,7 +1121,7 @@
- connector->connector_type = connector_type;
-
- drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc);
-- drm_sysfs_connector_add(connector);
-+ //drm_sysfs_connector_add(connector);
-
- /* Set the input timing to the screen. Assume always input 0. */
- intel_sdvo_set_target_input(intel_output, true, false);
Index: linux-2.6.28/drivers/gpu/drm/psb/psb_priv.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/psb/psb_priv.h 2009-02-12 09:14:42.000000000 +0000
-@@ -0,0 +1,238 @@
++++ linux-2.6.28/drivers/gpu/drm/psb/psb_priv.h 2009-02-12 10:11:32.000000000 +0000
+@@ -0,0 +1,244 @@
+#include "psb_drm.h"
+#include "psb_reg.h"
+#include "psb_schedule.h"
+ uint32_t msvdx_start_idle;
+ unsigned long msvdx_idle_start_jiffies;
+
-+ int fence2_irq_on;
++ int fence2_irq_on;
++
++ /*
++ * MSVDX Rendec Memory
++ */
++ struct drm_buffer_object *ccb0;
++ uint32_t base_addr0;
++ struct drm_buffer_object *ccb1;
++ uint32_t base_addr1;
++
++ /*
++ * Memory managers
++ */
++
++ int have_vram;
++ int have_tt;
++ int have_mem_mmu;
++ int have_mem_aper;
++ int have_mem_kernel;
++ int have_mem_pds;
++ int have_mem_rastgeom;
++ struct mutex temp_mem;
++
++ /*
++ * Relocation buffer mapping.
++ */
++
++ spinlock_t reloc_lock;
++ unsigned int rel_mapped_pages;
++ wait_queue_head_t rel_mapped_queue;
++
++ /*
++ * SAREA
++ */
++ struct drm_psb_sarea *sarea_priv;
++
++ /*
++ * LVDS info
++ */
++ int backlight_duty_cycle; /* restore backlight to this value */
++ bool panel_wants_dither;
++ struct drm_display_mode *panel_fixed_mode;
++
++ /*
++ * Register state
++ */
++ uint32_t saveDSPACNTR;
++ uint32_t saveDSPBCNTR;
++ uint32_t savePIPEACONF;
++ uint32_t savePIPEBCONF;
++ uint32_t savePIPEASRC;
++ uint32_t savePIPEBSRC;
++ uint32_t saveFPA0;
++ uint32_t saveFPA1;
++ uint32_t saveDPLL_A;
++ uint32_t saveDPLL_A_MD;
++ uint32_t saveHTOTAL_A;
++ uint32_t saveHBLANK_A;
++ uint32_t saveHSYNC_A;
++ uint32_t saveVTOTAL_A;
++ uint32_t saveVBLANK_A;
++ uint32_t saveVSYNC_A;
++ uint32_t saveDSPASTRIDE;
++ uint32_t saveDSPASIZE;
++ uint32_t saveDSPAPOS;
++ uint32_t saveDSPABASE;
++ uint32_t saveDSPASURF;
++ uint32_t saveFPB0;
++ uint32_t saveFPB1;
++ uint32_t saveDPLL_B;
++ uint32_t saveDPLL_B_MD;
++ uint32_t saveHTOTAL_B;
++ uint32_t saveHBLANK_B;
++ uint32_t saveHSYNC_B;
++ uint32_t saveVTOTAL_B;
++ uint32_t saveVBLANK_B;
++ uint32_t saveVSYNC_B;
++ uint32_t saveDSPBSTRIDE;
++ uint32_t saveDSPBSIZE;
++ uint32_t saveDSPBPOS;
++ uint32_t saveDSPBBASE;
++ uint32_t saveDSPBSURF;
++ uint32_t saveVCLK_DIVISOR_VGA0;
++ uint32_t saveVCLK_DIVISOR_VGA1;
++ uint32_t saveVCLK_POST_DIV;
++ uint32_t saveVGACNTRL;
++ uint32_t saveADPA;
++ uint32_t saveLVDS;
++ uint32_t saveDVOA;
++ uint32_t saveDVOB;
++ uint32_t saveDVOC;
++ uint32_t savePP_ON;
++ uint32_t savePP_OFF;
++ uint32_t savePP_CONTROL;
++ uint32_t savePP_CYCLE;
++ uint32_t savePFIT_CONTROL;
++ uint32_t savePaletteA[256];
++ uint32_t savePaletteB[256];
++ uint32_t saveBLC_PWM_CTL;
++ uint32_t saveCLOCKGATING;
++
++ /*
++ * USE code base register management.
++ */
++
++ struct drm_reg_manager use_manager;
++
++ /*
++ * Xhw
++ */
++
++ uint32_t *xhw;
++ struct drm_buffer_object *xhw_bo;
++ struct drm_bo_kmap_obj xhw_kmap;
++ struct list_head xhw_in;
++ spinlock_t xhw_lock;
++ atomic_t xhw_client;
++ struct drm_file *xhw_file;
++ wait_queue_head_t xhw_queue;
++ wait_queue_head_t xhw_caller_queue;
++ struct mutex xhw_mutex;
++ struct psb_xhw_buf *xhw_cur_buf;
++ int xhw_submit_ok;
++ int xhw_on;
++
++ /*
++ * Scheduling.
++ */
++
++ struct mutex reset_mutex;
++ struct mutex cmdbuf_mutex;
++ struct psb_scheduler scheduler;
++ struct psb_buflist_item *buffers;
++ uint32_t ta_mem_pages;
++ struct psb_ta_mem *ta_mem;
++ int force_ta_mem_load;
++
++ /*
++ * Watchdog
++ */
++
++ spinlock_t watchdog_lock;
++ struct timer_list watchdog_timer;
++ struct work_struct watchdog_wq;
++ struct work_struct msvdx_watchdog_wq;
++ int timer_available;
++
++ /*
++ * msvdx command queue
++ */
++ spinlock_t msvdx_lock;
++ struct mutex msvdx_mutex;
++ struct list_head msvdx_queue;
++ int msvdx_busy;
++
++};
++
++
++extern void intel_modeset_init(struct drm_device *dev);
++extern void intel_modeset_cleanup(struct drm_device *dev);
++
++extern void intel_crtc_mode_restore(struct drm_crtc *crtc);
++extern void intel_crtc_mode_save(struct drm_crtc *crtc);
+Index: linux-2.6.28/drivers/gpu/drm/i915/i915_drv.h
+===================================================================
+--- linux-2.6.28.orig/drivers/gpu/drm/i915/i915_drv.h 2009-02-12 09:47:51.000000000 +0000
++++ linux-2.6.28/drivers/gpu/drm/i915/i915_drv.h 2009-02-12 10:06:18.000000000 +0000
+@@ -672,6 +672,7 @@
+ LOCK_TEST_WITH_RETURN(dev, file_priv); \
+ } while (0)
+
++#ifndef I915_READ
+ #define I915_READ(reg) readl(dev_priv->regs + (reg))
+ #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
+ #define I915_READ16(reg) readw(dev_priv->regs + (reg))
+@@ -685,6 +686,7 @@
+ writel(upper_32_bits(val), dev_priv->regs + \
+ (reg) + 4))
+ #endif
++#endif
+ #define POSTING_READ(reg) (void)I915_READ(reg)
+
+ #define I915_VERBOSE 0
+@@ -776,10 +778,15 @@
+ (dev)->pci_device == 0x29D2)
+
+ #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
+- IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
++ IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
++ IS_POULSBO(dev))
++
++#define IS_POULSBO(dev) (((dev)->pci_device == 0x8108) || \
++ ((dev)->pci_device == 0x8109))
+
+ #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
+- IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev))
++ IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
++ IS_POULSBO(dev))
+
+ #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev))
+ #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev))
+Index: linux-2.6.28/drivers/gpu/drm/i915/intel_display.c
+===================================================================
+--- linux-2.6.28.orig/drivers/gpu/drm/i915/intel_display.c 2009-02-12 09:58:47.000000000 +0000
++++ linux-2.6.28/drivers/gpu/drm/i915/intel_display.c 2009-02-12 16:32:26.000000000 +0000
+@@ -26,9 +26,9 @@
+
+ #include <linux/i2c.h>
+ #include "drmP.h"
+-#include "intel_drv.h"
++#include "../i915/intel_drv.h"
+ #include "i915_drm.h"
+-#include "i915_drv.h"
++#include "../i915/i915_drv.h"
+
+ #include "drm_crtc_helper.h"
+
+@@ -282,7 +282,7 @@
+ int refclk, intel_clock_t *best_clock)
+ {
+ struct drm_device *dev = crtc->dev;
+- struct drm_i915_private *dev_priv = dev->dev_private;
++ DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
+ intel_clock_t clock;
+ const intel_limit_t *limit = intel_limit(crtc);
+ int err = target;
+@@ -348,12 +348,8 @@
+ struct drm_framebuffer *old_fb)
+ {
+ struct drm_device *dev = crtc->dev;
+- struct drm_i915_private *dev_priv = dev->dev_private;
+- struct drm_i915_master_private *master_priv;
++ DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+- struct intel_framebuffer *intel_fb;
+- struct drm_i915_gem_object *obj_priv;
+- struct drm_gem_object *obj;
+ int pipe = intel_crtc->pipe;
+ unsigned long Start, Offset;
+ int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
+@@ -362,66 +358,8 @@
+ int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
+ u32 dspcntr, alignment;
+
+- /* no fb bound */
+- if (!crtc->fb) {
+- DRM_DEBUG("No FB bound\n");
+- return;
+- }
+-
+- intel_fb = to_intel_framebuffer(crtc->fb);
+- obj = intel_fb->obj;
+- obj_priv = obj->driver_private;
+-
+- switch (obj_priv->tiling_mode) {
+- case I915_TILING_NONE:
+- alignment = 64 * 1024;
+- break;
+- case I915_TILING_X:
+- if (IS_I9XX(dev))
+- alignment = 1024 * 1024;
+- else
+- alignment = 512 * 1024;
+- break;
+- case I915_TILING_Y:
+- /* FIXME: Is this true? */
+- DRM_ERROR("Y tiled not allowed for scan out buffers\n");
+- return;
+- default:
+- BUG();
+- }
+-
+- if (i915_gem_object_pin(intel_fb->obj, alignment))
+- return;
+-
+- i915_gem_object_set_to_gtt_domain(intel_fb->obj, 1);
+-
+- Start = obj_priv->gtt_offset;
+- Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
+-
+- I915_WRITE(dspstride, crtc->fb->pitch);
+-
+- dspcntr = I915_READ(dspcntr_reg);
+- /* Mask out pixel format bits in case we change it */
+- dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
+- switch (crtc->fb->bits_per_pixel) {
+- case 8:
+- dspcntr |= DISPPLANE_8BPP;
+- break;
+- case 16:
+- if (crtc->fb->depth == 15)
+- dspcntr |= DISPPLANE_15_16BPP;
+- else
+- dspcntr |= DISPPLANE_16BPP;
+- break;
+- case 24:
+- case 32:
+- dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
+- break;
+- default:
+- DRM_ERROR("Unknown color depth\n");
+- return;
+- }
+- I915_WRITE(dspcntr_reg, dspcntr);
++ Start = crtc->fb->offset;
++ Offset = y * crtc->fb->pitch + x;
+
+ DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
+ if (IS_I965G(dev)) {
+@@ -434,28 +372,18 @@
+ I915_READ(dspbase);
+ }
+
+- intel_wait_for_vblank(dev);
+-
+- if (old_fb) {
+- intel_fb = to_intel_framebuffer(old_fb);
+- i915_gem_object_unpin(intel_fb->obj);
+- }
+-
+- if (!dev->primary->master)
+- return;
+
+- master_priv = dev->primary->master->driver_priv;
+- if (!master_priv->sarea_priv)
++ if (!dev_priv->sarea_priv)
+ return;
+
+ switch (pipe) {
+ case 0:
+- master_priv->sarea_priv->pipeA_x = x;
+- master_priv->sarea_priv->pipeA_y = y;
++ dev_priv->sarea_priv->pipeA_x = x;
++ dev_priv->sarea_priv->pipeA_y = y;
+ break;
+ case 1:
+- master_priv->sarea_priv->pipeB_x = x;
+- master_priv->sarea_priv->pipeB_y = y;
++ dev_priv->sarea_priv->pipeB_x = x;
++ dev_priv->sarea_priv->pipeB_y = y;
+ break;
+ default:
+ DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
+@@ -474,8 +402,7 @@
+ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
+ {
+ struct drm_device *dev = crtc->dev;
+- struct drm_i915_master_private *master_priv;
+- struct drm_i915_private *dev_priv = dev->dev_private;
++ DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int pipe = intel_crtc->pipe;
+ int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
+@@ -569,23 +496,20 @@
+ break;
+ }
+
+- if (!dev->primary->master)
+- return;
+
+- master_priv = dev->primary->master->driver_priv;
+- if (!master_priv->sarea_priv)
++ if (!dev_priv->sarea_priv)
+ return;
+
+ enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
+
+ switch (pipe) {
+ case 0:
+- master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
+- master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
++ dev_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
++ dev_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
+ break;
+ case 1:
+- master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
+- master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
++ dev_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
++ dev_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
+ break;
+ default:
+ DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
+@@ -640,7 +564,7 @@
+ return 400000;
+ else if (IS_I915G(dev))
+ return 333000;
+- else if (IS_I945GM(dev) || IS_845G(dev))
++ else if (IS_I945GM(dev) || IS_POULSBO(dev) || IS_845G(dev))
+ return 200000;
+ else if (IS_I915GM(dev)) {
+ u16 gcfgc = 0;
+@@ -687,7 +611,7 @@
+ */
+ static int intel_panel_fitter_pipe (struct drm_device *dev)
+ {
+- struct drm_i915_private *dev_priv = dev->dev_private;
++ DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
+ u32 pfit_control;
+
+ /* i830 doesn't have a panel fitter */
+@@ -707,7 +631,228 @@
+ /* older chips can only use pipe 1 */
+ return 1;
+ }
++#if 0
++#define WA_NO_FB_GARBAGE_DISPLAY
++#ifdef WA_NO_FB_GARBAGE_DISPLAY
++static u32 fp_reg_value[2];
++static u32 dpll_reg_value[2];
++static u32 dpll_md_reg_value[2];
++static u32 dspcntr_reg_value[2];
++static u32 pipeconf_reg_value[2];
++static u32 htot_reg_value[2];
++static u32 hblank_reg_value[2];
++static u32 hsync_reg_value[2];
++static u32 vtot_reg_value[2];
++static u32 vblank_reg_value[2];
++static u32 vsync_reg_value[2];
++static u32 dspsize_reg_value[2];
++static u32 dspstride_reg_value[2];
++static u32 dsppos_reg_value[2];
++static u32 pipesrc_reg_value[2];
++
++static u32 dspbase_value[2];
+
-+ /*
-+ * MSVDX Rendec Memory
-+ */
-+ struct drm_buffer_object *ccb0;
-+ uint32_t base_addr0;
-+ struct drm_buffer_object *ccb1;
-+ uint32_t base_addr1;
++static u32 lvds_reg_value[2];
++static u32 vgacntrl_reg_value[2];
++static u32 pfit_control_reg_value[2];
+
-+ /*
-+ * Memory managers
-+ */
+
-+ int have_vram;
-+ int have_tt;
-+ int have_mem_mmu;
-+ int have_mem_aper;
-+ int have_mem_kernel;
-+ int have_mem_pds;
-+ int have_mem_rastgeom;
-+ struct mutex temp_mem;
++void intel_crtc_mode_restore(struct drm_crtc *crtc)
++{
++ struct drm_device *dev = crtc->dev;
++ DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
++ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
++ int pipe = intel_crtc->pipe;
++ int fp_reg = (pipe == 0) ? FPA0 : FPB0;
++ int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
++ int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
++ int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
++ int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
++ int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
++ int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
++ int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
++ int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
++ int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
++ int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
++ int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
++ int dspstride_reg = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
++ int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
++ int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
++ int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
+
-+ /*
-+ * Relocation buffer mapping.
-+ */
++ bool ok, is_sdvo = false, is_dvo = false;
++ bool is_crt = false, is_lvds = false, is_tv = false;
++ struct drm_mode_config *mode_config = &dev->mode_config;
++ struct drm_connector *output;
+
-+ spinlock_t reloc_lock;
-+ unsigned int rel_mapped_pages;
-+ wait_queue_head_t rel_mapped_queue;
++ list_for_each_entry(output, &mode_config->connector_list, head) {
++ struct intel_output *intel_output = to_intel_output(crtc);
+
-+ /*
-+ * SAREA
-+ */
-+ struct drm_psb_sarea *sarea_priv;
++ if (output->crtc != crtc)
++ continue;
+
-+ /*
-+ * LVDS info
-+ */
-+ int backlight_duty_cycle; /* restore backlight to this value */
-+ bool panel_wants_dither;
-+ struct drm_display_mode *panel_fixed_mode;
++ switch (intel_output->type) {
++ case INTEL_OUTPUT_LVDS:
++ is_lvds = TRUE;
++ break;
++ case INTEL_OUTPUT_SDVO:
++ is_sdvo = TRUE;
++ break;
++ case INTEL_OUTPUT_DVO:
++ is_dvo = TRUE;
++ break;
++ case INTEL_OUTPUT_TVOUT:
++ is_tv = TRUE;
++ break;
++ case INTEL_OUTPUT_ANALOG:
++ is_crt = TRUE;
++ break;
++ }
++ if(is_lvds && ((lvds_reg_value[pipe] & LVDS_PORT_EN) == 0))
++ {
++ printk("%s: is_lvds but not the boot display, so return\n",
++ __FUNCTION__);
++ return;
++ }
++ output->funcs->prepare(output);
++ }
+
-+ /*
-+ * Register state
-+ */
-+ uint32_t saveDSPACNTR;
-+ uint32_t saveDSPBCNTR;
-+ uint32_t savePIPEACONF;
-+ uint32_t savePIPEBCONF;
-+ uint32_t savePIPEASRC;
-+ uint32_t savePIPEBSRC;
-+ uint32_t saveFPA0;
-+ uint32_t saveFPA1;
-+ uint32_t saveDPLL_A;
-+ uint32_t saveDPLL_A_MD;
-+ uint32_t saveHTOTAL_A;
-+ uint32_t saveHBLANK_A;
-+ uint32_t saveHSYNC_A;
-+ uint32_t saveVTOTAL_A;
-+ uint32_t saveVBLANK_A;
-+ uint32_t saveVSYNC_A;
-+ uint32_t saveDSPASTRIDE;
-+ uint32_t saveDSPASIZE;
-+ uint32_t saveDSPAPOS;
-+ uint32_t saveDSPABASE;
-+ uint32_t saveDSPASURF;
-+ uint32_t saveFPB0;
-+ uint32_t saveFPB1;
-+ uint32_t saveDPLL_B;
-+ uint32_t saveDPLL_B_MD;
-+ uint32_t saveHTOTAL_B;
-+ uint32_t saveHBLANK_B;
-+ uint32_t saveHSYNC_B;
-+ uint32_t saveVTOTAL_B;
-+ uint32_t saveVBLANK_B;
-+ uint32_t saveVSYNC_B;
-+ uint32_t saveDSPBSTRIDE;
-+ uint32_t saveDSPBSIZE;
-+ uint32_t saveDSPBPOS;
-+ uint32_t saveDSPBBASE;
-+ uint32_t saveDSPBSURF;
-+ uint32_t saveVCLK_DIVISOR_VGA0;
-+ uint32_t saveVCLK_DIVISOR_VGA1;
-+ uint32_t saveVCLK_POST_DIV;
-+ uint32_t saveVGACNTRL;
-+ uint32_t saveADPA;
-+ uint32_t saveLVDS;
-+ uint32_t saveDVOA;
-+ uint32_t saveDVOB;
-+ uint32_t saveDVOC;
-+ uint32_t savePP_ON;
-+ uint32_t savePP_OFF;
-+ uint32_t savePP_CONTROL;
-+ uint32_t savePP_CYCLE;
-+ uint32_t savePFIT_CONTROL;
-+ uint32_t savePaletteA[256];
-+ uint32_t savePaletteB[256];
-+ uint32_t saveBLC_PWM_CTL;
-+ uint32_t saveCLOCKGATING;
++ intel_crtc_prepare(crtc);
++ /* Disable the panel fitter if it was on our pipe */
++ if (intel_panel_fitter_pipe(dev) == pipe)
++ I915_WRITE(PFIT_CONTROL, 0);
+
++ if (dpll_reg_value[pipe] & DPLL_VCO_ENABLE) {
++ I915_WRITE(fp_reg, fp_reg_value[pipe]);
++ I915_WRITE(dpll_reg, dpll_reg_value[pipe]& ~DPLL_VCO_ENABLE);
++ I915_READ(dpll_reg);
++ udelay(150);
++ }
+
+ /*
-+ * USE code base register management.
-+ */
++ if(is_lvds)
++ I915_WRITE(LVDS, lvds_reg_value[pipe]);
++ */
++ if (is_lvds) {
++ I915_WRITE(LVDS, lvds_reg_value[pipe]);
++ I915_READ(LVDS);
++ }
+
-+ struct drm_reg_manager use_manager;
++ I915_WRITE(fp_reg, fp_reg_value[pipe]);
++ I915_WRITE(dpll_reg, dpll_reg_value[pipe]);
++ I915_READ(dpll_reg);
++ udelay(150);
++ //I915_WRITE(dpll_md_reg, dpll_md_reg_value[pipe]);
++ I915_WRITE(dpll_reg, dpll_reg_value[pipe]);
++ I915_READ(dpll_reg);
++ udelay(150);
++ I915_WRITE(htot_reg, htot_reg_value[pipe]);
++ I915_WRITE(hblank_reg, hblank_reg_value[pipe]);
++ I915_WRITE(hsync_reg, hsync_reg_value[pipe]);
++ I915_WRITE(vtot_reg, vtot_reg_value[pipe]);
++ I915_WRITE(vblank_reg, vblank_reg_value[pipe]);
++ I915_WRITE(vsync_reg, vsync_reg_value[pipe]);
++ I915_WRITE(dspstride_reg, dspstride_reg_value[pipe]);
++ I915_WRITE(dspsize_reg, dspsize_reg_value[pipe]);
++ I915_WRITE(dsppos_reg, dsppos_reg_value[pipe]);
++ I915_WRITE(pipesrc_reg, pipesrc_reg_value[pipe]);
++ I915_WRITE(pipeconf_reg, pipeconf_reg_value[pipe]);
++ I915_READ(pipeconf_reg);
++ intel_wait_for_vblank(dev);
++ I915_WRITE(dspcntr_reg, dspcntr_reg_value[pipe]);
++ I915_WRITE(dspbase, dspbase_value[pipe]);
++ I915_READ(dspbase);
++ I915_WRITE(VGACNTRL, vgacntrl_reg_value[pipe]);
++ intel_wait_for_vblank(dev);
++ I915_WRITE(PFIT_CONTROL, pfit_control_reg_value[pipe]);
+
-+ /*
-+ * Xhw
-+ */
++ intel_crtc_commit(crtc);
++ list_for_each_entry(output, &mode_config->connector_list, head) {
++ if (output->crtc != crtc)
++ continue;
+
-+ uint32_t *xhw;
-+ struct drm_buffer_object *xhw_bo;
-+ struct drm_bo_kmap_obj xhw_kmap;
-+ struct list_head xhw_in;
-+ spinlock_t xhw_lock;
-+ atomic_t xhw_client;
-+ struct drm_file *xhw_file;
-+ wait_queue_head_t xhw_queue;
-+ wait_queue_head_t xhw_caller_queue;
-+ struct mutex xhw_mutex;
-+ struct psb_xhw_buf *xhw_cur_buf;
-+ int xhw_submit_ok;
-+ int xhw_on;
++ output->funcs->commit(output);
++ //output->funcs->dpms(output, DRM_MODE_DPMS_OFF);
++ //printk("turn off the display first\n");
++ }
++ return;
++}
+
-+ /*
-+ * Scheduling.
-+ */
++void intel_crtc_mode_save(struct drm_crtc *crtc)
++{
++ struct drm_device *dev = crtc->dev;
++ DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
++ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
++ int pipe = intel_crtc->pipe;
++ int fp_reg = (pipe == 0) ? FPA0 : FPB0;
++ int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
++ int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
++ int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
++ int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
++ int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
++ int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
++ int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
++ int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
++ int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
++ int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
++ int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
++ int dspstride_reg = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
++ int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
++ int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
++ int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
++ bool ok, is_sdvo = false, is_dvo = false;
++ bool is_crt = false, is_lvds = false, is_tv = false;
++ struct drm_mode_config *mode_config = &dev->mode_config;
++ struct drm_connector *output;
+
-+ struct mutex reset_mutex;
-+ struct mutex cmdbuf_mutex;
-+ struct psb_scheduler scheduler;
-+ struct psb_buflist_item *buffers;
-+ uint32_t ta_mem_pages;
-+ struct psb_ta_mem *ta_mem;
-+ int force_ta_mem_load;
++ list_for_each_entry(output, &mode_config->connector_list, head) {
++ struct intel_output *intel_output = to_intel_output(crtc);
+
-+ /*
-+ * Watchdog
-+ */
++ if (output->crtc != crtc)
++ continue;
+
-+ spinlock_t watchdog_lock;
-+ struct timer_list watchdog_timer;
-+ struct work_struct watchdog_wq;
-+ struct work_struct msvdx_watchdog_wq;
-+ int timer_available;
++ switch (intel_output->type) {
++ case INTEL_OUTPUT_LVDS:
++ is_lvds = TRUE;
++ break;
++ case INTEL_OUTPUT_SDVO:
++ is_sdvo = TRUE;
++ break;
++ case INTEL_OUTPUT_DVO:
++ is_dvo = TRUE;
++ break;
++ case INTEL_OUTPUT_TVOUT:
++ is_tv = TRUE;
++ break;
++ case INTEL_OUTPUT_ANALOG:
++ is_crt = TRUE;
++ break;
++ }
++ }
+
-+ /*
-+ * msvdx command queue
-+ */
-+ spinlock_t msvdx_lock;
-+ struct mutex msvdx_mutex;
-+ struct list_head msvdx_queue;
-+ int msvdx_busy;
++ fp_reg_value[pipe] = I915_READ(fp_reg);
++ dpll_reg_value[pipe] = I915_READ(dpll_reg);
++ dpll_md_reg_value[pipe] = I915_READ(dpll_md_reg);
++ dspcntr_reg_value[pipe] = I915_READ(dspcntr_reg);
++ pipeconf_reg_value[pipe] = I915_READ(pipeconf_reg);
++ htot_reg_value[pipe] = I915_READ(htot_reg);
++ hblank_reg_value[pipe] = I915_READ(hblank_reg);
++ hsync_reg_value[pipe] = I915_READ(hsync_reg);
++ vtot_reg_value[pipe] = I915_READ(vtot_reg);
++ vblank_reg_value[pipe] = I915_READ(vblank_reg);
++ vsync_reg_value[pipe] = I915_READ(vsync_reg);
++ dspsize_reg_value[pipe] = I915_READ(dspsize_reg);
++ dspstride_reg_value[pipe] = I915_READ(dspstride_reg);
++ dsppos_reg_value[pipe] = I915_READ(dsppos_reg);
++ pipesrc_reg_value[pipe] = I915_READ(pipesrc_reg);
++ dspbase_value[pipe] = I915_READ(dspbase);
++ if(is_lvds)
++ lvds_reg_value[pipe] = I915_READ(LVDS);
++ vgacntrl_reg_value[pipe] = I915_READ(VGACNTRL);
++ pfit_control_reg_value[pipe] = I915_READ(PFIT_CONTROL);
++}
++#endif
++#endif
+ static void intel_crtc_mode_set(struct drm_crtc *crtc,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode,
+@@ -715,7 +860,7 @@
+ struct drm_framebuffer *old_fb)
+ {
+ struct drm_device *dev = crtc->dev;
+- struct drm_i915_private *dev_priv = dev->dev_private;
++ DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int pipe = intel_crtc->pipe;
+ int fp_reg = (pipe == 0) ? FPA0 : FPB0;
+@@ -730,6 +875,7 @@
+ int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
+ int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
+ int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
++ int dspstride_reg = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
+ int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
+ int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
+ int refclk;
+@@ -740,7 +886,10 @@
+ struct drm_mode_config *mode_config = &dev->mode_config;
+ struct drm_connector *connector;
+
+- drm_vblank_pre_modeset(dev, pipe);
++ if (!crtc->fb) {
++ DRM_ERROR("Can't set mode without attached fb\n");
++ return;
++ }
+
+ list_for_each_entry(connector, &mode_config->connector_list, head) {
+ struct intel_output *intel_output = to_intel_output(connector);
+@@ -784,13 +933,15 @@
+
+ dpll = DPLL_VGA_MODE_DIS;
+ if (IS_I9XX(dev)) {
+- if (is_lvds)
++ if (is_lvds) {
+ dpll |= DPLLB_MODE_LVDS;
+- else
++ if (IS_POULSBO(dev))
++ dpll |= DPLL_DVO_HIGH_SPEED;
++ } else
+ dpll |= DPLLB_MODE_DAC_SERIAL;
+ if (is_sdvo) {
+ dpll |= DPLL_DVO_HIGH_SPEED;
+- if (IS_I945G(dev) || IS_I945GM(dev)) {
++ if (IS_I945G(dev) || IS_I945GM(dev) || IS_POULSBO(dev)) {
+ int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
+ dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
+ }
+@@ -841,6 +992,25 @@
+ /* Set up the display plane register */
+ dspcntr = DISPPLANE_GAMMA_ENABLE;
+
++ switch (crtc->fb->bits_per_pixel) {
++ case 8:
++ dspcntr |= DISPPLANE_8BPP;
++ break;
++ case 16:
++ if (crtc->fb->depth == 15)
++ dspcntr |= DISPPLANE_15_16BPP;
++ else
++ dspcntr |= DISPPLANE_16BPP;
++ break;
++ case 32:
++ dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
++ break;
++ default:
++ DRM_ERROR("Unknown color depth\n");
++ return;
++ }
+
-+};
+
-Index: linux-2.6.28/drivers/gpu/drm/i915/i915_drv.h
-===================================================================
---- linux-2.6.28.orig/drivers/gpu/drm/i915/i915_drv.h 2009-02-12 09:47:51.000000000 +0000
-+++ linux-2.6.28/drivers/gpu/drm/i915/i915_drv.h 2009-02-11 21:23:41.000000000 +0000
-@@ -672,6 +672,7 @@
- LOCK_TEST_WITH_RETURN(dev, file_priv); \
- } while (0)
+ if (pipe == 0)
+ dspcntr |= DISPPLANE_SEL_PIPE_A;
+ else
+@@ -934,6 +1104,7 @@
+ ((adjusted_mode->crtc_vblank_end - 1) << 16));
+ I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
+ ((adjusted_mode->crtc_vsync_end - 1) << 16));
++ I915_WRITE(dspstride_reg, crtc->fb->pitch);
+ /* pipesrc and dspsize control the size that is scaled from, which should
+ * always be the user's requested size.
+ */
+@@ -950,14 +1121,14 @@
+ /* Flush the plane changes */
+ intel_pipe_set_base(crtc, x, y, old_fb);
-+#ifndef I915_READ
- #define I915_READ(reg) readl(dev_priv->regs + (reg))
- #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
- #define I915_READ16(reg) readw(dev_priv->regs + (reg))
-@@ -685,6 +686,7 @@
- writel(upper_32_bits(val), dev_priv->regs + \
- (reg) + 4))
- #endif
+- drm_vblank_post_modeset(dev, pipe);
++ intel_wait_for_vblank(dev);
+ }
+
+ /** Loads the palette/gamma unit for the CRTC with the prepared values */
+ void intel_crtc_load_lut(struct drm_crtc *crtc)
+ {
+ struct drm_device *dev = crtc->dev;
+- struct drm_i915_private *dev_priv = dev->dev_private;
++ DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
+ int i;
+@@ -980,7 +1151,7 @@
+ uint32_t width, uint32_t height)
+ {
+ struct drm_device *dev = crtc->dev;
+- struct drm_i915_private *dev_priv = dev->dev_private;
++ DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct drm_gem_object *bo;
+ struct drm_i915_gem_object *obj_priv;
+@@ -1019,7 +1190,7 @@
+ ret = -ENOMEM;
+ goto fail;
+ }
+-
++#if 0
+ /* we only need to pin inside GTT if cursor is non-phy */
+ if (!dev_priv->cursor_needs_physical) {
+ ret = i915_gem_object_pin(bo, PAGE_SIZE);
+@@ -1036,7 +1207,7 @@
+ }
+ addr = obj_priv->phys_obj->handle->busaddr;
+ }
+-
+#endif
- #define POSTING_READ(reg) (void)I915_READ(reg)
+ temp = 0;
+ /* set the pipe for the cursor */
+ temp |= (pipe << 28);
+@@ -1047,6 +1218,7 @@
+ I915_WRITE(base, addr);
- #define I915_VERBOSE 0
-@@ -776,10 +778,15 @@
- (dev)->pci_device == 0x29D2)
+ if (intel_crtc->cursor_bo) {
++#if 0
+ if (dev_priv->cursor_needs_physical) {
+ if (intel_crtc->cursor_bo != bo)
+ i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
+@@ -1055,6 +1227,7 @@
+ mutex_lock(&dev->struct_mutex);
+ drm_gem_object_unreference(intel_crtc->cursor_bo);
+ mutex_unlock(&dev->struct_mutex);
++#endif
+ }
- #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
-- IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
-+ IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
-+ IS_POULSBO(dev))
-+
-+#define IS_POULSBO(dev) (((dev)->pci_device == 0x8108) || \
-+ ((dev)->pci_device == 0x8109))
+ intel_crtc->cursor_addr = addr;
+@@ -1071,7 +1244,7 @@
+ static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
+ {
+ struct drm_device *dev = crtc->dev;
+- struct drm_i915_private *dev_priv = dev->dev_private;
++ DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int pipe = intel_crtc->pipe;
+ uint32_t temp = 0;
+@@ -1255,7 +1428,7 @@
+ /* Returns the clock of the currently programmed mode of the given pipe. */
+ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
+ {
+- struct drm_i915_private *dev_priv = dev->dev_private;
++ DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int pipe = intel_crtc->pipe;
+ u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
+@@ -1333,7 +1506,7 @@
+ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
+ struct drm_crtc *crtc)
+ {
+- struct drm_i915_private *dev_priv = dev->dev_private;
++ DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int pipe = intel_crtc->pipe;
+ struct drm_display_mode *mode;
+@@ -1399,7 +1572,6 @@
- #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
-- IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev))
-+ IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
-+ IS_POULSBO(dev))
+ drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
- #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev))
- #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev))
+- drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
+ intel_crtc->pipe = pipe;
+ for (i = 0; i < 256; i++) {
+ intel_crtc->lut_r[i] = i;
+@@ -1415,11 +1587,6 @@
+ intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1);
+ intel_crtc->mode_set.num_connectors = 0;
+
+- if (i915_fbpercrtc) {
+-
+-
+-
+- }
+ }
+
+ struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
+@@ -1454,27 +1621,17 @@
+ {
+ struct drm_connector *connector;
+
+- intel_crt_init(dev);
++ if (!IS_POULSBO(dev))
++ intel_crt_init(dev);
+
+ /* Set up integrated LVDS */
+ if (IS_MOBILE(dev) && !IS_I830(dev))
+ intel_lvds_init(dev);
+
+ if (IS_I9XX(dev)) {
+- int found;
+-
+- found = intel_sdvo_init(dev, SDVOB);
+- if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
+- intel_hdmi_init(dev, SDVOB);
+-
+- found = intel_sdvo_init(dev, SDVOC);
+- if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
+- intel_hdmi_init(dev, SDVOC);
+- } else
+- intel_dvo_init(dev);
+-
+- if (IS_I9XX(dev) && IS_MOBILE(dev))
+- intel_tv_init(dev);
++ intel_sdvo_init(dev, SDVOB);
++ intel_sdvo_init(dev, SDVOC);
++ }
+
+ list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+ struct intel_output *intel_output = to_intel_output(connector);
+@@ -1523,8 +1680,8 @@
+ struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+ struct drm_device *dev = fb->dev;
+
+- if (fb->fbdev)
+- intelfb_remove(dev, fb);
++ //if (fb->fbdev)
++ // intelfb_remove(dev, fb);
+
+ drm_framebuffer_cleanup(fb);
+ mutex_lock(&dev->struct_mutex);
+@@ -1601,7 +1758,7 @@
+
+ static const struct drm_mode_config_funcs intel_mode_funcs = {
+ .fb_create = intel_user_framebuffer_create,
+- .fb_changed = intelfb_probe,
++// .fb_changed = intelfb_probe,
+ };
+
+ void intel_modeset_init(struct drm_device *dev)
+@@ -1616,13 +1773,8 @@
+
+ dev->mode_config.funcs = (void *)&intel_mode_funcs;
+
+- if (IS_I965G(dev)) {
+- dev->mode_config.max_width = 8192;
+- dev->mode_config.max_height = 8192;
+- } else {
+- dev->mode_config.max_width = 2048;
+- dev->mode_config.max_height = 2048;
+- }
++ dev->mode_config.max_width = 2048;
++ dev->mode_config.max_height = 2048;
+
+ /* set memory base */
+ if (IS_I9XX(dev))
