# Third digit in PV should be incremented after a minor release
-PV = "4.9.1"
+PV = "4.9.2"
# BINV should be incremented to a revision after a minor gcc release
-BINV = "4.9.1"
+BINV = "4.9.2"
FILESEXTRAPATHS =. "${FILE_DIRNAME}/gcc-4.9:"
file://0049-Enable-SPE-AltiVec-generation-on-powepc-linux-target.patch \
file://0050-Revert-Use-dbx_reg_number-for-spanning-registers.patch \
file://0051-eabispe.patch \
+ file://0052-Add-target-hook-to-override-DWARF2-frame-register-si.patch \
file://0053-gcc-fix-segfault-from-calling-free-on-non-malloc-d-a.patch \
file://0054-gcc-Makefile.in-fix-parallel-building-failure.patch \
- file://0055-PR-rtl-optimization-61801.patch \
- file://0056-top-level-reorder_gcc-bug-61144.patch \
+ file://0055-dwarf-reg-processing-helper.patch \
+ file://0056-define-default-cfa-register-mapping.patch \
file://0057-aarch64-config.patch \
file://0058-gcc-r212171.patch \
file://0059-gcc-PR-rtl-optimization-63348.patch \
- file://target-gcc-includedir.patch \
+ file://0060-Only-allow-e500-double-in-SPE_SIMD_REGNO_P-registers.patch \
+ file://0061-target-gcc-includedir.patch \
"
-SRC_URI[md5sum] = "fddf71348546af523353bd43d34919c1"
-SRC_URI[sha256sum] = "d334781a124ada6f38e63b545e2a3b8c2183049515a1abab6d513f109f1d717e"
+SRC_URI[md5sum] = "4df8ee253b7f3863ad0b86359cd39c43"
+SRC_URI[sha256sum] = "2020c98295856aa13fda0f2f3a4794490757fc24bcca918d52cc8b4917b972dd"
S = "${TMPDIR}/work-shared/gcc-${PV}-${PR}/gcc-${PV}"
B = "${WORKDIR}/gcc-${PV}/build.${HOST_SYS}.${TARGET_SYS}"
EXTRA_OECONF_append_libc-uclibc = " --disable-decimal-float "
-EXTRA_OECONF_PATHS = "\
- --with-gxx-include-dir=/not/exist{target_includedir}/c++/${BINV} \
- --with-sysroot=/not/exist \
+EXTRA_OECONF_PATHS = "\
+ --with-gxx-include-dir=/not/exist{target_includedir}/c++/${BINV} \
+ --with-sysroot=/not/exist \
--with-build-sysroot=${STAGING_DIR_TARGET} \
"
-
-
--- /dev/null
+From d626297e87e19251a284ea1e9360e831b48999ca Mon Sep 17 00:00:00 2001
+From: mpf <mpf@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Thu, 4 Sep 2014 08:32:05 +0000
+Subject: [PATCH] Add target hook to override DWARF2 frame register size
+
+gcc/
+
+ * target.def (TARGET_DWARF_FRAME_REG_MODE): New target hook.
+ * targhooks.c (default_dwarf_frame_reg_mode): New function.
+ * targhooks.h (default_dwarf_frame_reg_mode): New prototype.
+ * doc/tm.texi.in (TARGET_DWARF_FRAME_REG_MODE): Document.
+ * doc/tm.texi: Regenerate.
+ * dwarf2cfi.c (expand_builtin_init_dwarf_reg_sizes): Abstract mode
+ selection logic to default_dwarf_frame_reg_mode.
+
+
+
+git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@214898 138bc75d-0d04-0410-961f-82ee72b054a4
+
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+Upstream-Status: Backport [gcc 5.0]
+
+---
+ gcc/ChangeLog | 10 ++++++++++
+ gcc/doc/tm.texi | 7 +++++++
+ gcc/doc/tm.texi.in | 2 ++
+ gcc/dwarf2cfi.c | 4 +---
+ gcc/target.def | 11 +++++++++++
+ gcc/targhooks.c | 13 +++++++++++++
+ gcc/targhooks.h | 1 +
+ 7 files changed, 45 insertions(+), 3 deletions(-)
+
+Index: gcc-4.9.2/gcc/doc/tm.texi
+===================================================================
+--- gcc-4.9.2.orig/gcc/doc/tm.texi
++++ gcc-4.9.2/gcc/doc/tm.texi
+@@ -9017,6 +9017,13 @@ register in Dwarf. Otherwise, this hook
+ If not defined, the default is to return @code{NULL_RTX}.
+ @end deftypefn
+
++@deftypefn {Target Hook} {enum machine_mode} TARGET_DWARF_FRAME_REG_MODE (int @var{regno})
++Given a register, this hook should return the mode which the
++corresponding Dwarf frame register should have. This is normally
++used to return a smaller mode than the raw mode to prevent call
++clobbered parts of a register altering the frame register size
++@end deftypefn
++
+ @deftypefn {Target Hook} void TARGET_INIT_DWARF_REG_SIZES_EXTRA (tree @var{address})
+ If some registers are represented in Dwarf-2 unwind information in
+ multiple pieces, define this hook to fill in information about the
+Index: gcc-4.9.2/gcc/doc/tm.texi.in
+===================================================================
+--- gcc-4.9.2.orig/gcc/doc/tm.texi.in
++++ gcc-4.9.2/gcc/doc/tm.texi.in
+@@ -6745,6 +6745,8 @@ the target supports DWARF 2 frame unwind
+
+ @hook TARGET_DWARF_REGISTER_SPAN
+
++@hook TARGET_DWARF_FRAME_REG_MODE
++
+ @hook TARGET_INIT_DWARF_REG_SIZES_EXTRA
+
+ @hook TARGET_ASM_TTYPE
+Index: gcc-4.9.2/gcc/dwarf2cfi.c
+===================================================================
+--- gcc-4.9.2.orig/gcc/dwarf2cfi.c
++++ gcc-4.9.2/gcc/dwarf2cfi.c
+@@ -271,11 +271,9 @@ expand_builtin_init_dwarf_reg_sizes (tre
+ if (rnum < DWARF_FRAME_REGISTERS)
+ {
+ HOST_WIDE_INT offset = rnum * GET_MODE_SIZE (mode);
+- enum machine_mode save_mode = reg_raw_mode[i];
+ HOST_WIDE_INT size;
++ enum machine_mode save_mode = targetm.dwarf_frame_reg_mode (i);
+
+- if (HARD_REGNO_CALL_PART_CLOBBERED (i, save_mode))
+- save_mode = choose_hard_reg_mode (i, 1, true);
+ if (dnum == DWARF_FRAME_RETURN_COLUMN)
+ {
+ if (save_mode == VOIDmode)
+Index: gcc-4.9.2/gcc/target.def
+===================================================================
+--- gcc-4.9.2.orig/gcc/target.def
++++ gcc-4.9.2/gcc/target.def
+@@ -3218,6 +3218,17 @@ If not defined, the default is to return
+ rtx, (rtx reg),
+ hook_rtx_rtx_null)
+
++/* Given a register return the mode of the corresponding DWARF frame
++ register. */
++DEFHOOK
++(dwarf_frame_reg_mode,
++ "Given a register, this hook should return the mode which the\n\
++corresponding Dwarf frame register should have. This is normally\n\
++used to return a smaller mode than the raw mode to prevent call\n\
++clobbered parts of a register altering the frame register size",
++ enum machine_mode, (int regno),
++ default_dwarf_frame_reg_mode)
++
+ /* If expand_builtin_init_dwarf_reg_sizes needs to fill in table
+ entries not corresponding directly to registers below
+ FIRST_PSEUDO_REGISTER, this hook should generate the necessary
+Index: gcc-4.9.2/gcc/targhooks.c
+===================================================================
+--- gcc-4.9.2.orig/gcc/targhooks.c
++++ gcc-4.9.2/gcc/targhooks.c
+@@ -1438,6 +1438,19 @@ default_debug_unwind_info (void)
+ return UI_NONE;
+ }
+
++/* Determine the correct mode for a Dwarf frame register that represents
++ register REGNO. */
++
++enum machine_mode
++default_dwarf_frame_reg_mode (int regno)
++{
++ enum machine_mode save_mode = reg_raw_mode[regno];
++
++ if (HARD_REGNO_CALL_PART_CLOBBERED (regno, save_mode))
++ save_mode = choose_hard_reg_mode (regno, 1, true);
++ return save_mode;
++}
++
+ /* To be used by targets where reg_raw_mode doesn't return the right
+ mode for registers used in apply_builtin_return and apply_builtin_arg. */
+
+Index: gcc-4.9.2/gcc/targhooks.h
+===================================================================
+--- gcc-4.9.2.orig/gcc/targhooks.h
++++ gcc-4.9.2/gcc/targhooks.h
+@@ -194,6 +194,7 @@ extern int default_label_align_max_skip
+ extern int default_jump_align_max_skip (rtx);
+ extern section * default_function_section(tree decl, enum node_frequency freq,
+ bool startup, bool exit);
++extern enum machine_mode default_dwarf_frame_reg_mode (int);
+ extern enum machine_mode default_get_reg_raw_mode (int);
+
+ extern void *default_get_pch_validity (size_t *);
+++ /dev/null
-From 556537c4ad0df4cbebb74197bb2bdea75cf5dd35 Mon Sep 17 00:00:00 2001
-From: rguenth <rguenth@138bc75d-0d04-0410-961f-82ee72b054a4>
-Date: Thu, 17 Jul 2014 07:48:49 +0000
-Subject: [PATCH] 2014-07-17 Richard Biener <rguenther@suse.de>
-
- PR rtl-optimization/61801
- * sched-deps.c (sched_analyze_2): For ASM_OPERANDS and
- ASM_INPUT don't set reg_pending_barrier if it appears in a
- debug-insn.
-
-
-git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@212739 138bc75d-0d04-0410-961f-82ee72b054a4
-
-Upstream-Status: Backport [https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61801]
-Signed-off-by: Peter A. Bigot <pab@pabigot.com>
-
----
- gcc/sched-deps.c | 3 ++-
-
-diff --git a/gcc/sched-deps.c b/gcc/sched-deps.c
-index efc4223..df29bd3 100644
---- a/gcc/sched-deps.c
-+++ b/gcc/sched-deps.c
-@@ -2750,7 +2750,8 @@ sched_analyze_2 (struct deps_desc *deps, rtx x, rtx insn)
- Consider for instance a volatile asm that changes the fpu rounding
- mode. An insn should not be moved across this even if it only uses
- pseudo-regs because it might give an incorrectly rounded result. */
-- if (code != ASM_OPERANDS || MEM_VOLATILE_P (x))
-+ if ((code != ASM_OPERANDS || MEM_VOLATILE_P (x))
-+ && !DEBUG_INSN_P (insn))
- reg_pending_barrier = TRUE_BARRIER;
-
- /* For all ASM_OPERANDS, we must traverse the vector of input operands.
---
-1.8.5.5
-
--- /dev/null
+From 4fd39f1329379e00f958394adde6be96f0caf21f Mon Sep 17 00:00:00 2001
+From: hainque <hainque@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Fri, 5 Dec 2014 16:53:22 +0000
+Subject: [PATCH] 2014-12-05 Olivier Hainque <hainque@adacore.com>
+
+ * dwarf2cfi.c (init_one_dwarf_reg_size): New helper, processing
+ one particular reg for expand_builtin_init_dwarf_reg_sizes.
+ (expand_builtin_init_dwarf_reg_sizes): Rework to use helper and
+ account for dwarf register spans.
+
+
+
+git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218428 138bc75d-0d04-0410-961f-82ee72b054a4
+
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+Upstream-Status: Backport [gcc 5.0]
+
+---
+ gcc/ChangeLog | 7 +++++
+ gcc/dwarf2cfi.c | 98 +++++++++++++++++++++++++++++++++++++++++++++------------
+ 2 files changed, 85 insertions(+), 20 deletions(-)
+
+Index: gcc-4.9.2/gcc/dwarf2cfi.c
+===================================================================
+--- gcc-4.9.2.orig/gcc/dwarf2cfi.c
++++ gcc-4.9.2/gcc/dwarf2cfi.c
+@@ -252,7 +252,59 @@ init_return_column_size (enum machine_mo
+ gen_int_mode (size, mode));
+ }
+
+-/* Generate code to initialize the register size table. */
++/* Datastructure used by expand_builtin_init_dwarf_reg_sizes and
++ init_one_dwarf_reg_size to communicate on what has been done by the
++ latter. */
++
++typedef struct
++{
++ /* Whether the dwarf return column was initialized. */
++ bool wrote_return_column;
++
++ /* For each hard register REGNO, whether init_one_dwarf_reg_size
++ was given REGNO to process already. */
++ bool processed_regno [FIRST_PSEUDO_REGISTER];
++
++} init_one_dwarf_reg_state;
++
++/* Helper for expand_builtin_init_dwarf_reg_sizes. Generate code to
++ initialize the dwarf register size table entry corresponding to register
++ REGNO in REGMODE. TABLE is the table base address, SLOTMODE is the mode to
++ use for the size entry to initialize, and INIT_STATE is the communication
++ datastructure conveying what we're doing to our caller. */
++
++static
++void init_one_dwarf_reg_size (int regno, machine_mode regmode,
++ rtx table, machine_mode slotmode,
++ init_one_dwarf_reg_state *init_state)
++{
++ const unsigned int dnum = DWARF_FRAME_REGNUM (regno);
++ const unsigned int rnum = DWARF2_FRAME_REG_OUT (dnum, 1);
++
++ const HOST_WIDE_INT slotoffset = rnum * GET_MODE_SIZE (slotmode);
++ const HOST_WIDE_INT regsize = GET_MODE_SIZE (regmode);
++
++ init_state->processed_regno[regno] = true;
++
++ if (rnum >= DWARF_FRAME_REGISTERS)
++ return;
++
++ if (dnum == DWARF_FRAME_RETURN_COLUMN)
++ {
++ if (regmode == VOIDmode)
++ return;
++ init_state->wrote_return_column = true;
++ }
++
++ if (slotoffset < 0)
++ return;
++
++ emit_move_insn (adjust_address (table, slotmode, slotoffset),
++ gen_int_mode (regsize, slotmode));
++}
++
++/* Generate code to initialize the dwarf register size table located
++ at the provided ADDRESS. */
+
+ void
+ expand_builtin_init_dwarf_reg_sizes (tree address)
+@@ -261,35 +313,40 @@ expand_builtin_init_dwarf_reg_sizes (tre
+ enum machine_mode mode = TYPE_MODE (char_type_node);
+ rtx addr = expand_normal (address);
+ rtx mem = gen_rtx_MEM (BLKmode, addr);
+- bool wrote_return_column = false;
++
++ init_one_dwarf_reg_state init_state;
++
++ memset ((char *)&init_state, 0, sizeof (init_state));
+
+ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+ {
+- unsigned int dnum = DWARF_FRAME_REGNUM (i);
+- unsigned int rnum = DWARF2_FRAME_REG_OUT (dnum, 1);
+-
+- if (rnum < DWARF_FRAME_REGISTERS)
+- {
+- HOST_WIDE_INT offset = rnum * GET_MODE_SIZE (mode);
+- HOST_WIDE_INT size;
+- enum machine_mode save_mode = targetm.dwarf_frame_reg_mode (i);
++ machine_mode save_mode;
++ rtx span;
+
+- if (dnum == DWARF_FRAME_RETURN_COLUMN)
++ /* No point in processing a register multiple times. This could happen
++ with register spans, e.g. when a reg is first processed as a piece of
++ a span, then as a register on its own later on. */
++
++ if (init_state.processed_regno[i])
++ continue;
++
++ save_mode = targetm.dwarf_frame_reg_mode (i);
++ span = targetm.dwarf_register_span (gen_rtx_REG (save_mode, i));
++ if (!span)
++ init_one_dwarf_reg_size (i, save_mode, mem, mode, &init_state);
++ else
++ {
++ for (int si = 0; si < XVECLEN (span, 0); si++)
+ {
+- if (save_mode == VOIDmode)
+- continue;
+- wrote_return_column = true;
+- }
+- size = GET_MODE_SIZE (save_mode);
+- if (offset < 0)
+- continue;
++ rtx reg = XVECEXP (span, 0, si);
++ init_one_dwarf_reg_size
++ (REGNO (reg), GET_MODE (reg), mem, mode, &init_state);
++ }
+
+- emit_move_insn (adjust_address (mem, mode, offset),
+- gen_int_mode (size, mode));
+ }
+ }
+
+- if (!wrote_return_column)
++ if (!init_state.wrote_return_column)
+ init_return_column_size (mode, mem, DWARF_FRAME_RETURN_COLUMN);
+
+ #ifdef DWARF_ALT_FRAME_RETURN_COLUMN
--- /dev/null
+From c0235a33de8c4f78cce35b2a8c2035c83fe1bd14 Mon Sep 17 00:00:00 2001
+From: hainque <hainque@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Fri, 5 Dec 2014 17:01:42 +0000
+Subject: [PATCH] 2014-12-05 Olivier Hainque <hainque@adacore.com>
+
+ gcc/
+ * defaults.h: (DWARF_REG_TO_UNWIND_COLUMN): Define default.
+ * dwarf2cfi.c (init_one_dwarf_reg_size): Honor
+ DWARF_REG_TO_UNWIND_COLUMN.
+
+ libgcc/
+ * unwind-dw2.c (DWARF_REG_TO_UNWIND_COLUMN): Remove default def,
+ now provided by defaults.h.
+
+
+
+git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218429 138bc75d-0d04-0410-961f-82ee72b054a4
+
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+Upstream-Status: Backport [gcc 5.0]
+
+---
+ gcc/ChangeLog | 6 ++++++
+ gcc/defaults.h | 5 +++++
+ gcc/dwarf2cfi.c | 3 ++-
+ libgcc/ChangeLog | 5 +++++
+ libgcc/unwind-dw2.c | 4 ----
+ 5 files changed, 18 insertions(+), 5 deletions(-)
+
+Index: gcc-4.9.2/gcc/defaults.h
+===================================================================
+--- gcc-4.9.2.orig/gcc/defaults.h
++++ gcc-4.9.2/gcc/defaults.h
+@@ -438,6 +438,11 @@ see the files COPYING3 and COPYING.RUNTI
+ #define DWARF_FRAME_REGNUM(REG) DBX_REGISTER_NUMBER (REG)
+ #endif
+
++/* The mapping from dwarf CFA reg number to internal dwarf reg numbers. */
++#ifndef DWARF_REG_TO_UNWIND_COLUMN
++#define DWARF_REG_TO_UNWIND_COLUMN(REGNO) (REGNO)
++#endif
++
+ /* Map register numbers held in the call frame info that gcc has
+ collected using DWARF_FRAME_REGNUM to those that should be output in
+ .debug_frame and .eh_frame. */
+Index: gcc-4.9.2/gcc/dwarf2cfi.c
+===================================================================
+--- gcc-4.9.2.orig/gcc/dwarf2cfi.c
++++ gcc-4.9.2/gcc/dwarf2cfi.c
+@@ -280,8 +280,9 @@ void init_one_dwarf_reg_size (int regno,
+ {
+ const unsigned int dnum = DWARF_FRAME_REGNUM (regno);
+ const unsigned int rnum = DWARF2_FRAME_REG_OUT (dnum, 1);
++ const unsigned int dcol = DWARF_REG_TO_UNWIND_COLUMN (rnum);
+
+- const HOST_WIDE_INT slotoffset = rnum * GET_MODE_SIZE (slotmode);
++ const HOST_WIDE_INT slotoffset = dcol * GET_MODE_SIZE (slotmode);
+ const HOST_WIDE_INT regsize = GET_MODE_SIZE (regmode);
+
+ init_state->processed_regno[regno] = true;
+Index: gcc-4.9.2/libgcc/unwind-dw2.c
+===================================================================
+--- gcc-4.9.2.orig/libgcc/unwind-dw2.c
++++ gcc-4.9.2/libgcc/unwind-dw2.c
+@@ -55,10 +55,6 @@
+ #define PRE_GCC3_DWARF_FRAME_REGISTERS DWARF_FRAME_REGISTERS
+ #endif
+
+-#ifndef DWARF_REG_TO_UNWIND_COLUMN
+-#define DWARF_REG_TO_UNWIND_COLUMN(REGNO) (REGNO)
+-#endif
+-
+ /* ??? For the public function interfaces, we tend to gcc_assert that the
+ column numbers are in range. For the dwarf2 unwind info this does happen,
+ although so far in a case that doesn't actually matter.
+++ /dev/null
-
-Upstream-Status: Backport
-
-Originally-submitted-by: Peter Urbanec <openembedded-devel@urbanec.net>
-Signed-off-by: Saul Wold <sgw@linux.intel.com>
-
---- /dev/null
-+++ b/meta/recipes-devtools/gcc/gcc-4.9/0056-top-level-reorder_gcc-bug-61144.patch
-@@ -0,0 +1,21 @@
-+--- a/gcc/varpool.c 2014/10/05 02:50:01 215895
-++++ b/gcc/varpool.c 2014/10/05 04:52:19 215896
-+@@ -329,8 +329,16 @@
-+
-+ /* Variables declared 'const' without an initializer
-+ have zero as the initializer if they may not be
-+- overridden at link or run time. */
-+- if (!DECL_INITIAL (real_decl)
-++ overridden at link or run time.
-++
-++ It is actually requirement for C++ compiler to optimize const variables
-++ consistently. As a GNU extension, do not enfore this rule for user defined
-++ weak variables, so we support interposition on:
-++ static const int dummy = 0;
-++ extern const int foo __attribute__((__weak__, __alias__("dummy")));
-++ */
-++ if ((!DECL_INITIAL (real_decl)
-++ || (DECL_WEAK (decl) && !DECL_COMDAT (decl)))
-+ && (DECL_EXTERNAL (decl) || decl_replaceable_p (decl)))
-+ return error_mark_node;
-+
-
--- /dev/null
+From 5c0092070253113cf0d9c45eacc884b3ecc34d81 Mon Sep 17 00:00:00 2001
+From: jsm28 <jsm28@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Sat, 25 Oct 2014 00:23:17 +0000
+Subject: [PATCH] Only allow e500 double in SPE_SIMD_REGNO_P registers.
+
+rs6000_hard_regno_nregs_internal allows SPE vectors in single
+registers satisfying SPE_SIMD_REGNO_P (i.e. register numbers 0 to
+31). However, the corresponding test for e500 double treats all
+registers as being able to store a 64-bit value, rather than just
+those GPRs.
+
+Logically this inconsistency is wrong; in addition, it causes problems
+unwinding from signal handlers. linux-unwind.h uses
+ARG_POINTER_REGNUM as a place to store the return address from a
+signal handler, but this logic in rs6000_hard_regno_nregs_internal
+results in that being considered an 8-byte register, resulting in
+assertion failures.
+(<https://gcc.gnu.org/ml/gcc-patches/2014-09/msg02625.html> first
+needs to be applied for unwinding to work in general on e500.) This
+patch makes rs6000_hard_regno_nregs_internal handle the e500 double
+case consistently with SPE vectors.
+
+Tested with no regressions with cross to powerpc-linux-gnuspe (given
+the aforementioned patch applied). Failures of signal handling
+unwinding tests such as gcc.dg/cleanup-{8,9,10,11}.c are fixed by this
+patch.
+
+ * config/rs6000/rs6000.c (rs6000_hard_regno_nregs_internal): Do
+ not allow e500 double in registers not satisyfing
+ SPE_SIMD_REGNO_P.
+
+
+git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@216688 138bc75d-0d04-0410-961f-82ee72b054a4
+
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+Upstream-Status: Backport [gcc 5.0]
+
+---
+ gcc/ChangeLog | 6 ++++++
+ gcc/config/rs6000/rs6000.c | 2 +-
+ 2 files changed, 7 insertions(+), 1 deletion(-)
+
+Index: gcc-4.9.2/gcc/config/rs6000/rs6000.c
+===================================================================
+--- gcc-4.9.2.orig/gcc/config/rs6000/rs6000.c
++++ gcc-4.9.2/gcc/config/rs6000/rs6000.c
+@@ -1703,7 +1703,7 @@ rs6000_hard_regno_nregs_internal (int re
+ SCmode so as to pass the value correctly in a pair of
+ registers. */
+ else if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode
+- && !DECIMAL_FLOAT_MODE_P (mode))
++ && !DECIMAL_FLOAT_MODE_P (mode) && SPE_SIMD_REGNO_P (regno))
+ reg_size = UNITS_PER_FP_WORD;
+
+ else
