]> code.ossystems Code Review - openembedded-core.git/commitdiff
runqemu: Add riscv support for qemu machines
authorKhem Raj <raj.khem@gmail.com>
Fri, 6 Oct 2017 00:50:44 +0000 (17:50 -0700)
committerRichard Purdie <richard.purdie@linuxfoundation.org>
Sun, 5 Nov 2017 13:44:55 +0000 (13:44 +0000)
Signed-off-by: Khem Raj <raj.khem@gmail.com>
Signed-off-by: Ross Burton <ross.burton@intel.com>
scripts/runqemu

index df76270904359bc157098ab295c51aaea0c7c65c..9dc6a05c57f9b35a36857e2d8955a6e4f72f6fe1 100755 (executable)
@@ -1077,6 +1077,10 @@ class BaseConfig(object):
             qbsys = 'mipsel'
         elif mach == 'qemumips64el':
             qbsys = 'mips64el'
+        elif mach == 'qemuriscv64':
+            qbsys = 'riscv64'
+        elif mach == 'qemuriscv32':
+            qbsys = 'riscv32'
 
         return 'qemu-system-%s' % qbsys