]> code.ossystems Code Review - openembedded-core.git/commitdiff
go: Disable PIE on RISCV
authorKhem Raj <raj.khem@gmail.com>
Sun, 26 Jan 2020 19:27:50 +0000 (11:27 -0800)
committerRichard Purdie <richard.purdie@linuxfoundation.org>
Mon, 27 Jan 2020 16:38:54 +0000 (16:38 +0000)
Its not supported yet

Signed-off-by: Khem Raj <raj.khem@gmail.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
meta/recipes-devtools/go/go_1.13.bb

index 483e2e2cb79ab0bb90c140bffa9d854fe16e8ab2..5d40cf9d048b460137d5c5d9255ac37b29cbcd1e 100644 (file)
@@ -3,11 +3,11 @@ require go-target.inc
 
 export GOBUILDMODE=""
 
-# Add pie to GOBUILDMODE to satisfy "textrel" QA checking, but mips
-# doesn't support -buildmode=pie, so skip the QA checking for mips and its
+# Add pie to GOBUILDMODE to satisfy "textrel" QA checking, but mips/riscv
+# doesn't support -buildmode=pie, so skip the QA checking for mips/riscv and its
 # variants.
 python() {
-    if 'mips' in d.getVar('TARGET_ARCH',True):
+    if 'mips' in d.getVar('TARGET_ARCH',True) or 'riscv' in d.getVar('TARGET_ARCH',True):
         d.appendVar('INSANE_SKIP_%s' % d.getVar('PN',True), " textrel")
     else:
         d.setVar('GOBUILDMODE', 'pie')