perf: Disable FPU tune for i.MX5 SoCs to workaround GCC ICE

GCC 4.8 currently ICE when building perf for i.MX5 SoCs and we can
workaround it disabling the FPU tunning for it. This is a temporary
solution until GCC fixes this in an upcoming release.

GCC bugzilla: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57748

Change-Id: I5a23e6b57695a90e9750f0fa28c419b260c83be2
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>

diff --git a/meta-fsl-arm/recipes-kernel/perf/perf.bbappend b/meta-fsl-arm/recipes-kernel/perf/perf.bbappend
new file mode 100644 (file)
index 0000000..604e2b4
--- /dev/null
+++ b/meta-fsl-arm/recipes-kernel/perf/perf.bbappend
@@ -0,0 +1,3 @@
+# FIXME: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57748
+TUNE_CCARGS_mx5 := "${@oe_filter_out('-mfpu=neon', '${TUNE_CCARGS}', d)}"
+