From: Otavio Salvador Date: Thu, 29 Oct 2015 21:53:57 +0000 (-0200) Subject: cgtqmx6eval: Fix SPL support X-Git-Url: https://code.ossystems.io/gitweb?a=commitdiff_plain;h=42387867d9ab1ffc7cd5b92a65baff7983bc45f3;p=bsp%2Fu-boot.git cgtqmx6eval: Fix SPL support The patchset had some changes for approval on the U-Boot. Basically: - Add missing CONFIG_BOARD_LATE_INIT - Fix checkpatch error This patch integrate those changes on this forked version. Signed-off-by: Otavio Salvador --- diff --git a/board/congatec/cgtqmx6eval/README b/board/congatec/cgtqmx6eval/README index b339cd0f5b..1d736dc351 100644 --- a/board/congatec/cgtqmx6eval/README +++ b/board/congatec/cgtqmx6eval/README @@ -25,13 +25,13 @@ host PC (/tftpboot , for example). => sf probe -=> tftp SPL +=> tftp 0x12000000 SPL => sf erase 0x0 0x10000 -=> sf write 0x12000000 0x400 0x10000 +=> sf write 0x12000000 0x400 0x100 -=> tftp u-boot.img +=> tftp 0x12000000 u-boot.img => sf erase 0x10000 0x70000 diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c index 6057da6708..e7624209e8 100644 --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c @@ -985,8 +985,7 @@ static void conv_ascii(unsigned char *dst, unsigned char *src, int len) unsigned char *sptr = src; unsigned char *dptr = dst; - while (remain) - { + while (remain) { if (*sptr) { *dptr = *sptr; dptr++; @@ -1016,8 +1015,7 @@ static bool is_2gb(void) /* Congatec Part Numbers 104 and 105 have 2GiB of RAM */ conv_ascii(outbuf, data->pn, sizeof(data->pn)); - if (!strcmp((const char *)outbuf, "016104") || - !strcmp((const char *)outbuf, "016105")) + if (!memcmp(outbuf, "016104", 6) || !memcmp(outbuf, "016105", 6)) return true; else return false; @@ -1053,11 +1051,11 @@ static void spl_dram_init(int width) mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs); mx6_dram_cfg(&sysinfo, &mx6q_mmcd_calib, &mem_ddr_2g); } else if (is_cpu_type(MXC_CPU_MX6SOLO)) { - sysinfo.walat = 1; // add additional write latency for Solo and DualLite + sysinfo.walat = 1; mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs); mx6_dram_cfg(&sysinfo, &mx6s_mmcd_calib, &mem_ddr_4g); } else if (is_cpu_type(MXC_CPU_MX6DL)) { - sysinfo.walat = 1; // add additional write latency for Solo and DualLite + sysinfo.walat = 1; mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs); mx6_dram_cfg(&sysinfo, &mx6dl_mmcd_calib, &mem_ddr_2g); } diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index c7131f155b..487c011cc2 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -31,6 +31,7 @@ #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT #define CONFIG_MISC_INIT_R #define CONFIG_MXC_UART