From: Khem Raj <raj.khem@gmail.com>
Date: Fri, 6 Oct 2017 00:50:40 +0000 (-0700)
Subject: site: Add riscv32 and riscv64
X-Git-Tag: uninative-1.8~1325
X-Git-Url: https://code.ossystems.io/gitweb?a=commitdiff_plain;h=ee3ec248700669fe9b8b589e4a513918949a26e3;p=openembedded-core.git

site: Add riscv32 and riscv64

Signed-off-by: Khem Raj <raj.khem@gmail.com>
Signed-off-by: Ross Burton <ross.burton@intel.com>
---

diff --git a/meta/site/riscv32-linux b/meta/site/riscv32-linux
new file mode 100644
index 0000000000..a496bd1aca
--- /dev/null
+++ b/meta/site/riscv32-linux
@@ -0,0 +1,4 @@
+# glib-2.0
+glib_cv_stack_grows=${glib_cv_stack_grows=no}
+glib_cv_uscore=${glib_cv_uscore=no}
+
diff --git a/meta/site/riscv64-linux b/meta/site/riscv64-linux
new file mode 100644
index 0000000000..a496bd1aca
--- /dev/null
+++ b/meta/site/riscv64-linux
@@ -0,0 +1,4 @@
+# glib-2.0
+glib_cv_stack_grows=${glib_cv_stack_grows=no}
+glib_cv_uscore=${glib_cv_uscore=no}
+