From: Leon Woestenberg Date: Fri, 6 Jan 2012 19:07:22 +0000 (+0100) Subject: linux-imx: Replace patch for DMA_ZONE by improved patch. X-Git-Tag: 2.1~1941^2~2 X-Git-Url: https://code.ossystems.io/gitweb?a=commitdiff_plain;h=f87e3a792413f3b247c9542119cada997040ca32;p=meta-freescale.git linux-imx: Replace patch for DMA_ZONE by improved patch. Add Freescale patches from L2.6.35_MX53_201112_Patches, to be integrated and tested later. Signed-off-by: Leon Woestenberg --- diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx/1130-ENGR00157473-MX5X-UART-disable-UART2-DMA-to-make-G.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1130-ENGR00157473-MX5X-UART-disable-UART2-DMA-to-make-G.patch new file mode 100755 index 00000000..aa897705 --- /dev/null +++ b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1130-ENGR00157473-MX5X-UART-disable-UART2-DMA-to-make-G.patch @@ -0,0 +1,41 @@ +From f7702086585465f6ccaa33ae815535e8ff10f025 Mon Sep 17 00:00:00 2001 +From: Zhang Jiejing +Date: Fri, 23 Sep 2011 11:05:04 +0800 +Subject: [PATCH] ENGR00157473 MX5X: UART: disable UART2 DMA to make GPS work. + +After enable DMA, GPS will keep report these DMA error: + + UART: DMA_ERROR: sr1:2010 sr2:508b + UART: DMA_ERROR: sr1:2050 sr2:508a + UART: DMA_ERROR: sr1:2050 sr2:508b + UART: DMA_ERROR: sr1:10 sr2:1083 + UART: DMA_ERROR: sr1:50 sr2:1082 + UART: DMA_ERROR: sr1:2010 sr2:508b + UART: DMA_ERROR: sr1:2050 sr2:508a + UART: DMA_ERROR: sr1:2010 sr2:508b + UART: DMA_ERROR: sr1:2010 sr2:508b + UART: DMA_ERROR: sr1:2010 sr2:508b + UART: DMA_ERROR: sr1:50 sr2:1083 + +Signed-off-by: Zhang Jiejing +(cherry picked from commit ddaf091fd3f5fae56b3c83f5cf59ee4f189f0a40) +--- + arch/arm/mach-mx5/serial.h | 2 +- + 1 files changed, 1 insertions(+), 1 deletions(-) + +diff --git a/arch/arm/mach-mx5/serial.h b/arch/arm/mach-mx5/serial.h +index 6ed55da..b142fdb 100644 +--- a/arch/arm/mach-mx5/serial.h ++++ b/arch/arm/mach-mx5/serial.h +@@ -45,7 +45,7 @@ + #define UART1_DMA_ENABLE 0 + /* UART 2 configuration */ + #define UART2_UCR4_CTSTL -1 +-#define UART2_DMA_ENABLE 1 ++#define UART2_DMA_ENABLE 0 + #define UART2_DMA_RXBUFSIZE 512 + #define UART2_UFCR_RXTL 16 + #define UART2_UFCR_TXTL 16 +-- +1.5.4.4 + diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx/1131-ENGR00158480-IPUv3-Set-IDMAC-LOCK-for-SDC-display-ch.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1131-ENGR00158480-IPUv3-Set-IDMAC-LOCK-for-SDC-display-ch.patch new file mode 100755 index 00000000..d0653002 --- /dev/null +++ b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1131-ENGR00158480-IPUv3-Set-IDMAC-LOCK-for-SDC-display-ch.patch @@ -0,0 +1,41 @@ +From b33793cbdf0b24f61398dfb98718ac9377e2b046 Mon Sep 17 00:00:00 2001 +From: Liu Ying +Date: Fri, 30 Sep 2011 16:00:09 +0800 +Subject: [PATCH] ENGR00158480 IPUv3:Set IDMAC LOCK for SDC display channels + +Set IDMAC_LOCK_EN_1 to make SDC display channels to generate +eight AXI bursts upon the assertion of the DMA request. +This change fixes the random garbage lines when showing +NV12 frames decoded by VPU with V4L2 output on +XGA@60 display's overlay framebuffer. V4L2 output uses +MEM_PP_MEM to do 180 degree rotation. + +The issue can be reproduced by the following VPU unit test +on MX53 SMD platform: +/unit_tests/mxc_vpu_test.out -D +'-i /1920x1080_H264_AAC5.1ch.2.1ch_track1.h264 -f 2 -w 1024 +-h 768 -r 180 -u 1 -t 1' + +Signed-off-by: Liu Ying +(cherry picked from commit 50f969030c25bc33cf0f05a6a5cad98c52afd858) +--- + drivers/mxc/ipu3/ipu_common.c | 3 +++ + 1 files changed, 3 insertions(+), 0 deletions(-) + +diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c +index 8dfa54f..4b12905 100644 +--- a/drivers/mxc/ipu3/ipu_common.c ++++ b/drivers/mxc/ipu3/ipu_common.c +@@ -385,6 +385,9 @@ static int ipu_probe(struct platform_device *pdev) + /* Set sync refresh channels and CSI->mem channel as high priority */ + __raw_writel(0x18800001L, IDMAC_CHA_PRI(0)); + ++ /* AXI burst setting for sync refresh channels */ ++ __raw_writel(0x003F0000, IDMAC_CH_LOCK_EN_1); ++ + /* Set MCU_T to divide MCU access window into 2 */ + __raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN); + +-- +1.5.4.4 + diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx/1132-ENGR00155891-mx53_loco-enable-mc34708-s-WDI-functio.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1132-ENGR00155891-mx53_loco-enable-mc34708-s-WDI-functio.patch new file mode 100755 index 00000000..8ebcf840 --- /dev/null +++ b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1132-ENGR00155891-mx53_loco-enable-mc34708-s-WDI-functio.patch @@ -0,0 +1,48 @@ +From 8cece584b73434c1eb76a553424ff5b875fd1022 Mon Sep 17 00:00:00 2001 +From: Robin Gong +Date: Sat, 8 Oct 2011 11:17:42 +0800 +Subject: [PATCH] ENGR00155891 mx53_loco: enable mc34708's WDI function and pin configuration + +Because of reboot failure, we add mc34708's WDI reset function and the pin's +mux function when system reboot. So mc34708 will be reset when AP reboot. +Signed-off-by: Robin Gong +(cherry picked from commit 8e03278824625e8d528e129ad49e094e4d533f87) +--- + arch/arm/mach-mx5/mx53_loco_pmic_mc34708.c | 5 +++++ + arch/arm/plat-mxc/system.c | 4 ++++ + 2 files changed, 9 insertions(+), 0 deletions(-) + +diff --git a/arch/arm/mach-mx5/mx53_loco_pmic_mc34708.c b/arch/arm/mach-mx5/mx53_loco_pmic_mc34708.c +index ca5a052..3ad0206 100644 +--- a/arch/arm/mach-mx5/mx53_loco_pmic_mc34708.c ++++ b/arch/arm/mach-mx5/mx53_loco_pmic_mc34708.c +@@ -285,6 +285,11 @@ static int mc34708_regulator_init(struct mc34708 *mc34708) + value &= ~SWHOLD_MASK; + pmic_write_reg(REG_MC34708_USB_CONTROL, value, 0xffffff); + ++ /* enable WDI reset*/ ++ pmic_read_reg(REG_MC34708_POWER_CTL2, &value, 0xffffff); ++ value |= 0x1000; ++ pmic_write_reg(REG_MC34708_POWER_CTL2, value, 0xffffff); ++ + mc34708_register_regulator(mc34708, MC34708_SW1A, &sw1a_init); + mc34708_register_regulator(mc34708, MC34708_SW1B, &sw1b_init); + mc34708_register_regulator(mc34708, MC34708_SW2, &sw2_init); +diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c +index e4665a2..4f21d5c 100644 +--- a/arch/arm/plat-mxc/system.c ++++ b/arch/arm/plat-mxc/system.c +@@ -78,6 +78,10 @@ void arch_reset(char mode, const char *cmd) + } + + /* Assert SRS signal */ ++#ifdef CONFIG_ARCH_MX5 ++ if (board_is_mx53_loco_mc34708()) /*only for mx53_loco_mc34708*/ ++ mxc_iomux_v3_setup_pad(MX53_PAD_GPIO_9__WDOG1_WDOG_B); ++#endif + __raw_writew(wcr_enable, wdog_base); + + /* wait for reset to assert... */ +-- +1.5.4.4 + diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx/1133-ENGR00159010-IPUv3-Restore-IDMAC_CH_LOCK_EN_1-for-re.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1133-ENGR00159010-IPUv3-Restore-IDMAC_CH_LOCK_EN_1-for-re.patch new file mode 100755 index 00000000..0fc04f6c --- /dev/null +++ b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1133-ENGR00159010-IPUv3-Restore-IDMAC_CH_LOCK_EN_1-for-re.patch @@ -0,0 +1,32 @@ +From 3d739cd79c28ea5d633a3f64758570b16260df69 Mon Sep 17 00:00:00 2001 +From: Liu Ying +Date: Sat, 8 Oct 2011 13:30:15 +0800 +Subject: [PATCH] ENGR00159010 IPUv3:Restore IDMAC_CH_LOCK_EN_1 for resume + +This patch restores IDMAC_CH_LOCK_EN_1 register when IPUv3 +driver resumes. This avoid the relative issue if setting +IDMAC_CH_LOCK_EN_1 to be zero. + +Signed-off-by: Liu Ying +(cherry picked from commit fce84cf35dcb338886df8e58f66a7ad1048d2abe) +--- + drivers/mxc/ipu3/ipu_common.c | 3 +++ + 1 files changed, 3 insertions(+), 0 deletions(-) + +diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c +index 4b12905..1f5ed8b 100644 +--- a/drivers/mxc/ipu3/ipu_common.c ++++ b/drivers/mxc/ipu3/ipu_common.c +@@ -2780,6 +2780,9 @@ static int ipu_resume(struct platform_device *pdev) + + /* Set sync refresh channels as high priority */ + __raw_writel(0x18800001L, IDMAC_CHA_PRI(0)); ++ ++ /* AXI burst setting for sync refresh channels */ ++ __raw_writel(0x003F0000, IDMAC_CH_LOCK_EN_1); + clk_disable(g_ipu_clk); + } + mutex_unlock(&ipu_clk_lock); +-- +1.5.4.4 + diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx/1134-ENGR00159738-v4l2-correct-wrong-parameter-when-V4l2.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1134-ENGR00159738-v4l2-correct-wrong-parameter-when-V4l2.patch new file mode 100755 index 00000000..66711688 --- /dev/null +++ b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1134-ENGR00159738-v4l2-correct-wrong-parameter-when-V4l2.patch @@ -0,0 +1,29 @@ +From 0fd61785f56c2785b471e1d2dd1071a480380c3f Mon Sep 17 00:00:00 2001 +From: Yuxi Sun +Date: Wed, 12 Oct 2011 12:17:02 +0800 +Subject: [PATCH] ENGR00159738 v4l2: correct wrong parameter when V4l2 set window size + +Correct wrong parameter when call ipu_csi_set_window_size function + +Signed-off-by: Yuxi Sun +(cherry picked from commit c1cb33e5cbebb979967f74eecf55efe6a83884ab) +--- + drivers/media/video/mxc/capture/mxc_v4l2_capture.c | 2 +- + 1 files changed, 1 insertions(+), 1 deletions(-) + +diff --git a/drivers/media/video/mxc/capture/mxc_v4l2_capture.c b/drivers/media/video/mxc/capture/mxc_v4l2_capture.c +index ded1839..c030a39 100644 +--- a/drivers/media/video/mxc/capture/mxc_v4l2_capture.c ++++ b/drivers/media/video/mxc/capture/mxc_v4l2_capture.c +@@ -1594,7 +1594,7 @@ static int mxc_v4l_open(struct file *file) + pr_debug("On Open: Input to ipu size is %d x %d\n", + cam_fmt.fmt.pix.width, cam_fmt.fmt.pix.height); + ipu_csi_set_window_size(cam->crop_current.width, +- cam->crop_current.width, ++ cam->crop_current.height, + cam->csi); + ipu_csi_set_window_pos(cam->crop_current.left, + cam->crop_current.top, +-- +1.5.4.4 + diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx/1135-ENGR00160566-IPUv3-Improve-IDMAC_LOCK_EN-setting.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1135-ENGR00160566-IPUv3-Improve-IDMAC_LOCK_EN-setting.patch new file mode 100755 index 00000000..4debc1a5 --- /dev/null +++ b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1135-ENGR00160566-IPUv3-Improve-IDMAC_LOCK_EN-setting.patch @@ -0,0 +1,70 @@ +From 8deffb95c405d2dde68da4d2570e57b6f2ec8ae5 Mon Sep 17 00:00:00 2001 +From: Liu Ying +Date: Tue, 25 Oct 2011 14:16:30 +0800 +Subject: [PATCH] ENGR00160566 IPUv3:Improve IDMAC_LOCK_EN setting + +1) Clear IDMAC_LOCK_EN when dual display is enabled + to workaround black flash issue when playing video + on DP-FG. +2) Only set IDMAC_LOCK_EN for IPUv3M. + +Signed-off-by: Liu Ying +(cherry picked from commit 7c22da39601cfc6551292cbd2c5c1d9ee3b4fbfa) +--- + drivers/mxc/ipu3/ipu_common.c | 19 +++++++++++++++++-- + 1 files changed, 17 insertions(+), 2 deletions(-) + +diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c +index 1f5ed8b..baf22dd 100644 +--- a/drivers/mxc/ipu3/ipu_common.c ++++ b/drivers/mxc/ipu3/ipu_common.c +@@ -386,7 +386,8 @@ static int ipu_probe(struct platform_device *pdev) + __raw_writel(0x18800001L, IDMAC_CHA_PRI(0)); + + /* AXI burst setting for sync refresh channels */ +- __raw_writel(0x003F0000, IDMAC_CH_LOCK_EN_1); ++ if (g_ipu_hw_rev == 3) ++ __raw_writel(0x003F0000, IDMAC_CH_LOCK_EN_1); + + /* Set MCU_T to divide MCU access window into 2 */ + __raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN); +@@ -989,6 +990,11 @@ void ipu_uninit_channel(ipu_channel_t channel) + + __raw_writel(ipu_conf, IPU_CONF); + ++ /* Restore IDMAC_LOCK_EN when we don't use dual display */ ++ if (!(ipu_di_use_count[0] && ipu_di_use_count[1]) && ++ _ipu_is_dmfc_chan(in_dma) && g_ipu_hw_rev == 3) ++ __raw_writel(0x003F0000, IDMAC_CH_LOCK_EN_1); ++ + spin_unlock_irqrestore(&ipu_lock, lock_flags); + + ipu_put_clk(); +@@ -1800,6 +1806,14 @@ int32_t ipu_enable_channel(ipu_channel_t channel) + ipu_conf |= IPU_CONF_SMFC_EN; + __raw_writel(ipu_conf, IPU_CONF); + ++ /* Clear IDMAC_LOCK_EN to workaround black flash for dual display */ ++ if (g_ipu_hw_rev == 3 && _ipu_is_dmfc_chan(in_dma)) { ++ if (ipu_di_use_count[1] && ipu_di_use_count[0]) ++ __raw_writel(0x0, IDMAC_CH_LOCK_EN_1); ++ else ++ __raw_writel(0x003F0000, IDMAC_CH_LOCK_EN_1); ++ } ++ + if (idma_is_valid(in_dma)) { + reg = __raw_readl(IDMAC_CHA_EN(in_dma)); + __raw_writel(reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma)); +@@ -2782,7 +2796,8 @@ static int ipu_resume(struct platform_device *pdev) + __raw_writel(0x18800001L, IDMAC_CHA_PRI(0)); + + /* AXI burst setting for sync refresh channels */ +- __raw_writel(0x003F0000, IDMAC_CH_LOCK_EN_1); ++ if (g_ipu_hw_rev == 3) ++ __raw_writel(0x003F0000, IDMAC_CH_LOCK_EN_1); + clk_disable(g_ipu_clk); + } + mutex_unlock(&ipu_clk_lock); +-- +1.5.4.4 + diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx/1136-ENGR00161215-1-arch-arm-Add-two-new-IOCTLs-in-mxc_v.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1136-ENGR00161215-1-arch-arm-Add-two-new-IOCTLs-in-mxc_v.patch new file mode 100755 index 00000000..dbe92f4a --- /dev/null +++ b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1136-ENGR00161215-1-arch-arm-Add-two-new-IOCTLs-in-mxc_v.patch @@ -0,0 +1,33 @@ +From 3083ae11d58fb7a083663865020c0a763540532b Mon Sep 17 00:00:00 2001 +From: Sammy He +Date: Wed, 2 Nov 2011 20:02:35 +0800 +Subject: [PATCH] ENGR00161215-1 arch/arm: Add two new IOCTLs in mxc_vpu.h + +Add IOCTL VPU_IOC_QUERY_BITWORK_MEM and VPU_IOC_SET_BITWORK_MEM +for vpu driver. +The two ioctls can be used when user allocates working buffer +from user space, for exmaple, allocating it from pmem interface +on android, then register it to vpu driver. + +Signed-off-by: Sammy He +(cherry picked from commit ad29cb1c2ad8ca4bbb30ff2ff55a4e8888b08373) +--- + arch/arm/plat-mxc/include/mach/mxc_vpu.h | 2 ++ + 1 files changed, 2 insertions(+), 0 deletions(-) + +diff --git a/arch/arm/plat-mxc/include/mach/mxc_vpu.h b/arch/arm/plat-mxc/include/mach/mxc_vpu.h +index 355a9ef..32865e5 100644 +--- a/arch/arm/plat-mxc/include/mach/mxc_vpu.h ++++ b/arch/arm/plat-mxc/include/mach/mxc_vpu.h +@@ -48,6 +48,8 @@ struct vpu_mem_desc { + #define VPU_IOC_REQ_VSHARE_MEM _IO(VPU_IOC_MAGIC, 9) + #define VPU_IOC_SYS_SW_RESET _IO(VPU_IOC_MAGIC, 11) + #define VPU_IOC_GET_SHARE_MEM _IO(VPU_IOC_MAGIC, 12) ++#define VPU_IOC_QUERY_BITWORK_MEM _IO(VPU_IOC_MAGIC, 13) ++#define VPU_IOC_SET_BITWORK_MEM _IO(VPU_IOC_MAGIC, 14) + + #define BIT_CODE_RUN 0x000 + #define BIT_CODE_DOWN 0x004 +-- +1.5.4.4 + diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx/1137-ENGR00161215-2-vpu-Add-ioctls-for-querying-and-sett.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1137-ENGR00161215-2-vpu-Add-ioctls-for-querying-and-sett.patch new file mode 100755 index 00000000..b26260ac --- /dev/null +++ b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1137-ENGR00161215-2-vpu-Add-ioctls-for-querying-and-sett.patch @@ -0,0 +1,49 @@ +From 9ca7a0b9b98e41c543bd328469e213b89251d470 Mon Sep 17 00:00:00 2001 +From: Sammy He +Date: Wed, 2 Nov 2011 20:08:42 +0800 +Subject: [PATCH] ENGR00161215-2 vpu: Add ioctls for querying and setting bitwork memory + +Add VPU_IOC_QUERY_BITWORK_MEM and VPU_IOC_SET_BITWORK_MEM ioctls +implementation for registerring bitwork memory allocated from user +space to vpu driver. + +Signed-off-by: Sammy He +(cherry picked from commit 98d71e85dbd05df9c866d153a4ead9526a26422e) +--- + drivers/mxc/vpu/mxc_vpu.c | 20 ++++++++++++++++++++ + 1 files changed, 20 insertions(+), 0 deletions(-) + +diff --git a/drivers/mxc/vpu/mxc_vpu.c b/drivers/mxc/vpu/mxc_vpu.c +index 41bd188..00f164a 100644 +--- a/drivers/mxc/vpu/mxc_vpu.c ++++ b/drivers/mxc/vpu/mxc_vpu.c +@@ -446,6 +446,26 @@ static int vpu_ioctl(struct inode *inode, struct file *filp, u_int cmd, + } + break; + } ++ /* ++ * The following two ioctl is used when user allocates working buffer ++ * and register it to vpu driver. ++ */ ++ case VPU_IOC_QUERY_BITWORK_MEM: ++ { ++ if (copy_to_user((void __user *)arg, ++ &bitwork_mem, ++ sizeof(struct vpu_mem_desc))) ++ ret = -EFAULT; ++ break; ++ } ++ case VPU_IOC_SET_BITWORK_MEM: ++ { ++ if (copy_from_user(&bitwork_mem, ++ (struct vpu_mem_desc *)arg, ++ sizeof(struct vpu_mem_desc))) ++ ret = -EFAULT; ++ break; ++ } + case VPU_IOC_SYS_SW_RESET: + { + if (vpu_plat->reset) +-- +1.5.4.4 + diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx/1138-ENGR00162195-IPUv3M-Clear-IDMAC_LOCK_EN_1-for-tough.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1138-ENGR00162195-IPUv3M-Clear-IDMAC_LOCK_EN_1-for-tough.patch new file mode 100755 index 00000000..27bac664 --- /dev/null +++ b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1138-ENGR00162195-IPUv3M-Clear-IDMAC_LOCK_EN_1-for-tough.patch @@ -0,0 +1,43 @@ +From f19b8f13079c5593c31a5eb381ba5ac734779f84 Mon Sep 17 00:00:00 2001 +From: Liu Ying +Date: Tue, 15 Nov 2011 16:21:25 +0800 +Subject: [PATCH] ENGR00162195 IPUv3M:Clear IDMAC_LOCK_EN_1 for tough single display + +This patch clears IDMAC_LOCK_EN_1 for tough single display(dmfc=3). +For example, 1080P50/1080P60 with 32bpp fb. + +Signed-off-by: Liu Ying +(cherry picked from commit 204a5fb6af1426c499332224dff00f52bdbef39b) +--- + drivers/mxc/ipu3/ipu_common.c | 6 +++++- + 1 files changed, 5 insertions(+), 1 deletions(-) + +diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c +index baf22dd..18d46b3 100644 +--- a/drivers/mxc/ipu3/ipu_common.c ++++ b/drivers/mxc/ipu3/ipu_common.c +@@ -991,7 +991,9 @@ void ipu_uninit_channel(ipu_channel_t channel) + __raw_writel(ipu_conf, IPU_CONF); + + /* Restore IDMAC_LOCK_EN when we don't use dual display */ ++ /* and the video mode for single display is not tough */ + if (!(ipu_di_use_count[0] && ipu_di_use_count[1]) && ++ dmfc_type_setup != DMFC_HIGH_RESOLUTION_ONLY_DP && + _ipu_is_dmfc_chan(in_dma) && g_ipu_hw_rev == 3) + __raw_writel(0x003F0000, IDMAC_CH_LOCK_EN_1); + +@@ -1807,8 +1809,10 @@ int32_t ipu_enable_channel(ipu_channel_t channel) + __raw_writel(ipu_conf, IPU_CONF); + + /* Clear IDMAC_LOCK_EN to workaround black flash for dual display */ ++ /* and for tough video mode of single display */ + if (g_ipu_hw_rev == 3 && _ipu_is_dmfc_chan(in_dma)) { +- if (ipu_di_use_count[1] && ipu_di_use_count[0]) ++ if ((ipu_di_use_count[1] && ipu_di_use_count[0]) || ++ (dmfc_type_setup == DMFC_HIGH_RESOLUTION_ONLY_DP)) + __raw_writel(0x0, IDMAC_CH_LOCK_EN_1); + else + __raw_writel(0x003F0000, IDMAC_CH_LOCK_EN_1); +-- +1.5.4.4 + diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx/1139-ENGR00162464-update-pm4-microcode-pm4_microcode_r18.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1139-ENGR00162464-update-pm4-microcode-pm4_microcode_r18.patch new file mode 100755 index 00000000..b880c2b5 --- /dev/null +++ b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1139-ENGR00162464-update-pm4-microcode-pm4_microcode_r18.patch @@ -0,0 +1,820 @@ +From 10841bda9560f6a5b5581f9a2df3760cf6ee8c17 Mon Sep 17 00:00:00 2001 +From: Richard Zhao +Date: Fri, 18 Nov 2011 10:33:10 +0800 +Subject: [PATCH] ENGR00162464 update pm4 microcode: pm4_microcode_r18_20111020.a.inl.rel + +It fix gpu hang. + +Signed-off-by: Richard Zhao +(cherry picked from commit acc00a6f1847bf8cdde1802b4375dc89d5160dfe) +--- + drivers/mxc/amd-gpu/common/pm4_microcode.inl | 371 +++++++++++++------------- + 1 files changed, 186 insertions(+), 185 deletions(-) + +diff --git a/drivers/mxc/amd-gpu/common/pm4_microcode.inl b/drivers/mxc/amd-gpu/common/pm4_microcode.inl +index aa7c9fc..058548b 100644 +--- a/drivers/mxc/amd-gpu/common/pm4_microcode.inl ++++ b/drivers/mxc/amd-gpu/common/pm4_microcode.inl +@@ -1,4 +1,4 @@ +-/* Copyright (c) 2008-2010, QUALCOMM Incorporated. All rights reserved. ++/* Copyright (c) 2008-2011, QUALCOMM Incorporated. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: +@@ -26,12 +26,14 @@ + * + */ + ++// Microcode Source Version 20111020.a ++ + #ifndef PM4_MICROCODE_H + #define PM4_MICROCODE_H + +-#define PM4_MICROCODE_VERSION 322696 ++#define PM4_MICROCODE_VERSION 422468 + +-#define PM4_MICROCODE_SIZE 768 ++#define PM4_MICROCODE_SIZE 768 // Size of PM4 microcode in QWORD + + + #ifdef _PRIMLIB_INCLUDE +@@ -47,20 +49,20 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0x00000000, 0xd9004800, 0x000 }, + { 0x00000000, 0x00400000, 0x000 }, + { 0x00000000, 0x34e00000, 0x000 }, +- { 0x00000000, 0x00600000, 0x28c }, ++ { 0x00000000, 0x00600000, 0x287 }, + { 0x0000ffff, 0xc0280a20, 0x000 }, + { 0x00000000, 0x00294582, 0x000 }, + { 0x00000000, 0xd9004800, 0x000 }, + { 0x00000000, 0x00400000, 0x000 }, +- { 0x00000000, 0x00600000, 0x28c }, ++ { 0x00000000, 0x00600000, 0x287 }, + { 0x0000ffff, 0xc0284620, 0x000 }, + { 0x00000000, 0xd9004800, 0x000 }, + { 0x00000000, 0x00400000, 0x000 }, +- { 0x00000000, 0x00600000, 0x2b0 }, ++ { 0x00000000, 0x00600000, 0x2ac }, + { 0x00000000, 0xc0200c00, 0x000 }, + { 0x000021fc, 0x0029462c, 0x000 }, + { 0x00000000, 0x00404803, 0x021 }, +- { 0x00000000, 0x00600000, 0x2b0 }, ++ { 0x00000000, 0x00600000, 0x2ac }, + { 0x00000000, 0xc0200000, 0x000 }, + { 0x00000000, 0xc0200c00, 0x000 }, + { 0x000021fc, 0x0029462c, 0x000 }, +@@ -78,7 +80,7 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0x0000000e, 0x00404811, 0x000 }, + { 0x00000394, 0x00204411, 0x000 }, + { 0x00000001, 0xc0404811, 0x000 }, +- { 0x00000000, 0x00600000, 0x2b0 }, ++ { 0x00000000, 0x00600000, 0x2ac }, + { 0x000021f9, 0x0029462c, 0x000 }, + { 0x00000008, 0xc0210a20, 0x000 }, + { 0x00000000, 0x14e00000, 0x02d }, +@@ -88,53 +90,48 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0x0000001b, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ce00000, 0x043 }, + { 0x00000002, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x04a }, ++ { 0x00000000, 0x0ce00000, 0x045 }, + { 0x00000003, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x051 }, ++ { 0x00000000, 0x0ce00000, 0x047 }, + { 0x00000004, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x058 }, ++ { 0x00000000, 0x0ce00000, 0x049 }, + { 0x00000014, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x058 }, ++ { 0x00000000, 0x0ce00000, 0x049 }, + { 0x00000015, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x060 }, ++ { 0x00000000, 0x0ce00000, 0x05b }, + { 0x000021f9, 0x0029462c, 0x000 }, + { 0x00000000, 0xc0404802, 0x000 }, + { 0x0000001f, 0x40280a20, 0x000 }, + { 0x0000001b, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ce00000, 0x043 }, + { 0x00000002, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x04a }, +- { 0x00000000, 0x00400000, 0x051 }, ++ { 0x00000000, 0x0ce00000, 0x045 }, ++ { 0x00000000, 0x00400000, 0x047 }, + { 0x0000001f, 0xc0210e20, 0x000 }, +- { 0x00000612, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204803, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x000021f9, 0x0029462c, 0x000 }, +- { 0x00000000, 0x00404802, 0x000 }, ++ { 0x00000612, 0x00404411, 0x04c }, + { 0x0000001e, 0xc0210e20, 0x000 }, +- { 0x00000600, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204803, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x000021f9, 0x0029462c, 0x000 }, +- { 0x00000000, 0x00404802, 0x000 }, ++ { 0x00000600, 0x00404411, 0x04c }, + { 0x0000001e, 0xc0210e20, 0x000 }, +- { 0x00000605, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204803, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x000021f9, 0x0029462c, 0x000 }, +- { 0x00000000, 0x00404802, 0x000 }, ++ { 0x00000605, 0x00404411, 0x04c }, + { 0x0000001f, 0x40280a20, 0x000 }, + { 0x0000001f, 0xc0210e20, 0x000 }, + { 0x0000060a, 0x00204411, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, ++ { 0x00000000, 0xc0201000, 0x000 }, ++ { 0x00000000, 0x00204804, 0x000 }, ++ { 0x00000000, 0xc0200c00, 0x000 }, ++ { 0x00000000, 0x00204803, 0x000 }, ++ { 0x00000080, 0x00201c11, 0x000 }, + { 0x000021f9, 0x0029462c, 0x000 }, +- { 0x00000000, 0x00404802, 0x000 }, +- { 0x0000001f, 0xc0680a20, 0x2b0 }, ++ { 0x00000000, 0x00204802, 0x000 }, ++ { 0x00000000, 0x00600000, 0x130 }, ++ { 0x00000000, 0x002f0070, 0x000 }, ++ { 0x00000000, 0x0ce00000, 0x000 }, ++ { 0x00000001, 0x00331e27, 0x000 }, ++ { 0x00000000, 0x002f0227, 0x000 }, ++ { 0x00000000, 0x0ae00000, 0x054 }, ++ { 0x00000000, 0x00400000, 0x051 }, ++ { 0x0000001f, 0xc0680a20, 0x2ac }, + { 0x000021f9, 0x0029462c, 0x000 }, + { 0x00000000, 0x00404802, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, +@@ -142,24 +139,24 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0x00001fff, 0x40280a20, 0x000 }, + { 0x80000000, 0x40280e20, 0x000 }, + { 0x40000000, 0xc0281220, 0x000 }, +- { 0x00040000, 0x00694622, 0x2ba }, ++ { 0x00040000, 0x00694622, 0x2b4 }, + { 0x00000000, 0x00201410, 0x000 }, + { 0x00000000, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x06d }, +- { 0x00000000, 0xc0401800, 0x070 }, ++ { 0x00000000, 0x0ae00000, 0x068 }, ++ { 0x00000000, 0xc0401800, 0x06b }, + { 0x00001fff, 0xc0281a20, 0x000 }, +- { 0x00040000, 0x00694626, 0x2ba }, ++ { 0x00040000, 0x00694626, 0x2b4 }, + { 0x00000000, 0x00201810, 0x000 }, + { 0x00000000, 0x002f0224, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x073 }, +- { 0x00000000, 0xc0401c00, 0x076 }, ++ { 0x00000000, 0x0ae00000, 0x06e }, ++ { 0x00000000, 0xc0401c00, 0x071 }, + { 0x00001fff, 0xc0281e20, 0x000 }, +- { 0x00040000, 0x00694627, 0x2ba }, ++ { 0x00040000, 0x00694627, 0x2b4 }, + { 0x00000000, 0x00201c10, 0x000 }, + { 0x00000000, 0x00204402, 0x000 }, + { 0x00000000, 0x002820c5, 0x000 }, + { 0x00000000, 0x004948e8, 0x000 }, +- { 0x00000000, 0x00600000, 0x28c }, ++ { 0x00000000, 0x00600000, 0x287 }, + { 0x00000010, 0x40210a20, 0x000 }, + { 0x000000ff, 0x00280a22, 0x000 }, + { 0x000007ff, 0x40280e20, 0x000 }, +@@ -167,25 +164,25 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0x00000005, 0xc0211220, 0x000 }, + { 0x00080000, 0x00281224, 0x000 }, + { 0x00000013, 0x00210224, 0x000 }, +- { 0x00000000, 0x14c00000, 0x084 }, ++ { 0x00000000, 0x14c00000, 0x07f }, + { 0xa100ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204811, 0x000 }, + { 0x00000000, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x088 }, ++ { 0x00000000, 0x0ae00000, 0x083 }, + { 0x00000000, 0x0020162d, 0x000 }, +- { 0x00004000, 0x00500e23, 0x097 }, ++ { 0x00004000, 0x00500e23, 0x092 }, + { 0x00000001, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x08c }, ++ { 0x00000000, 0x0ae00000, 0x087 }, + { 0x00000001, 0x0020162d, 0x000 }, +- { 0x00004800, 0x00500e23, 0x097 }, ++ { 0x00004800, 0x00500e23, 0x092 }, + { 0x00000002, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x090 }, ++ { 0x00000000, 0x0ae00000, 0x08b }, + { 0x00000003, 0x0020162d, 0x000 }, +- { 0x00004900, 0x00500e23, 0x097 }, ++ { 0x00004900, 0x00500e23, 0x092 }, + { 0x00000003, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x094 }, ++ { 0x00000000, 0x0ae00000, 0x08f }, + { 0x00000002, 0x0020162d, 0x000 }, +- { 0x00004908, 0x00500e23, 0x097 }, ++ { 0x00004908, 0x00500e23, 0x092 }, + { 0x00000012, 0x0020162d, 0x000 }, + { 0x00002000, 0x00300e23, 0x000 }, + { 0x00000000, 0x00290d83, 0x000 }, +@@ -200,7 +197,7 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0x00000000, 0x002948e5, 0x000 }, + { 0x9300ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00404806, 0x000 }, +- { 0x00000000, 0x00600000, 0x28c }, ++ { 0x00000000, 0x00600000, 0x287 }, + { 0x00000000, 0xc0200800, 0x000 }, + { 0x00000000, 0xc0201400, 0x000 }, + { 0x0000001f, 0x00211a25, 0x000 }, +@@ -209,31 +206,31 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0x00000010, 0x00211225, 0x000 }, + { 0x8300ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x002f0224, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x0ae }, ++ { 0x00000000, 0x0ae00000, 0x0a9 }, + { 0x00000000, 0x00203622, 0x000 }, +- { 0x00004000, 0x00504a23, 0x0bd }, ++ { 0x00004000, 0x00504a23, 0x0b8 }, + { 0x00000001, 0x002f0224, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x0b2 }, ++ { 0x00000000, 0x0ae00000, 0x0ad }, + { 0x00000001, 0x00203622, 0x000 }, +- { 0x00004800, 0x00504a23, 0x0bd }, ++ { 0x00004800, 0x00504a23, 0x0b8 }, + { 0x00000002, 0x002f0224, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x0b6 }, ++ { 0x00000000, 0x0ae00000, 0x0b1 }, + { 0x00000003, 0x00203622, 0x000 }, +- { 0x00004900, 0x00504a23, 0x0bd }, ++ { 0x00004900, 0x00504a23, 0x0b8 }, + { 0x00000003, 0x002f0224, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x0ba }, ++ { 0x00000000, 0x0ae00000, 0x0b5 }, + { 0x00000002, 0x00203622, 0x000 }, +- { 0x00004908, 0x00504a23, 0x0bd }, ++ { 0x00004908, 0x00504a23, 0x0b8 }, + { 0x00000012, 0x00203622, 0x000 }, + { 0x00000000, 0x00290d83, 0x000 }, + { 0x00002000, 0x00304a23, 0x000 }, + { 0x8400ffff, 0x00204411, 0x000 }, + { 0x00000000, 0xc0204800, 0x000 }, + { 0x00000000, 0x21000000, 0x000 }, +- { 0x00000000, 0x00400000, 0x0a4 }, ++ { 0x00000000, 0x00400000, 0x09f }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000001, 0x00204811, 0x000 }, +- { 0x00040578, 0x00604411, 0x2ba }, ++ { 0x00040578, 0x00604411, 0x2b4 }, + { 0x00000000, 0xc0400000, 0x000 }, + { 0x00000000, 0xc0200c00, 0x000 }, + { 0x00000000, 0xc0201000, 0x000 }, +@@ -241,62 +238,62 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0x00000000, 0xc0201800, 0x000 }, + { 0x00007f00, 0x00280a21, 0x000 }, + { 0x00004500, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x0cd }, ++ { 0x00000000, 0x0ce00000, 0x0c8 }, + { 0x00000000, 0xc0201c00, 0x000 }, + { 0x00000000, 0x17000000, 0x000 }, + { 0x00000010, 0x00280a23, 0x000 }, + { 0x00000010, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x0d5 }, ++ { 0x00000000, 0x0ce00000, 0x0d0 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000001, 0x00204811, 0x000 }, +- { 0x00040000, 0x00694624, 0x2ba }, +- { 0x00000000, 0x00400000, 0x0d6 }, +- { 0x00000000, 0x00600000, 0x135 }, ++ { 0x00040000, 0x00694624, 0x2b4 }, ++ { 0x00000000, 0x00400000, 0x0d1 }, ++ { 0x00000000, 0x00600000, 0x130 }, + { 0x00000000, 0x002820d0, 0x000 }, + { 0x00000007, 0x00280a23, 0x000 }, + { 0x00000001, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x0dd }, ++ { 0x00000000, 0x0ae00000, 0x0d8 }, + { 0x00000000, 0x002f00a8, 0x000 }, +- { 0x00000000, 0x04e00000, 0x0f6 }, +- { 0x00000000, 0x00400000, 0x0fd }, ++ { 0x00000000, 0x04e00000, 0x0f1 }, ++ { 0x00000000, 0x00400000, 0x0f8 }, + { 0x00000002, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x0e2 }, ++ { 0x00000000, 0x0ae00000, 0x0dd }, + { 0x00000000, 0x002f00a8, 0x000 }, +- { 0x00000000, 0x02e00000, 0x0f6 }, +- { 0x00000000, 0x00400000, 0x0fd }, ++ { 0x00000000, 0x02e00000, 0x0f1 }, ++ { 0x00000000, 0x00400000, 0x0f8 }, + { 0x00000003, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x0e7 }, ++ { 0x00000000, 0x0ae00000, 0x0e2 }, + { 0x00000000, 0x002f00a8, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x0f6 }, +- { 0x00000000, 0x00400000, 0x0fd }, ++ { 0x00000000, 0x0ce00000, 0x0f1 }, ++ { 0x00000000, 0x00400000, 0x0f8 }, + { 0x00000004, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x0ec }, ++ { 0x00000000, 0x0ae00000, 0x0e7 }, + { 0x00000000, 0x002f00a8, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x0f6 }, +- { 0x00000000, 0x00400000, 0x0fd }, +- { 0x00000005, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x0f1 }, ++ { 0x00000000, 0x00400000, 0x0f8 }, ++ { 0x00000005, 0x002f0222, 0x000 }, ++ { 0x00000000, 0x0ae00000, 0x0ec }, + { 0x00000000, 0x002f00a8, 0x000 }, +- { 0x00000000, 0x06e00000, 0x0f6 }, +- { 0x00000000, 0x00400000, 0x0fd }, ++ { 0x00000000, 0x06e00000, 0x0f1 }, ++ { 0x00000000, 0x00400000, 0x0f8 }, + { 0x00000006, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x0f6 }, ++ { 0x00000000, 0x0ae00000, 0x0f1 }, + { 0x00000000, 0x002f00a8, 0x000 }, +- { 0x00000000, 0x08e00000, 0x0f6 }, +- { 0x00000000, 0x00400000, 0x0fd }, ++ { 0x00000000, 0x08e00000, 0x0f1 }, ++ { 0x00000000, 0x00400000, 0x0f8 }, + { 0x00007f00, 0x00280a21, 0x000 }, + { 0x00004500, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x000 }, + { 0x00000008, 0x00210a23, 0x000 }, +- { 0x00000000, 0x14e00000, 0x11b }, ++ { 0x00000000, 0x14e00000, 0x116 }, + { 0x00000000, 0xc0204400, 0x000 }, + { 0x00000000, 0xc0404800, 0x000 }, + { 0x00007f00, 0x00280a21, 0x000 }, + { 0x00004500, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x102 }, ++ { 0x00000000, 0x0ae00000, 0x0fd }, + { 0x00000000, 0xc0200000, 0x000 }, + { 0x00000000, 0xc0400000, 0x000 }, +- { 0x00000000, 0x00404c07, 0x0cd }, ++ { 0x00000000, 0x00404c07, 0x0c8 }, + { 0x00000000, 0xc0201000, 0x000 }, + { 0x00000000, 0xc0201400, 0x000 }, + { 0x00000000, 0xc0201800, 0x000 }, +@@ -304,11 +301,11 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0x00000000, 0x17000000, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000001, 0x00204811, 0x000 }, +- { 0x00040000, 0x00694624, 0x2ba }, ++ { 0x00040000, 0x00694624, 0x2b4 }, + { 0x00000000, 0x002820d0, 0x000 }, + { 0x00000000, 0x002f00a8, 0x000 }, + { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x00404c07, 0x107 }, ++ { 0x00000000, 0x00404c07, 0x102 }, + { 0x00000000, 0xc0201000, 0x000 }, + { 0x00000000, 0xc0201400, 0x000 }, + { 0x00000000, 0xc0201800, 0x000 }, +@@ -316,11 +313,11 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0x00000000, 0x17000000, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000001, 0x00204811, 0x000 }, +- { 0x00040000, 0x00694624, 0x2ba }, ++ { 0x00040000, 0x00694624, 0x2b4 }, + { 0x00000000, 0x002820d0, 0x000 }, + { 0x00000000, 0x002f00a8, 0x000 }, + { 0x00000000, 0x06e00000, 0x000 }, +- { 0x00000000, 0x00404c07, 0x113 }, ++ { 0x00000000, 0x00404c07, 0x10e }, + { 0x0000060d, 0x00204411, 0x000 }, + { 0x00000000, 0xc0204800, 0x000 }, + { 0x0000860e, 0x00204411, 0x000 }, +@@ -335,13 +332,13 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0x00000001, 0x00204811, 0x000 }, + { 0x00000000, 0xc0200800, 0x000 }, + { 0x00007fff, 0x00281a22, 0x000 }, +- { 0x00040000, 0x00694626, 0x2ba }, ++ { 0x00040000, 0x00694626, 0x2b4 }, + { 0x00000000, 0x00200c10, 0x000 }, + { 0x00000000, 0xc0201000, 0x000 }, + { 0x80000000, 0x00281a22, 0x000 }, + { 0x00000000, 0x002f0226, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x132 }, +- { 0x00000000, 0x00600000, 0x135 }, ++ { 0x00000000, 0x0ce00000, 0x12d }, ++ { 0x00000000, 0x00600000, 0x130 }, + { 0x00000000, 0x00201c10, 0x000 }, + { 0x00000000, 0x00300c67, 0x000 }, + { 0x0000060d, 0x00204411, 0x000 }, +@@ -353,10 +350,10 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0x00000000, 0x00204811, 0x000 }, + { 0x000001ea, 0x00204411, 0x000 }, + { 0x00000000, 0x00204804, 0x000 }, +- { 0x00000000, 0x1ac00000, 0x13b }, ++ { 0x00000000, 0x1ac00000, 0x136 }, + { 0x9e00ffff, 0x00204411, 0x000 }, + { 0xdeadbeef, 0x00204811, 0x000 }, +- { 0x00000000, 0x1ae00000, 0x13e }, ++ { 0x00000000, 0x1ae00000, 0x139 }, + { 0xa400ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x0080480b, 0x000 }, + { 0x000001f3, 0x00204411, 0x000 }, +@@ -405,28 +402,28 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0x00000001, 0x00303e2f, 0x000 }, + { 0x00000000, 0xc0200800, 0x000 }, + { 0x00000000, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x172 }, ++ { 0x00000000, 0x0ce00000, 0x16d }, + { 0x00000000, 0xd9000000, 0x000 }, + { 0x00000000, 0x00400000, 0x000 }, +- { 0x00000000, 0x00600000, 0x28c }, ++ { 0x00000000, 0x00600000, 0x287 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000002, 0x00204811, 0x000 }, + { 0x00000000, 0x002f0230, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x175 }, ++ { 0x00000000, 0x0ae00000, 0x170 }, + { 0x00000000, 0xc0200800, 0x000 }, + { 0x00000009, 0x00210222, 0x000 }, +- { 0x00000000, 0x14c00000, 0x17d }, +- { 0x00000000, 0x00600000, 0x2b7 }, ++ { 0x00000000, 0x14c00000, 0x178 }, ++ { 0x00000000, 0x00600000, 0x2aa }, + { 0x00000000, 0x00200c11, 0x000 }, + { 0x00000016, 0x00203623, 0x000 }, + { 0x00000000, 0x00210222, 0x000 }, +- { 0x00000000, 0x14c00000, 0x180 }, ++ { 0x00000000, 0x14c00000, 0x17b }, + { 0x00000000, 0xc0200000, 0x000 }, + { 0x00000001, 0x00210222, 0x000 }, +- { 0x00000000, 0x14c00000, 0x183 }, ++ { 0x00000000, 0x14c00000, 0x17e }, + { 0x00000000, 0xc0200000, 0x000 }, + { 0x00000002, 0x00210222, 0x000 }, +- { 0x00000000, 0x14c00000, 0x18d }, ++ { 0x00000000, 0x14c00000, 0x188 }, + { 0x00000004, 0xc0203620, 0x000 }, + { 0x00000005, 0xc0203620, 0x000 }, + { 0x00000006, 0xc0203620, 0x000 }, +@@ -436,7 +433,7 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0x0000000a, 0xc0203620, 0x000 }, + { 0x0000000b, 0xc0203620, 0x000 }, + { 0x00000003, 0x00210222, 0x000 }, +- { 0x00000000, 0x14c00000, 0x1b5 }, ++ { 0x00000000, 0x14c00000, 0x1b0 }, + { 0x00000000, 0xc0200c00, 0x000 }, + { 0x8c00ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, +@@ -476,24 +473,24 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0x00000003, 0x00384a27, 0x000 }, + { 0x00300000, 0x00293a2e, 0x000 }, + { 0x00000004, 0x00210222, 0x000 }, +- { 0x00000000, 0x14c00000, 0x1bd }, ++ { 0x00000000, 0x14c00000, 0x1b8 }, + { 0xa300ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x40204800, 0x000 }, + { 0x0000000a, 0xc0220e20, 0x000 }, + { 0x00000011, 0x00203623, 0x000 }, + { 0x000021f4, 0x00204411, 0x000 }, +- { 0x0000000a, 0x00614a2c, 0x2b7 }, ++ { 0x0000000a, 0x00614a2c, 0x2aa }, + { 0x00000005, 0x00210222, 0x000 }, +- { 0x00000000, 0x14c00000, 0x1c0 }, ++ { 0x00000000, 0x14c00000, 0x1bb }, + { 0x00000000, 0xc0200000, 0x000 }, + { 0x00000006, 0x00210222, 0x000 }, +- { 0x00000000, 0x14c00000, 0x1c6 }, ++ { 0x00000000, 0x14c00000, 0x1c1 }, + { 0x9c00ffff, 0x00204411, 0x000 }, + { 0x0000001f, 0x40214a20, 0x000 }, + { 0x9600ffff, 0x00204411, 0x000 }, + { 0x00000000, 0xc0204800, 0x000 }, + { 0x00000007, 0x00210222, 0x000 }, +- { 0x00000000, 0x14c00000, 0x1d0 }, ++ { 0x00000000, 0x14c00000, 0x1cb }, + { 0x3fffffff, 0x00283a2e, 0x000 }, + { 0xc0000000, 0x40280e20, 0x000 }, + { 0x00000000, 0x0029386e, 0x000 }, +@@ -503,7 +500,7 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0x00000000, 0xc0202c00, 0x000 }, + { 0x00000000, 0x0020480b, 0x000 }, + { 0x00000008, 0x00210222, 0x000 }, +- { 0x00000000, 0x14c00000, 0x1dc }, ++ { 0x00000000, 0x14c00000, 0x1d7 }, + { 0x00000000, 0xc0200c00, 0x000 }, + { 0x00000013, 0x00203623, 0x000 }, + { 0x00000015, 0x00203623, 0x000 }, +@@ -515,7 +512,7 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0xefffffff, 0x00283a2e, 0x000 }, + { 0x00000000, 0x0029386e, 0x000 }, + { 0x00000000, 0x00400000, 0x000 }, +- { 0x00000000, 0x00600000, 0x28c }, ++ { 0x00000000, 0x00600000, 0x287 }, + { 0x00000000, 0xc0200800, 0x000 }, + { 0x0000001f, 0x00210e22, 0x000 }, + { 0x00000000, 0x14e00000, 0x000 }, +@@ -529,46 +526,46 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0x8400ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, + { 0x00000000, 0x21000000, 0x000 }, +- { 0x00000000, 0x00400000, 0x1de }, ++ { 0x00000000, 0x00400000, 0x1d9 }, + { 0x8200ffff, 0x00204411, 0x000 }, + { 0x00000001, 0x00204811, 0x000 }, + { 0x00000000, 0xc0200800, 0x000 }, + { 0x00003fff, 0x40280e20, 0x000 }, + { 0x00000010, 0xc0211220, 0x000 }, + { 0x00000000, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x1fb }, +- { 0x00000000, 0x2ae00000, 0x205 }, ++ { 0x00000000, 0x0ae00000, 0x1f6 }, ++ { 0x00000000, 0x2ae00000, 0x200 }, + { 0x20000080, 0x00281e2e, 0x000 }, + { 0x00000080, 0x002f0227, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x1f8 }, +- { 0x00000000, 0x00401c0c, 0x1f9 }, ++ { 0x00000000, 0x0ce00000, 0x1f3 }, ++ { 0x00000000, 0x00401c0c, 0x1f4 }, + { 0x00000010, 0x00201e2d, 0x000 }, + { 0x000021f9, 0x00294627, 0x000 }, +- { 0x00000000, 0x00404811, 0x205 }, ++ { 0x00000000, 0x00404811, 0x200 }, + { 0x00000001, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x23a }, +- { 0x00000000, 0x28e00000, 0x205 }, ++ { 0x00000000, 0x0ae00000, 0x235 }, ++ { 0x00000000, 0x28e00000, 0x200 }, + { 0x00800080, 0x00281e2e, 0x000 }, + { 0x00000080, 0x002f0227, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x202 }, +- { 0x00000000, 0x00401c0c, 0x203 }, ++ { 0x00000000, 0x0ce00000, 0x1fd }, ++ { 0x00000000, 0x00401c0c, 0x1fe }, + { 0x00000010, 0x00201e2d, 0x000 }, + { 0x000021f9, 0x00294627, 0x000 }, + { 0x00000001, 0x00204811, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x20c }, ++ { 0x00000000, 0x0ae00000, 0x207 }, + { 0x00000003, 0x00204811, 0x000 }, + { 0x0000000c, 0x0020162d, 0x000 }, + { 0x0000000d, 0x00201a2d, 0x000 }, +- { 0xffdfffff, 0x00483a2e, 0x210 }, ++ { 0xffdfffff, 0x00483a2e, 0x20b }, + { 0x00000004, 0x00204811, 0x000 }, + { 0x0000000e, 0x0020162d, 0x000 }, + { 0x0000000f, 0x00201a2d, 0x000 }, + { 0xffefffff, 0x00283a2e, 0x000 }, + { 0x00000000, 0x00201c10, 0x000 }, + { 0x00000000, 0x002f0067, 0x000 }, +- { 0x00000000, 0x04e00000, 0x205 }, ++ { 0x00000000, 0x04e00000, 0x200 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000006, 0x00204811, 0x000 }, + { 0x8300ffff, 0x00204411, 0x000 }, +@@ -578,10 +575,10 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0x8400ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, + { 0x00000000, 0x21000000, 0x000 }, +- { 0x00000000, 0x00601010, 0x28c }, ++ { 0x00000000, 0x00601010, 0x287 }, + { 0x0000000c, 0x00221e24, 0x000 }, + { 0x00000000, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x22d }, ++ { 0x00000000, 0x0ae00000, 0x228 }, + { 0x20000000, 0x00293a2e, 0x000 }, + { 0x000021f7, 0x0029462c, 0x000 }, + { 0x00000000, 0x002948c7, 0x000 }, +@@ -594,7 +591,7 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0x00000000, 0x00204803, 0x000 }, + { 0x00000000, 0x23000000, 0x000 }, + { 0x8d00ffff, 0x00204411, 0x000 }, +- { 0x00000000, 0x00404803, 0x240 }, ++ { 0x00000000, 0x00404803, 0x23b }, + { 0x00800000, 0x00293a2e, 0x000 }, + { 0x000021f6, 0x0029462c, 0x000 }, + { 0x00000000, 0x002948c7, 0x000 }, +@@ -607,7 +604,7 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0x00000000, 0x00204803, 0x000 }, + { 0x00000000, 0x25000000, 0x000 }, + { 0x8e00ffff, 0x00204411, 0x000 }, +- { 0x00000000, 0x00404803, 0x240 }, ++ { 0x00000000, 0x00404803, 0x23b }, + { 0x8300ffff, 0x00204411, 0x000 }, + { 0x00000003, 0x00381224, 0x000 }, + { 0x00005000, 0x00304a24, 0x000 }, +@@ -621,37 +618,37 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000001, 0x00204811, 0x000 }, + { 0x00000001, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x24a }, ++ { 0x00000000, 0x0ae00000, 0x245 }, + { 0x000021f6, 0x0029122c, 0x000 }, +- { 0x00040000, 0x00494624, 0x24c }, ++ { 0x00040000, 0x00494624, 0x247 }, + { 0x000021f7, 0x0029122c, 0x000 }, + { 0x00040000, 0x00294624, 0x000 }, +- { 0x00000000, 0x00600000, 0x2ba }, ++ { 0x00000000, 0x00600000, 0x2b4 }, + { 0x00000000, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x252 }, ++ { 0x00000000, 0x0ce00000, 0x24d }, + { 0x00000001, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x252 }, +- { 0x00000000, 0x00481630, 0x258 }, ++ { 0x00000000, 0x0ce00000, 0x24d }, ++ { 0x00000000, 0x00481630, 0x253 }, + { 0x00000fff, 0x00281630, 0x000 }, + { 0x0000000c, 0x00211a30, 0x000 }, + { 0x00000fff, 0x00281a26, 0x000 }, + { 0x00000000, 0x002f0226, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x258 }, ++ { 0x00000000, 0x0ae00000, 0x253 }, + { 0x00000000, 0xc0400000, 0x000 }, +- { 0x00040d02, 0x00604411, 0x2ba }, ++ { 0x00040d02, 0x00604411, 0x2b4 }, + { 0x00000000, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x25d }, ++ { 0x00000000, 0x0ae00000, 0x258 }, + { 0x00000010, 0x00211e30, 0x000 }, +- { 0x00000fff, 0x00482630, 0x267 }, ++ { 0x00000fff, 0x00482630, 0x262 }, + { 0x00000001, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x261 }, ++ { 0x00000000, 0x0ae00000, 0x25c }, + { 0x00000fff, 0x00281e30, 0x000 }, +- { 0x00000200, 0x00402411, 0x267 }, ++ { 0x00000200, 0x00402411, 0x262 }, + { 0x00000000, 0x00281e30, 0x000 }, + { 0x00000010, 0x00212630, 0x000 }, + { 0x00000010, 0x00211a30, 0x000 }, + { 0x00000000, 0x002f0226, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x258 }, ++ { 0x00000000, 0x0ae00000, 0x253 }, + { 0x00000000, 0xc0400000, 0x000 }, + { 0x00000003, 0x00381625, 0x000 }, + { 0x00000003, 0x00381a26, 0x000 }, +@@ -662,13 +659,13 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0x00000000, 0xc0204800, 0x000 }, + { 0x00000000, 0x00204806, 0x000 }, + { 0x00005000, 0x00302225, 0x000 }, +- { 0x00040000, 0x00694628, 0x2ba }, ++ { 0x00040000, 0x00694628, 0x2b4 }, + { 0x00000001, 0x00302228, 0x000 }, + { 0x00000000, 0x00202810, 0x000 }, +- { 0x00040000, 0x00694628, 0x2ba }, ++ { 0x00040000, 0x00694628, 0x2b4 }, + { 0x00000001, 0x00302228, 0x000 }, + { 0x00000000, 0x00200810, 0x000 }, +- { 0x00040000, 0x00694628, 0x2ba }, ++ { 0x00040000, 0x00694628, 0x2b4 }, + { 0x00000001, 0x00302228, 0x000 }, + { 0x00000000, 0x00201410, 0x000 }, + { 0x0000060d, 0x00204411, 0x000 }, +@@ -678,39 +675,42 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0x00000000, 0x00204802, 0x000 }, + { 0x00000000, 0x00204805, 0x000 }, + { 0x00000000, 0x002f0128, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x282 }, ++ { 0x00000000, 0x0ae00000, 0x27d }, + { 0x00005000, 0x00302227, 0x000 }, + { 0x0000000c, 0x00300e23, 0x000 }, + { 0x00000003, 0x00331a26, 0x000 }, + { 0x00000000, 0x002f0226, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x270 }, ++ { 0x00000000, 0x0ae00000, 0x26b }, + { 0x00000000, 0x00400000, 0x000 }, + { 0x000001f3, 0x00204411, 0x000 }, + { 0x04000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00400000, 0x289 }, +- { 0x00000000, 0xc0600000, 0x28c }, ++ { 0x00000000, 0x00400000, 0x284 }, ++ { 0x00000000, 0xc0600000, 0x287 }, + { 0x00000000, 0x00400000, 0x000 }, +- { 0x00000000, 0x0ec00000, 0x28e }, ++ { 0x00000000, 0x0ec00000, 0x289 }, + { 0x00000000, 0x00800000, 0x000 }, + { 0x000021f9, 0x0029462c, 0x000 }, + { 0x00000005, 0x00204811, 0x000 }, ++ { 0x8100ffff, 0x00204411, 0x000 }, ++ { 0x00000002, 0x00204811, 0x000 }, ++ { 0x0000000a, 0x0021262c, 0x000 }, ++ { 0x00000000, 0x00210130, 0x000 }, ++ { 0x00000000, 0x14c00000, 0x292 }, ++ { 0xa500ffff, 0x00204411, 0x000 }, ++ { 0x00000001, 0x00404811, 0x28e }, + { 0x00000000, 0x0020280c, 0x000 }, + { 0x00000011, 0x0020262d, 0x000 }, + { 0x00000000, 0x002f012c, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x295 }, +- { 0x00000000, 0x00403011, 0x296 }, ++ { 0x00000000, 0x0ae00000, 0x297 }, ++ { 0x00000000, 0x00403011, 0x298 }, + { 0x00000400, 0x0030322c, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000002, 0x00204811, 0x000 }, + { 0x0000000a, 0x0021262c, 0x000 }, + { 0x00000000, 0x00210130, 0x000 }, +- { 0x00000000, 0x14c00000, 0x29d }, ++ { 0x00000000, 0x14c00000, 0x29f }, + { 0xa500ffff, 0x00204411, 0x000 }, +- { 0x00000001, 0x00404811, 0x299 }, +- { 0x8100ffff, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00042294, 0x00604411, 0x2ba }, +- { 0x00000000, 0x00200010, 0x000 }, ++ { 0x00000001, 0x00404811, 0x29b }, + { 0xa500ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204811, 0x000 }, + { 0x000021f4, 0x0029462c, 0x000 }, +@@ -721,11 +721,9 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0x00000002, 0x00204811, 0x000 }, + { 0x00000000, 0x00210130, 0x000 }, + { 0xdf7fffff, 0x00283a2e, 0x000 }, +- { 0x8100ffff, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00042294, 0x00604411, 0x2ba }, +- { 0x00000000, 0x00200010, 0x000 }, + { 0x00000010, 0x0080362a, 0x000 }, ++ { 0x00000000, 0x00203011, 0x000 }, ++ { 0x00000010, 0x0080362c, 0x000 }, + { 0x9700ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x0020480c, 0x000 }, + { 0xa200ffff, 0x00204411, 0x000 }, +@@ -733,13 +731,11 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000002, 0x00204811, 0x000 }, + { 0x00000000, 0x00810130, 0x000 }, +- { 0x00000000, 0x00203011, 0x000 }, +- { 0x00000010, 0x0080362c, 0x000 }, + { 0x00000000, 0xc0400000, 0x000 }, +- { 0x00000000, 0x1ac00000, 0x2ba }, ++ { 0x00000000, 0x1ac00000, 0x2b4 }, + { 0x9f00ffff, 0x00204411, 0x000 }, + { 0xdeadbeef, 0x00204811, 0x000 }, +- { 0x00000000, 0x1ae00000, 0x2bd }, ++ { 0x00000000, 0x1ae00000, 0x2b7 }, + { 0x00000000, 0x00800000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, +@@ -778,26 +774,32 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, +- { 0x00020143, 0x00020002, 0x000 }, ++ { 0x00000000, 0x00000000, 0x000 }, ++ { 0x00000000, 0x00000000, 0x000 }, ++ { 0x00000000, 0x00000000, 0x000 }, ++ { 0x00000000, 0x00000000, 0x000 }, ++ { 0x00000000, 0x00000000, 0x000 }, ++ { 0x00000000, 0x00000000, 0x000 }, ++ { 0x0002013e, 0x00020002, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, +- { 0x00020002, 0x01dd0002, 0x000 }, +- { 0x006301ee, 0x00280012, 0x000 }, ++ { 0x00020002, 0x01d80002, 0x000 }, ++ { 0x005e01e9, 0x00280012, 0x000 }, + { 0x00020002, 0x00020026, 0x000 }, +- { 0x00020002, 0x01ec0002, 0x000 }, +- { 0x00790242, 0x00020002, 0x000 }, ++ { 0x00020002, 0x01e70002, 0x000 }, ++ { 0x0074023d, 0x00020002, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, + { 0x00200012, 0x00020016, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, +- { 0x011b00c5, 0x00020125, 0x000 }, +- { 0x00020141, 0x00020002, 0x000 }, +- { 0x00c50002, 0x0143002e, 0x000 }, +- { 0x00a2016b, 0x00020145, 0x000 }, +- { 0x00020002, 0x01200002, 0x000 }, +- { 0x00020002, 0x010f0103, 0x000 }, ++ { 0x011600c0, 0x00020120, 0x000 }, ++ { 0x0002013c, 0x00020002, 0x000 }, ++ { 0x00c00002, 0x013e002e, 0x000 }, ++ { 0x009d0166, 0x00020140, 0x000 }, ++ { 0x00020002, 0x011b0002, 0x000 }, ++ { 0x00020002, 0x010a00fe, 0x000 }, + { 0x00090002, 0x000e000e, 0x000 }, +- { 0x0058003d, 0x00600002, 0x000 }, +- { 0x000200c1, 0x0002028a, 0x000 }, ++ { 0x0049003d, 0x005b0002, 0x000 }, ++ { 0x000200bc, 0x00020285, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, +@@ -805,7 +807,7 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0x00020002, 0x00020002, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, +- { 0x000502b9, 0x00020008, 0x000 }, ++ { 0x000502b3, 0x00020008, 0x000 }, + }; + + #endif +@@ -813,4 +815,3 @@ static const uint32 ME_JUMP_TABLE_START = 740; + static const uint32 ME_JUMP_TABLE_END = 768; + + #endif +- +-- +1.5.4.4 + diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx/1140-ENGR00162711-DA9053-Add-dummy-write-for-DA9053-I2C.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1140-ENGR00162711-DA9053-Add-dummy-write-for-DA9053-I2C.patch new file mode 100755 index 00000000..908a3608 --- /dev/null +++ b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1140-ENGR00162711-DA9053-Add-dummy-write-for-DA9053-I2C.patch @@ -0,0 +1,434 @@ +From 7c0c7fc3189f456f1899bf4aa0a27e3f71f6a808 Mon Sep 17 00:00:00 2001 +From: Wayne Zou +Date: Mon, 21 Nov 2011 14:44:33 +0800 +Subject: [PATCH] ENGR00162711 DA9053: Add dummy write for DA9053 I2C register access + +DA9053 i2c issue: Rarely the i2c interface of DA9053 hang and it can +not be recovered if not power off totally. The Dialog suggests adding +dummy write for DA9053 I2C register access, in order to decrease the failure +of DA9053 register access and possibility of i2c failure. + +Signed-off-by: Wayne Zou +(cherry picked from commit bfd7cba1eeb46977b18a3c5fa65d812817a8294d) +--- + drivers/mfd/da9052-i2c.c | 317 ++++++++++++++++++++++++---------------------- + 1 files changed, 166 insertions(+), 151 deletions(-) + +diff --git a/drivers/mfd/da9052-i2c.c b/drivers/mfd/da9052-i2c.c +index 6209e97..457523f 100644 +--- a/drivers/mfd/da9052-i2c.c ++++ b/drivers/mfd/da9052-i2c.c +@@ -19,6 +19,8 @@ static struct da9052 *da9052_i2c; + + #define I2C_CONNECTED 0 + ++#define DA9052_I2C_BUG_WORKAROUND ++ + static int da9052_i2c_is_connected(void) + { + struct da9052_ssc_msg msg; +@@ -76,6 +78,15 @@ static int __devinit da9052_i2c_probe(struct i2c_client *client, + + /* Validate I2C connectivity */ + if ( I2C_CONNECTED == da9052_i2c_is_connected()) { ++ /* Enable Repeated Write Mode permanently */ ++ struct da9052_ssc_msg ctrl_msg = { ++ DA9052_CONTROLB_REG, DA9052_CONTROLB_WRITEMODE}; ++ if (da9052_i2c_write(da9052_i2c, &ctrl_msg) < 0) { ++ dev_info(&da9052_i2c->i2c_client->dev, ++ "%s: repeated mode not set!!\n", __func__); ++ return -ENODEV; ++ } ++ + /* I2C is connected */ + da9052_i2c->connecting_device = I2C; + if( 0!= da9052_ssc_init(da9052_i2c) ) +@@ -100,27 +111,59 @@ static int da9052_i2c_remove(struct i2c_client *client) + return 0; + } + ++#ifdef DA9052_I2C_BUG_WORKAROUND ++const unsigned char i2c_flush_data[] = {0xFF, 0xFF}; ++static const char safe_table[256] = { ++ [DA9052_STATUSA_REG] = 1, ++ [DA9052_STATUSB_REG] = 1, ++ [DA9052_STATUSC_REG] = 1, ++ [DA9052_STATUSD_REG] = 1, ++ [DA9052_ADCRESL_REG] = 1, ++ [DA9052_ADCRESH_REG] = 1, ++ [DA9052_VDDRES_REG] = 1, ++ [DA9052_ICHGAV_REG] = 1, ++ [DA9052_TBATRES_REG] = 1, ++ [DA9052_ADCIN4RES_REG] = 1, ++ [DA9052_ADCIN5RES_REG] = 1, ++ [DA9052_ADCIN6RES_REG] = 1, ++ [DA9052_TJUNCRES_REG] = 1, ++ [DA9052_TSIXMSB_REG] = 1, ++ [DA9052_TSIYMSB_REG] = 1, ++ [DA9052_TSILSB_REG] = 1, ++ [DA9052_TSIZMSB_REG] = 1, ++}; ++/* Enable safe register addresses */ ++static inline int da9052_is_i2c_reg_safe(unsigned char reg) ++{ ++ return safe_table[reg]; ++} ++#endif ++ + int da9052_i2c_write(struct da9052 *da9052, struct da9052_ssc_msg *msg) + { + struct i2c_msg i2cmsg; +- unsigned char buf[2] = {0}; ++ unsigned char buf[4] = {0}; + int ret = 0; + +- /* Copy the ssc msg to local character buffer */ +- buf[0] = msg->addr; +- buf[1] = msg->data; +- + /*Construct a i2c msg for a da9052 driver ssc message request */ + i2cmsg.addr = da9052->slave_addr; +- i2cmsg.len = 2; + i2cmsg.buf = buf; +- +- /* To write the data on I2C set flag to zero */ + i2cmsg.flags = 0; ++ i2cmsg.len = 2; ++ ++ /* Copy the ssc msg and additional data to flush chip I2C registers */ ++ buf[0] = msg->addr; ++ buf[1] = msg->data; + ++#ifdef DA9052_I2C_BUG_WORKAROUND ++ if (!da9052_is_i2c_reg_safe(msg->addr)) { ++ i2cmsg.len = 4; ++ buf[2] = i2c_flush_data[0]; ++ buf[3] = i2c_flush_data[1]; ++ } ++#endif + /* Start the i2c transfer by calling host i2c driver function */ + ret = i2c_transfer(da9052->adapter, &i2cmsg, 1); +- + if (ret < 0) { + dev_info(&da9052->i2c_client->dev,\ + "_%s:master_xfer Failed!!\n", __func__); +@@ -132,10 +175,8 @@ int da9052_i2c_write(struct da9052 *da9052, struct da9052_ssc_msg *msg) + + int da9052_i2c_read(struct da9052 *da9052, struct da9052_ssc_msg *msg) + { +- +- /*Get the da9052_i2c client details*/ + unsigned char buf[2] = {0, 0}; +- struct i2c_msg i2cmsg[2]; ++ struct i2c_msg i2cmsg[3]; + int ret = 0; + + /* Copy SSC Msg to local character buffer */ +@@ -145,107 +186,82 @@ int da9052_i2c_read(struct da9052 *da9052, struct da9052_ssc_msg *msg) + i2cmsg[0].addr = da9052->slave_addr ; + i2cmsg[0].len = 1; + i2cmsg[0].buf = &buf[0]; +- +- /*To write the data on I2C set flag to zero */ + i2cmsg[0].flags = 0; + +- /* Read the data from da9052*/ + /*Construct a i2c msg for a da9052 driver ssc message request */ + i2cmsg[1].addr = da9052->slave_addr ; + i2cmsg[1].len = 1; + i2cmsg[1].buf = &buf[1]; +- +- /*To read the data on I2C set flag to I2C_M_RD */ + i2cmsg[1].flags = I2C_M_RD; + +- /* Start the i2c transfer by calling host i2c driver function */ ++ /* Standard read transfer */ + ret = i2c_transfer(da9052->adapter, i2cmsg, 2); ++ ++#ifdef DA9052_I2C_BUG_WORKAROUND ++ if (!da9052_is_i2c_reg_safe(msg->addr)) { ++ /* Prepare additional message to flush chip I2C registers */ ++ i2cmsg[2].addr = da9052->slave_addr; ++ i2cmsg[2].len = 2; ++ i2cmsg[2].flags = 0; /* Write operation */ ++ i2cmsg[2].buf = (unsigned char *)i2c_flush_data; ++ ++ /* Read transfer with additional flush write */ ++ ret = i2c_transfer(da9052->adapter, &i2cmsg[2], 1); ++ } ++#endif ++ + if (ret < 0) { +- dev_info(&da9052->i2c_client->dev,\ +- "2 - %s:master_xfer Failed!!\n", __func__); ++ dev_info(&da9052->i2c_client->dev, ++ "2 - %s:master_xfer Failed!!\n", __func__); + return ret; + } + +- msg->data = *i2cmsg[1].buf; +- ++ msg->data = buf[1]; + return 0; + } + + int da9052_i2c_write_many(struct da9052 *da9052, + struct da9052_ssc_msg *sscmsg, int msg_no) + { +- + struct i2c_msg i2cmsg; +- unsigned char data_buf[MAX_READ_WRITE_CNT+1]; +- struct da9052_ssc_msg ctrlb_msg; +- struct da9052_ssc_msg *msg_queue = sscmsg; + int ret = 0; +- /* Flag to check if requested registers are contiguous */ +- unsigned char cont_data = 1; +- unsigned char cnt = 0; +- +- /* Check if requested registers are contiguous */ +- for (cnt = 1; cnt < msg_no; cnt++) { +- if ((msg_queue[cnt].addr - msg_queue[cnt-1].addr) != 1) { +- /* Difference is not 1, i.e. non-contiguous registers */ +- cont_data = 0; +- break; +- } +- } +- +- if (cont_data == 0) { +- /* Requested registers are non-contiguous */ +- for (cnt = 0; cnt < msg_no; cnt++) { +- ret = da9052->write(da9052, &msg_queue[cnt]); +- if (ret != 0) +- return ret; +- } +- return 0; +- } +- /* +- * Requested registers are contiguous +- * or PAGE WRITE sequence of I2C transactions is as below +- * (slave_addr + reg_addr + data_1 + data_2 + ...) +- * First read current WRITE MODE via CONTROL_B register of DA9052 +- */ +- ctrlb_msg.addr = DA9052_CONTROLB_REG; +- ctrlb_msg.data = 0x0; +- ret = da9052->read(da9052, &ctrlb_msg); +- +- if (ret != 0) +- return ret; +- +- /* Check if PAGE WRITE mode is set */ +- if (ctrlb_msg.data & DA9052_CONTROLB_WRITEMODE) { +- /* REPEAT WRITE mode is configured */ +- /* Now set DA9052 into PAGE WRITE mode */ +- ctrlb_msg.data &= ~DA9052_CONTROLB_WRITEMODE; +- ret = da9052->write(da9052, &ctrlb_msg); +- +- if (ret != 0) +- return ret; +- } +- +- /* Put first register address */ +- data_buf[0] = msg_queue[0].addr; +- +- for (cnt = 0; cnt < msg_no; cnt++) +- data_buf[cnt+1] = msg_queue[cnt].data; +- +- /* Construct a i2c msg for PAGE WRITE */ ++ int safe = 1; ++ unsigned char *data_ptr; ++#ifdef DA9052_I2C_BUG_WORKAROUND ++ unsigned char data_buf[2 * MAX_READ_WRITE_CNT + 2]; ++#else ++ unsigned char data_buf[2 * MAX_READ_WRITE_CNT]; ++#endif ++ ++ BUG_ON(msg_no < 0); ++ BUG_ON(msg_no >= MAX_READ_WRITE_CNT); ++ ++ /* Construct a i2c msg for REPEATED WRITE */ + i2cmsg.addr = da9052->slave_addr ; +- /* First register address + all data*/ +- i2cmsg.len = (msg_no + 1); ++ i2cmsg.len = 2*msg_no; + i2cmsg.buf = data_buf; +- +- /*To write the data on I2C set flag to zero */ + i2cmsg.flags = 0; + ++ for (data_ptr = data_buf; msg_no; msg_no--) { ++ safe &= da9052_is_i2c_reg_safe(sscmsg->addr); ++ *(data_ptr++) = sscmsg->addr; ++ *(data_ptr++) = sscmsg->data; ++ sscmsg++; ++ } ++#ifdef DA9052_I2C_BUG_WORKAROUND ++ if (!safe) { ++ i2cmsg.len += 2; ++ *(data_ptr++) = i2c_flush_data[0]; ++ *data_ptr = i2c_flush_data[1]; ++ } ++#endif ++ + /* Start the i2c transfer by calling host i2c driver function */ + ret = i2c_transfer(da9052->adapter, &i2cmsg, 1); + if (ret < 0) { +- dev_info(&da9052->i2c_client->dev,\ +- "1 - i2c_transfer function falied in [%s]!!!\n", __func__); ++ dev_info(&da9052->i2c_client->dev, ++ "1 - i2c_transfer function falied in [%s]!!!\n", ++ __func__); + return ret; + } + +@@ -255,83 +271,82 @@ int da9052_i2c_write_many(struct da9052 *da9052, + int da9052_i2c_read_many(struct da9052 *da9052, + struct da9052_ssc_msg *sscmsg, int msg_no) + { +- +- struct i2c_msg i2cmsg; ++#ifdef DA9052_I2C_BUG_WORKAROUND ++ struct i2c_msg i2cmsg[2 * MAX_READ_WRITE_CNT]; ++#else ++ struct i2c_msg i2cmsg[2 * MAX_READ_WRITE_CNT + 1]; ++#endif + unsigned char data_buf[MAX_READ_WRITE_CNT]; +- struct da9052_ssc_msg *msg_queue = sscmsg; ++ struct i2c_msg *msg_ptr = i2cmsg; + int ret = 0; +- /* Flag to check if requested registers are contiguous */ +- unsigned char cont_data = 1; +- unsigned char cnt = 0; +- +- /* Check if requested registers are contiguous */ +- for (cnt = 1; cnt < msg_no; cnt++) { +- if ((msg_queue[cnt].addr - msg_queue[cnt-1].addr) != 1) { +- /* Difference is not 1, i.e. non-contiguous registers */ +- cont_data = 0; +- break; ++ int safe = 1; ++ int last_reg_read = -2; ++ int cnt; ++ ++ BUG_ON(msg_no < 0); ++ BUG_ON(msg_no >= MAX_READ_WRITE_CNT); ++ ++ /* Construct a i2c msgs for a da9052 driver ssc message request */ ++ for (cnt = 0; cnt < msg_no; cnt++) { ++ if ((int)sscmsg[cnt].addr != last_reg_read + 1) { ++ safe &= da9052_is_i2c_reg_safe(sscmsg[cnt].addr); ++ ++ /* Build messages for first register, read in a row */ ++ msg_ptr->addr = da9052->slave_addr; ++ msg_ptr->len = 1; ++ msg_ptr->buf = &sscmsg[cnt].addr; ++ msg_ptr->flags = 0; ++ msg_ptr++; ++ ++ msg_ptr->addr = da9052->slave_addr; ++ msg_ptr->len = 1; ++ msg_ptr->buf = &data_buf[cnt]; ++ msg_ptr->flags = I2C_M_RD; ++ msg_ptr++; ++ ++ last_reg_read = sscmsg[cnt].addr; ++ } else { ++ /* Increase read counter for consecutive reads */ ++ (msg_ptr - 1)->len++; + } + } + +- if (cont_data == 0) { +- /* Requested registers are non-contiguous */ +- for (cnt = 0; cnt < msg_no; cnt++) { +- ret = da9052->read(da9052, &msg_queue[cnt]); +- if (ret != 0) { +- dev_info(&da9052->i2c_client->dev,\ +- "Error in %s", __func__); +- return ret; +- } +- } +- return 0; ++#ifdef DA9052_I2C_BUG_WORKAROUND ++ if (!safe) { ++ /* Prepare additional message to flush chip I2C registers */ ++ msg_ptr->addr = da9052->slave_addr; ++ msg_ptr->len = 2; ++ msg_ptr->flags = 0; /* Write operation */ ++ msg_ptr->buf = (unsigned char *)i2c_flush_data; ++ msg_ptr++; + } +- +- /* +- * We want to perform PAGE READ via I2C +- * For PAGE READ sequence of I2C transactions is as below +- * (slave_addr + reg_addr) + (slave_addr + data_1 + data_2 + ...) +- */ +- /* Copy address of first register */ +- data_buf[0] = msg_queue[0].addr; +- +- /* Construct a i2c msg for first transaction of PAGE READ i.e. write */ +- i2cmsg.addr = da9052->slave_addr ; +- i2cmsg.len = 1; +- i2cmsg.buf = data_buf; +- +- /*To write the data on I2C set flag to zero */ +- i2cmsg.flags = 0; +- +- /* Start the i2c transfer by calling host i2c driver function */ +- ret = i2c_transfer(da9052->adapter, &i2cmsg, 1); +- if (ret < 0) { +- dev_info(&da9052->i2c_client->dev,\ +- "1 - i2c_transfer function falied in [%s]!!!\n", __func__); +- return ret; ++#endif ++ ++ /* Using one transfer seems not to work well with D9052. ++ * Read transfer with additional flush write ++ * Performing many transfers is stable on D9052 ++ */ ++ for (cnt = 0; cnt < (msg_ptr - i2cmsg) - 1; cnt += 2) { ++ ret = i2c_transfer(da9052->adapter, &i2cmsg[cnt], 2); ++ if (ret < 0) { ++ dev_info(&da9052->i2c_client->dev, ++ "2 - %s:master_xfer Failed on msg[%d]!!\n", ++ __func__, cnt); ++ return ret; ++ } + } +- +- /* Now Read the data from da9052 */ +- /* Construct a i2c msg for second transaction of PAGE READ i.e. read */ +- i2cmsg.addr = da9052->slave_addr ; +- i2cmsg.len = msg_no; +- i2cmsg.buf = data_buf; +- +- /*To read the data on I2C set flag to I2C_M_RD */ +- i2cmsg.flags = I2C_M_RD; +- +- /* Start the i2c transfer by calling host i2c driver function */ +- ret = i2c_transfer(da9052->adapter, +- &i2cmsg, 1); +- if (ret < 0) { +- dev_info(&da9052->i2c_client->dev,\ +- "2 - i2c_transfer function falied in [%s]!!!\n", __func__); +- return ret; ++ if (cnt < (msg_ptr - i2cmsg)) { ++ ret = i2c_transfer(da9052->adapter, &i2cmsg[cnt], 1); ++ if (ret < 0) { ++ dev_info(&da9052->i2c_client->dev, ++ "2 - %s:master_xfer Failed on msg[%d]!!\n", ++ __func__, cnt); ++ return ret; ++ } + } + +- /* Gather READ data */ + for (cnt = 0; cnt < msg_no; cnt++) + sscmsg[cnt].data = data_buf[cnt]; +- + return 0; + } + +-- +1.5.4.4 + diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx/1141-ENGR00162708-MX5-Add-I2C-dummy-write-and-mask-nONKE.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1141-ENGR00162708-MX5-Add-I2C-dummy-write-and-mask-nONKE.patch new file mode 100755 index 00000000..9244dbff --- /dev/null +++ b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1141-ENGR00162708-MX5-Add-I2C-dummy-write-and-mask-nONKE.patch @@ -0,0 +1,86 @@ +From 3bc50cddbc5bc8c20c3bac50794a7ec80602ab16 Mon Sep 17 00:00:00 2001 +From: Wayne Zou +Date: Mon, 21 Nov 2011 15:06:54 +0800 +Subject: [PATCH] ENGR00162708 MX5: Add I2C dummy write and mask nONKEY event for i2c operation + +MX5: Add I2C dummy write when acessing DA9053 registers and mask nONKEY event +for i2c operation before suspend + +Signed-off-by: Wayne Zou +(cherry picked from commit 0cc56da7dc91bbd5b6e9a51c1576daedce36093c) +--- + arch/arm/mach-mx5/pm_da9053.c | 22 +++++++++++++++++++--- + 1 files changed, 19 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/mach-mx5/pm_da9053.c b/arch/arm/mach-mx5/pm_da9053.c +index 63eda3a..7bb8915 100644 +--- a/arch/arm/mach-mx5/pm_da9053.c ++++ b/arch/arm/mach-mx5/pm_da9053.c +@@ -60,6 +60,7 @@ as the normal setting on Da9053 */ + #define DA9052_GPIO0809_SMD_SET 0x18 + #define DA9052_ID1415_SMD_SET 0x1 + #define DA9052_GPI9_IRQ_MASK 0x2 ++#define DA9052_IRQ_MASKB_ONKEY 0x1 + + static u8 volt_settings[DA9052_LDO10_REG - DA9052_BUCKCORE_REG + 1]; + extern int pm_i2c_imx_xfer(struct i2c_msg *msgs, int num); +@@ -67,7 +68,8 @@ extern int pm_i2c_imx_xfer(struct i2c_msg *msgs, int num); + static void pm_da9053_read_reg(u8 reg, u8 *value) + { + unsigned char buf[2] = {0, 0}; +- struct i2c_msg i2cmsg[2]; ++ unsigned char dummy[2] = {0xff, 0xff}; ++ struct i2c_msg i2cmsg[3]; + buf[0] = reg; + i2cmsg[0].addr = 0x48 ; + i2cmsg[0].len = 1; +@@ -83,16 +85,22 @@ static void pm_da9053_read_reg(u8 reg, u8 *value) + + pm_i2c_imx_xfer(i2cmsg, 2); + *value = buf[1]; ++ ++ i2cmsg[2].addr = 0x48 ; ++ i2cmsg[2].len = 2; ++ i2cmsg[2].buf = &dummy[0]; ++ i2cmsg[2].flags = 0; ++ pm_i2c_imx_xfer(i2cmsg, 1); + } + + static void pm_da9053_write_reg(u8 reg, u8 value) + { +- unsigned char buf[2] = {0, 0}; ++ unsigned char buf[4] = {0, 0, 0xff, 0xff}; + struct i2c_msg i2cmsg[2]; + buf[0] = reg; + buf[1] = value; + i2cmsg[0].addr = 0x48 ; +- i2cmsg[0].len = 2; ++ i2cmsg[0].len = 4; + i2cmsg[0].buf = &buf[0]; + i2cmsg[0].flags = 0; + pm_i2c_imx_xfer(i2cmsg, 1); +@@ -172,6 +180,10 @@ int da9053_suspend_cmd_hw(void) + } + clk_enable(i2c_clk); + ++ pm_da9053_read_reg(DA9052_IRQMASKB_REG, &data); ++ data |= DA9052_IRQ_MASKB_ONKEY; ++ pm_da9053_write_reg(DA9052_IRQMASKB_REG, data); ++ + pm_da9053_preset_voltage(); + pm_da9053_write_reg(DA9052_CONTROLC_REG, + DA9052_CONTROLC_SMD_SET); +@@ -194,6 +206,10 @@ int da9053_suspend_cmd_hw(void) + pm_da9053_write_reg(DA9052_SEQTIMER_REG, 0); + /* pm_da9053_write_reg(DA9052_SEQB_REG, 0x1f); */ + ++ pm_da9053_read_reg(DA9052_IRQMASKB_REG, &data); ++ data &= ~DA9052_IRQ_MASKB_ONKEY; ++ pm_da9053_write_reg(DA9052_IRQMASKB_REG, data); ++ + clk_disable(i2c_clk); + clk_put(i2c_clk); + return 0; +-- +1.5.4.4 + diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx/1142-ENGR00163698-MX53-ARD-fix-typo-error-for-pwm1-pad-d.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1142-ENGR00163698-MX53-ARD-fix-typo-error-for-pwm1-pad-d.patch new file mode 100755 index 00000000..5b17895f --- /dev/null +++ b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1142-ENGR00163698-MX53-ARD-fix-typo-error-for-pwm1-pad-d.patch @@ -0,0 +1,33 @@ +From bad1d7edba0addd5cb925d237242edbfbbf2f108 Mon Sep 17 00:00:00 2001 +From: Yuxi Sun +Date: Fri, 2 Dec 2011 11:12:28 +0800 +Subject: [PATCH] ENGR00163698 MX53 ARD: fix typo error for pwm1 pad disable function + +Fix typo error for pwm1 pad disable function. + +Signed-off-by: Yuxi Sun +(cherry picked from commit d04b2646528b586baeecc1f128508b5363e7ed63) +--- + arch/arm/mach-mx5/mx53_ard.c | 6 +++--- + 1 files changed, 3 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/mach-mx5/mx53_ard.c b/arch/arm/mach-mx5/mx53_ard.c +index 6550ca9..378e1c1 100644 +--- a/arch/arm/mach-mx5/mx53_ard.c ++++ b/arch/arm/mach-mx5/mx53_ard.c +@@ -393,9 +393,9 @@ static void disable_pwm1_pad(void) + { + mxc_iomux_v3_setup_pad(mx53_ard_pwm_pads[2]); + +- gpio_request(ARD_PWM2_OFF, "pwm2-off"); +- gpio_direction_output(ARD_PWM2_OFF, 1); +- gpio_free(ARD_PWM2_OFF); ++ gpio_request(ARD_PWM1_OFF, "pwm1-off"); ++ gpio_direction_output(ARD_PWM1_OFF, 1); ++ gpio_free(ARD_PWM1_OFF); + } + + static struct mxc_pwm_platform_data mxc_pwm1_platform_data = { +-- +1.5.4.4 + diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx/1143-ENGR00162578-DMA-mx5-increase-DMA-Zone-size-to-112.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1143-ENGR00162578-DMA-mx5-increase-DMA-Zone-size-to-112.patch new file mode 100755 index 00000000..cdbb0061 --- /dev/null +++ b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1143-ENGR00162578-DMA-mx5-increase-DMA-Zone-size-to-112.patch @@ -0,0 +1,109 @@ +From 690f2f35563a1f7a89b796f9b0e7996627dbda21 Mon Sep 17 00:00:00 2001 +From: Robin Gong +Date: Fri, 18 Nov 2011 10:52:32 +0800 +Subject: [PATCH] ENGR00162578 DMA mx5: increase DMA Zone size to 112 + +Increase DMA zone size from 96 to 112 size, and default size is 112, +change imx5_defconfig, change SPBA0_BASE_ADDR_VIRT from 0xFB100000 to +0xF7C00000 , so that it can't overlap with DMA zone +Signed-off-by: Robin Gong +(cherry picked from commit 2d04dcb9b717a7c46358987f41a03141eccc42b0) +--- + arch/arm/configs/imx5_defconfig | 7 ++++--- + arch/arm/plat-mxc/Kconfig | 4 ++-- + arch/arm/plat-mxc/include/mach/memory.h | 4 ++-- + arch/arm/plat-mxc/include/mach/mx5x.h | 2 +- + 4 files changed, 9 insertions(+), 8 deletions(-) + +diff --git a/arch/arm/configs/imx5_defconfig b/arch/arm/configs/imx5_defconfig +index 419adde..3a0cc96 100644 +--- a/arch/arm/configs/imx5_defconfig ++++ b/arch/arm/configs/imx5_defconfig +@@ -1,7 +1,7 @@ + # + # Automatically generated make config: don't edit + # Linux kernel version: 2.6.35.3 +-# Wed Jun 1 20:11:44 2011 ++# Fri Nov 18 10:24:37 2011 + # + CONFIG_ARM=y + CONFIG_HAVE_PWM=y +@@ -266,7 +266,7 @@ CONFIG_ARCH_MXC_HAS_NFC_V3=y + CONFIG_ARCH_MXC_HAS_NFC_V3_2=y + CONFIG_MXC_BLUETOOTH_RFKILL=y + CONFIG_IRAM_ALLOC=y +-CONFIG_DMA_ZONE_SIZE=96 ++CONFIG_DMA_ZONE_SIZE=112 + CONFIG_ISP1504_MXC=y + CONFIG_UTMI_MXC=y + # CONFIG_MXC_IRQ_PRIOR is not set +@@ -1230,9 +1230,9 @@ CONFIG_SENSORS_MAX17135=y + # CONFIG_SENSORS_W83627EHF is not set + # CONFIG_SENSORS_LIS3_SPI is not set + # CONFIG_SENSORS_LIS3_I2C is not set ++CONFIG_SENSORS_IMX_AHCI=y + CONFIG_SENSORS_MAG3110=y + CONFIG_SENSORS_ISL29003=y +-CONFIG_SENSORS_IMX_AHCI=y + CONFIG_MXC_MMA8450=y + CONFIG_MXC_MMA8451=y + # CONFIG_THERMAL is not set +@@ -2112,6 +2112,7 @@ CONFIG_MXC_MC13892_POWER=y + CONFIG_MXC_MC34708_ADC=y + CONFIG_MXC_MC34708_RTC=y + CONFIG_MXC_MC34708_BATTERY=m ++# CONFIG_MXC_MC34708_PWM is not set + # CONFIG_MXC_PMIC_MC9S08DZ60 is not set + + # +diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig +index 926379f..7a4412a 100644 +--- a/arch/arm/plat-mxc/Kconfig ++++ b/arch/arm/plat-mxc/Kconfig +@@ -87,8 +87,8 @@ config MXC_FB_IRAM + + config DMA_ZONE_SIZE + int "DMA memory zone size" +- range 0 96 +- default 24 ++ range 0 112 ++ default 112 + help + This is the size in MB for the DMA zone. The DMA zone is used for + dedicated memory for large contiguous video buffers +diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h +index 83532f6..2e66516 100644 +--- a/arch/arm/plat-mxc/include/mach/memory.h ++++ b/arch/arm/plat-mxc/include/mach/memory.h +@@ -1,5 +1,5 @@ + /* +- * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + + /* +@@ -63,7 +63,7 @@ + #else + + #ifdef CONFIG_ARCH_MX5 +-#define CONSISTENT_DMA_SIZE (96 * SZ_1M) ++#define CONSISTENT_DMA_SIZE (112 * SZ_1M) + #else + #define CONSISTENT_DMA_SIZE (32 * SZ_1M) + #endif +diff --git a/arch/arm/plat-mxc/include/mach/mx5x.h b/arch/arm/plat-mxc/include/mach/mx5x.h +index 5c16710..96f6686 100644 +--- a/arch/arm/plat-mxc/include/mach/mx5x.h ++++ b/arch/arm/plat-mxc/include/mach/mx5x.h +@@ -194,7 +194,7 @@ + * SPBA global module enabled #0 + */ + #define SPBA0_BASE_ADDR 0x70000000 +-#define SPBA0_BASE_ADDR_VIRT 0xFB100000 ++#define SPBA0_BASE_ADDR_VIRT 0xF7C00000 + #define SPBA0_SIZE SZ_1M + + #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) +-- +1.5.4.4 + diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx/1144-ENGR00169603-MX53-ARD-FlexCAN-Set-lp_apm-as-clock.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1144-ENGR00169603-MX53-ARD-FlexCAN-Set-lp_apm-as-clock.patch new file mode 100755 index 00000000..360902c7 --- /dev/null +++ b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1144-ENGR00169603-MX53-ARD-FlexCAN-Set-lp_apm-as-clock.patch @@ -0,0 +1,37 @@ +From a5baaf44b75b0bd6d3411fc87531ddfd411e34fb Mon Sep 17 00:00:00 2001 +From: Rogerio Pimentel +Date: Thu, 8 Dec 2011 16:33:41 -0200 +Subject: [PATCH] ENGR00169603 MX53 ARD: FlexCAN: Set lp_apm as clock source + +The FlexCAN clock source must be lp_apm (24MHZ) instead +ipg_clock_root (60MHZ) to meet automotive clock requirements. + +Signed-off-by: Rogerio Pimentel +(cherry picked from commit b7456a4f5f6fa12235effbffe4e4d1b62159b948) +--- + arch/arm/mach-mx5/mx53_ard.c | 2 ++ + 1 files changed, 2 insertions(+), 0 deletions(-) + +diff --git a/arch/arm/mach-mx5/mx53_ard.c b/arch/arm/mach-mx5/mx53_ard.c +index 378e1c1..b1252fb 100644 +--- a/arch/arm/mach-mx5/mx53_ard.c ++++ b/arch/arm/mach-mx5/mx53_ard.c +@@ -455,6 +455,7 @@ static void flexcan_xcvr_enable(int id, int en) + static struct flexcan_platform_data flexcan0_data = { + .core_reg = NULL, + .io_reg = NULL, ++ .root_clk_id = "lp_apm", + .xcvr_enable = flexcan_xcvr_enable, + .br_clksrc = 1, + .br_rjw = 2, +@@ -472,6 +473,7 @@ static struct flexcan_platform_data flexcan0_data = { + static struct flexcan_platform_data flexcan1_data = { + .core_reg = NULL, + .io_reg = NULL, ++ .root_clk_id = "lp_apm", + .xcvr_enable = flexcan_xcvr_enable, + .br_clksrc = 1, + .br_rjw = 2, +-- +1.5.4.4 + diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx/1145-ENGR00170342-PWM-fix-pwm-output-can-t-be-set-to-100.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1145-ENGR00170342-PWM-fix-pwm-output-can-t-be-set-to-100.patch new file mode 100755 index 00000000..095ab148 --- /dev/null +++ b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1145-ENGR00170342-PWM-fix-pwm-output-can-t-be-set-to-100.patch @@ -0,0 +1,35 @@ +From d1eff01309855f850d82e4ce9abe42ad76aa7f9f Mon Sep 17 00:00:00 2001 +From: Yuxi Sun +Date: Thu, 15 Dec 2011 10:12:53 +0800 +Subject: [PATCH] ENGR00170342 PWM: fix pwm output can't be set to 100% full duty + +The chip document says the counter counts up to period_cycles + 1 +and then is reset to 0, so the actual period of the PWM wave is +period_cycles + 2 + +Signed-off-by: Yuxi Sun +(cherry picked from commit e1465447502c77b2951af7ace43d8f76fa5039fb) +--- + arch/arm/plat-mxc/pwm.c | 6 +++++- + 1 files changed, 5 insertions(+), 1 deletions(-) + +diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c +index 2f8a35e..ccba298 100644 +--- a/arch/arm/plat-mxc/pwm.c ++++ b/arch/arm/plat-mxc/pwm.c +@@ -83,7 +83,11 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) + prescale = period_cycles / 0x10000 + 1; + + period_cycles /= prescale; +- c = (unsigned long long)period_cycles * duty_ns; ++ /* the chip document says the counter counts up to ++ * period_cycles + 1 and then is reset to 0, so the ++ * actual period of the PWM wave is period_cycles + 2 ++ */ ++ c = (unsigned long long)(period_cycles + 2) * duty_ns; + do_div(c, period_ns); + duty_cycles = c; + +-- +1.5.4.4 + diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx/1146-ENGR00170244-1-ARM-AHCI-Enable-PDDQ-mode-when-no-d.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1146-ENGR00170244-1-ARM-AHCI-Enable-PDDQ-mode-when-no-d.patch new file mode 100755 index 00000000..9a6def32 --- /dev/null +++ b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1146-ENGR00170244-1-ARM-AHCI-Enable-PDDQ-mode-when-no-d.patch @@ -0,0 +1,80 @@ +From 10df11bb736c8166e53b41f96688b2e6bd53773b Mon Sep 17 00:00:00 2001 +From: Richard Zhu +Date: Fri, 16 Dec 2011 10:08:04 +0800 +Subject: [PATCH] ENGR00170244-1 ARM: AHCI: Enable PDDQ mode when no disk is attached + +In order to save the power consumption, enable the +PDDQ mode of AHCI PHY when there is no sata disk +on the port + +Signed-off-by: Richard Zhu +(cherry picked from commit a53c29d7e484a3562e3a4f24d952485fbeb4c933) +--- + arch/arm/plat-mxc/ahci_sata.c | 30 ++++++++++++++++++++------- + arch/arm/plat-mxc/include/mach/ahci_sata.h | 1 + + 2 files changed, 23 insertions(+), 8 deletions(-) + +diff --git a/arch/arm/plat-mxc/ahci_sata.c b/arch/arm/plat-mxc/ahci_sata.c +index 466636b..76a2747 100644 +--- a/arch/arm/plat-mxc/ahci_sata.c ++++ b/arch/arm/plat-mxc/ahci_sata.c +@@ -156,7 +156,7 @@ static int sata_init(struct device *dev) + { + void __iomem *mmio; + u32 tmpdata; +- int ret = 0; ++ int ret = 0, iterations = 20; + struct clk *clk; + + sata_clk = clk_get(dev, "imx_sata_clk"); +@@ -281,14 +281,28 @@ static int sata_init(struct device *dev) + + if (AHCI_SAVE_PWR_WITHOUT_HOTPLUG) { + /* Release resources when there is no device on the port */ +- if ((readl(mmio + PORT_SATA_SR) & 0xF) == 0) { +- ret = -ENODEV; +- if (machine_is_mx53_smd() || machine_is_mx53_loco() +- || board_is_mx53_ard_b()) +- goto no_device; ++ do { ++ if ((readl(mmio + PORT_SATA_SR) & 0xF) == 0) ++ msleep(25); + else +- goto release_mem; +- } ++ break; ++ ++ if (iterations == 0) { ++ pr_info("No sata disk.\n"); ++ ret = -ENODEV; ++ /* Enter into PDDQ mode, save power */ ++ tmpdata = readl(mmio + PORT_PHY_CTL); ++ writel(tmpdata | PORT_PHY_CTL_PDDQ_LOC, ++ mmio + PORT_PHY_CTL); ++ ++ if (machine_is_mx53_smd() ++ || machine_is_mx53_loco() ++ || board_is_mx53_ard_b()) ++ goto no_device; ++ else ++ goto release_mem; ++ } ++ } while (iterations-- > 0); + } + + iounmap(mmio); +diff --git a/arch/arm/plat-mxc/include/mach/ahci_sata.h b/arch/arm/plat-mxc/include/mach/ahci_sata.h +index ea68a19..e31797b 100644 +--- a/arch/arm/plat-mxc/include/mach/ahci_sata.h ++++ b/arch/arm/plat-mxc/include/mach/ahci_sata.h +@@ -37,6 +37,7 @@ enum { + PORT_PHY_CTL_CAP_DAT_LOC = 0x20000, + PORT_PHY_CTL_WRITE_LOC = 0x40000, + PORT_PHY_CTL_READ_LOC = 0x80000, ++ PORT_PHY_CTL_PDDQ_LOC = 0x100000, + /* Port0 PHY Status */ + PORT_PHY_SR = 0x17c, + /* PORT_PHY_SR */ +-- +1.5.4.4 + diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx/1147-ENGR00170244-2-ARM-AHCI-Enable-PDDQ-mode-when-no-d.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1147-ENGR00170244-2-ARM-AHCI-Enable-PDDQ-mode-when-no-d.patch new file mode 100755 index 00000000..3b14b8de --- /dev/null +++ b/meta-fsl-arm/recipes-kernel/linux/linux-imx/1147-ENGR00170244-2-ARM-AHCI-Enable-PDDQ-mode-when-no-d.patch @@ -0,0 +1,53 @@ +From 3cb5c41657a793fd442766d076eddde06af9c9ce Mon Sep 17 00:00:00 2001 +From: Richard Zhu +Date: Fri, 16 Dec 2011 10:08:42 +0800 +Subject: [PATCH] ENGR00170244-2 ARM: AHCI: Enable PDDQ mode when no disk is attached + +In order to save the power consumption, enable the +PDDQ mode of AHCI PHY when there is no sata disk +on the port + +Signed-off-by: Richard Zhu +(cherry picked from commit f97994abf50e9917a959ae62eabd08908a75a222) +--- + drivers/hwmon/imx_ahci_hwmon.c | 10 ++++++++++ + 1 files changed, 10 insertions(+), 0 deletions(-) + +diff --git a/drivers/hwmon/imx_ahci_hwmon.c b/drivers/hwmon/imx_ahci_hwmon.c +index 62048f7..7688d92 100644 +--- a/drivers/hwmon/imx_ahci_hwmon.c ++++ b/drivers/hwmon/imx_ahci_hwmon.c +@@ -90,6 +90,11 @@ static ssize_t imx_ahci_hwmon_temp_show(struct device *dev, + return -1; + } + ++ /* Disable PDDQ mode when this mode is enabled */ ++ read_sum = readl(mmio + PORT_PHY_CTL); ++ if (read_sum & PORT_PHY_CTL_PDDQ_LOC) ++ writel(read_sum & ~PORT_PHY_CTL_PDDQ_LOC, mmio + PORT_PHY_CTL); ++ + /* check rd-wr to reg */ + read_sum = 0; + sata_phy_cr_addr(SATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT, mmio); +@@ -230,6 +235,10 @@ static ssize_t imx_ahci_hwmon_temp_show(struct device *dev, + a = (m2 - m1) / (m2 / 1000); + temp = ((((-559) * a) / 1000) * a) / 1000 + (1379) * a / 1000 + (-458); + ++ /* Enable PDDQ mode to save power */ ++ read_sum = readl(mmio + PORT_PHY_CTL); ++ writel(read_sum | PORT_PHY_CTL_PDDQ_LOC, mmio + PORT_PHY_CTL); ++ + iounmap(mmio); + + /* Release the clocks */ +@@ -237,6 +246,7 @@ static ssize_t imx_ahci_hwmon_temp_show(struct device *dev, + clk_put(sata_ref_clk); + clk_disable(sata_clk); + clk_put(sata_clk); ++ + mutex_unlock(&hwmon->lock); + + return sprintf(buf, "%d\n", temp * 1000); +-- +1.5.4.4 + diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx/imx53ard/defconfig b/meta-fsl-arm/recipes-kernel/linux/linux-imx/imx53ard/defconfig index 3e92c9f7..294a6a4c 100644 --- a/meta-fsl-arm/recipes-kernel/linux/linux-imx/imx53ard/defconfig +++ b/meta-fsl-arm/recipes-kernel/linux/linux-imx/imx53ard/defconfig @@ -265,7 +265,7 @@ CONFIG_ARCH_MXC_HAS_NFC_V3=y CONFIG_ARCH_MXC_HAS_NFC_V3_2=y CONFIG_MXC_BLUETOOTH_RFKILL=y CONFIG_IRAM_ALLOC=y -CONFIG_DMA_ZONE_SIZE=182 +CONFIG_DMA_ZONE_SIZE=112 CONFIG_ISP1504_MXC=y CONFIG_UTMI_MXC=y # CONFIG_MXC_IRQ_PRIOR is not set diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx/imx53qsb/defconfig b/meta-fsl-arm/recipes-kernel/linux/linux-imx/imx53qsb/defconfig index a1db9e0a..cdbafd56 100644 --- a/meta-fsl-arm/recipes-kernel/linux/linux-imx/imx53qsb/defconfig +++ b/meta-fsl-arm/recipes-kernel/linux/linux-imx/imx53qsb/defconfig @@ -266,7 +266,7 @@ CONFIG_ARCH_MXC_HAS_NFC_V3=y CONFIG_ARCH_MXC_HAS_NFC_V3_2=y CONFIG_MXC_BLUETOOTH_RFKILL=y CONFIG_IRAM_ALLOC=y -CONFIG_DMA_ZONE_SIZE=182 +CONFIG_DMA_ZONE_SIZE=112 CONFIG_ISP1504_MXC=y CONFIG_UTMI_MXC=y # CONFIG_MXC_IRQ_PRIOR is not set diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx_2.6.35.3.bb b/meta-fsl-arm/recipes-kernel/linux/linux-imx_2.6.35.3.bb index e2b51b44..97e7ac45 100644 --- a/meta-fsl-arm/recipes-kernel/linux/linux-imx_2.6.35.3.bb +++ b/meta-fsl-arm/recipes-kernel/linux/linux-imx_2.6.35.3.bb @@ -4,14 +4,14 @@ DESCRIPTION = "Linux kernel for imx platforms" LICENSE = "GPLv2" LIC_FILES_CHKSUM = "file://COPYING;md5=d7810fab7487fb0aad327b76f1be7cd7" -PR = "r7" +PR = "r8" inherit kernel COMPATIBLE_MACHINE = "(imx53qsb|imx53ard)" SRC_URI = "git://opensource.freescale.com/pub/scm/imx/linux-2.6-imx.git;tag=rel_imx_2.6.35_11.09.01;protocol=http \ file://egalax_ts-enable-single-event-support.patch \ - file://plat-mxc-double-dma-zone-max.patch \ + file://1143-ENGR00162578-DMA-mx5-increase-DMA-Zone-size-to-112.patch \ file://devtmpfs-init-options-alignment.patch \ file://defconfig \ "