Priyanka Jain [Mon, 27 Jan 2014 08:37:11 +0000 (14:07 +0530)]
powerpc/t104xrdb: Update T1040RDB.h in config folder
Add usb2 node entry in "hwconfig string"
Remove controller interleaving from hwconfig string as T1040
has only one DDR conroller
SPI related macros which were earlier under #ifdef CONFIG_SPIFLASH
are move outside so that they are defined for all cases as these
macros are also used by other u-boot code
Add CONFIG_SYS_CSPR2_EXT to make CPLD accessible
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
[York Sun: Minor change to commit message] Signed-off-by: York Sun <yorksun@freescale.com>
Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5
Define MDIO related configs
Added eth.c file
Update t1040.c to support RGMII and SGMII
Update t1040qds.c to support ethernet
Define the PHY address
Changes:
- check image bpp instead of resolution when returns logo address
- remove 32bpp logo
- add 16bpp logo in two formats: bmp and gzipped bmp
- init logo address with "0" for unsupported bpp mode
- update boards configs with proper image size for gunzip
- extend structure vidinfo by two fields: logo_x_offset and logo_y_offset.
Vivek Gautam [Fri, 3 Jan 2014 10:40:53 +0000 (16:10 +0530)]
smdk5250: Remove 'board_usb_vbus_init()' function
Previously as a part of moving the VBUS gpio support to device tree
following patch removed this and added relevant support in driver: 4a271cb exynos: usb: Switch USB VBUS GPIOs to be device tree configured
Recent changes for common board file migration for exynos platform
added it again. So removing it now.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Julius Werner <jwerner@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Vivek Gautam [Fri, 3 Jan 2014 10:40:52 +0000 (16:10 +0530)]
exynos5250: usb: Fix VBus gpio numbers for ehci and xhci controllers
The gpio_*() apis require the exact gpio line number to deduce
the gpio bank and the gpio pin addresses.
So fix the gpio number for VBUS used for EHCI ports as well as
XHCI ports on exynos5250 boards.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Julius Werner <jwerner@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Ezequiel Garcia [Tue, 28 Jan 2014 10:19:06 +0000 (07:19 -0300)]
board: nios2: Check if flash is configured before calling early_flash_cmd_reset()
If CONFIG_CFI_FLASH_MTD is not defined, then we shouldn't perform the
flash early reset.
This commit fixes the following build error:
nios2-generic.c: In function `__early_flash_cmd_reset':
nios2-generic.c:23: error: `AMD_CMD_RESET' undeclared (first use in this function)
nios2-generic.c:23: error: (Each undeclared identifier is reported only once
nios2-generic.c:23: error: for each function it appears in.)
nios2-generic.c:24: error: `FLASH_CMD_RESET' undeclared (first use in this function)
Alexey Brodkin [Mon, 20 Jan 2014 10:30:39 +0000 (14:30 +0400)]
board_r - fixup functions table after relocation
This is only required for "PIC" relocation and doesn't apply to modern
"PIE" relocation which does data relocation as well as code.
"init_sequence_r" is just an array that consists of compile-time
adresses of init functions. Since this is basically an array of integers
(pointers to "void" to be more precise) it won't be modified during
relocation - it will be just copied to new location as it is.
As a consequence on execution after relocation "initcall_run_list" will
be jumping to pre-relocation addresses. As long as we don't overwrite
pre-relocation memory area init calls are executed correctly. But still
it is dangerous because after relocation we don't expect initially used
memory to stay untouched.
Cc: Tom Rini <trini@ti.com> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Doug Anderson <dianders@chromium.org> Cc: Thomas Langer <thomas.langer@lantiq.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Marek Vasut [Sat, 14 Dec 2013 04:55:29 +0000 (05:55 +0100)]
ARM: mx6: Enable PCIe on Sabrelite
Enable PCI express on MX6 Sabrelite.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
Marek Vasut [Sat, 14 Dec 2013 04:55:28 +0000 (05:55 +0100)]
ARM: mx6: Add PCI express driver
Add PCIe driver for the Freescale i.MX6 SoC . This driver operates the
PCIe block in RC mode only, the EP mode is NOT supported. The driver is
tested with the Intel e1000 NIC driver.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
Marek Vasut [Sat, 14 Dec 2013 05:27:26 +0000 (06:27 +0100)]
ARM: mx6: Add PCI express clock configuration
Split the SATA clock enabling function and add PCI express clock
enabling function. The SATA clock enabling function starts up the
100MHz SATA reference PLL in ENET_PLL register, but the code can
be re-used to enable the 125MHz PCIe reference in ENET_PLL, so pull
this code into separate function. Moreover, add the PCIe clock
enabling code.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Marek Vasut [Sat, 14 Dec 2013 04:55:26 +0000 (05:55 +0100)]
ARM: armv7: Make indirect vector addresses globl
Make indirect vectors addresses global, so they can be replaced by
various code that needs to do so. For example the MX6 PCI express
driver needs to temporarily replace data abort handler when reading
the config space.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
Dan Murphy [Thu, 16 Jan 2014 17:23:30 +0000 (11:23 -0600)]
spl: common: Support for USB MSD FAT image loading
Add SPL support to be able to detect a USB Mass Storage device
connected to a USB host. Once a USB Mass storage device is detected
the SPL will load the u-boot.img from a FAT partition to target address.
Masahiro Yamada [Wed, 15 Jan 2014 02:00:45 +0000 (11:00 +0900)]
ARM: merge commonly-defined PLATFORM_RELFLAGS
Before this commit, all arch/arm/cpu/${CPU}/config.mk except ARMv8
had the same option:
$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
This commit moves it into arch/arm/config.mk.
If the compiler does not support the option,
it is ignored by $(call cc-option,...).
So this commit gives no harm to ARMv8.
We do not have to define CONFIG_4xx in board config headers
because it is defined in arch/powerpc/cpu/ppc4xx/config.mk.
include/configs/JSE.h defines "CONFIG_4x", not "CONFIG_4xx".
I believe it is a typo because "CONFIG_4x" is not used at all
in other files.
So, I also deleted "CONFIG_4x" in include/configs/JSE.h.
Masahiro Yamada [Tue, 14 Jan 2014 01:55:02 +0000 (10:55 +0900)]
board: tec-ng: Do not make directories in a board Makefile
Commit e5c5301f refactored the build system not to make
directories in board makefiles.
But commit 8f380381 create directories again in
board/avionic-design/tec-ng/Makefile.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Alban Bedel <alban.bedel@avionic-design.de>
Darwin Rambo [Thu, 19 Dec 2013 23:14:19 +0000 (15:14 -0800)]
lib: fix return codes when CONFIG_SYS_VSNPRINTF is enabled
When CONFIG_SYS_VSNPRINTF is enabled, it protects print operations
such as sprintf, snprintf, vsnprintf, etc., from buffer overflows.
But vsnprintf_internal includes the terminating NULL character in
the calculation of number of characters written. This affects sprintf
and snprintf return values. Fix this issue by setting pointer 'str'
back to the location of the '\0'.
Signed-off-by: Darwin Rambo <drambo@broadcom.com> Reviewed-by: Steve Rae <srae@broadcom.com>
Darwin Rambo [Thu, 19 Dec 2013 23:06:12 +0000 (15:06 -0800)]
lib: time: add weak timer_init() function
If timer_init() is made a weak stub function, then it allows us to
remove several empty timer_init functions for those boards that
already have a timer initialized when u-boot starts. Architectures
that use the timer framework may also remove the need for timer.c.
Signed-off-by: Darwin Rambo <drambo@broadcom.com> Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Nishanth Menon [Tue, 14 Jan 2014 18:27:29 +0000 (12:27 -0600)]
DRA7: add ABB setup for MPU voltage domain
Patch adds modification to shared omap5 abb_setup() function, and
proper registers definitions needed for ABB setup sequence. ABB is
initialized for MPU voltage domain at OPP_NOM.
Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
This patch enables dynamically powering down the
IO receiver when not performing a read on boards using DDR3.
This optimizes both active and standby power consumption.
This bit is not set on EVM SK and EVM 1.5 and later boards.
Setting the same.
This has been tested on PG2.0 EVM1.5, EVM1.2, EVM-SK, BBB.
Lokesh Vutla [Thu, 19 Dec 2013 04:30:28 +0000 (10:00 +0530)]
ARM: AM43xx: Enable DDR dynamic IO power down for DDR3
This patch enables dynamically powering down the
IO receiver when not performing a read on DDR3 board.
This optimizes both active and standby power consumption.
This is derived from a patch that is done on AM335x[1]
TI: OMAP3: Create common config files for TI OMAP3 platforms.
Create a new file, include/configs/ti_omap3_common.h, for everything
common to the OMAP3 SoC leaving just the board specific part to board
configuration file.
Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
ARM: OMAP3: Rename OMAP3_PUBLIC_SRAM_* to NON_SECURE_SRAM_*
Other TI processors like am33xx, omap4 and omap5 have called these variables
as NON_SECURE_SRAM_*, shouldn't be a big problem rename these variables to
be coherent.
One reason more to rename these variables is to have the possibility of any
OMAP3 board to use the ti_armv7_common.h include as the NON_SECURE_SRAM_END
is used to define the CONFIG_SYS_INIT_SP_ADDR variable.
Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
TI: armv7: Do not define the number DRAM banks if is already defined.
If CONFIG_NR_DRAM_BANKS is not defined, we say (for simplicity) that we have
1 bank, but for some boards should be interesting that we can define
CONFIG_NR_DRAM_BANKS. To handle this possibility just define the number of
DRAM banks if is not already defined. This is useful for some OMAP3 boards
where the DRAM initialitzation is only at u-boot level.
Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
TI: armv7: Move ELM support to SoC configuration file.
The ELM hardware engine wihich is used for ECC error detections is not present
on OMAP3 SoC, so move the CONFIG_SPL_NAND_AM33XX_BCH from ti_armv7_common.h to
SoC configuration file.
Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Jassi Brar [Tue, 7 Aug 2012 09:29:52 +0000 (14:59 +0530)]
ARM: OMAP4/5: Remove dead code against CONFIG_SYS_ENABLE_PADS_ALL
The commit f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls"
removed the config option aimed towards moving that stuff into kernel, which
renders some code unreachable. Remove that code.
Jassi Brar [Tue, 7 Aug 2012 09:29:18 +0000 (14:59 +0530)]
ARM: OMAP4/5: Remove dead code against CONFIG_SYS_CLOCKS_ENABLE_ALL
The commit f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls"
removed the config option aimed towards moving that stuff into kernel, which
renders some code unreachable. Remove that code.
Haijun.Zhang [Fri, 10 Jan 2014 05:52:19 +0000 (13:52 +0800)]
eSDHC: Calculate envaddr accroding to the address format
On BSC9131, BSC9132, P1010 : For High Capacity SD Cards (> 2 GBytes), the
32-bit source address specifies the memory address in block address
format. Block length is fixed to 512 bytes as per the SD High Capacity
specification. So we need to convert the block address format
to byte address format to calculate the envaddr.
If there is no enough space for environment variables or envaddr
is larger than 4GiB, we relocate the envaddr to 0x400. The address
relocated is in the front of the first partition that is assigned
for sdboot only.
Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Reviewed-by: York Sun <yorksun@freescale.com>
Haijun.Zhang [Fri, 10 Jan 2014 05:52:17 +0000 (13:52 +0800)]
esdhc: Workaround for card can't be detected on T4240QDS
Card detection pin is ineffective on T4240QDS Rev1.0.
There are two cards can be connected to board.
1. eMMC card is built-in board, can not be removed. so
For eMMC card it is always there.
2. Card detecting pin is functional for SDHC card in Rev2.0.
This workaround force sdhc driver scan and initialize the card
regardless of whether the card is inserted or not in case Rev1.0.
Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Reviewed-by: York Sun <yorksun@freescale.com>
This patch reverts patch 'add ft_fixup_xgec to support 3rd and 4th 10GEC'.
When dual-role MAC acts as 10G,it still uses fsl,fman-port-1g-rx/tx as before.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
Shengzhou Liu [Mon, 13 Jan 2014 05:01:06 +0000 (13:01 +0800)]
t2080qds/ddr: update ddr parameters
- Optimize UDIMM parameters for whole range from 1500MT/s to 2140MT/s.
- Remove unused patameters: 'cpo', 'wrdata delay', '2T', which are
unrelated to DDR3/3L.
Tested with UDIMM 9JSF25672AZ-2G1K1 and verified speed 1200/1866/2133MT/s.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Po Liu [Fri, 10 Jan 2014 02:10:59 +0000 (10:10 +0800)]
powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
Using the TPL/SPL method to booting from 8k page NAND flash.
- Add 256kB size SRAM tlb for second step booting;
- Add spl.c for TPL image boot;
- Add spl_minimal.c for minimal SPL image;
- Add C29XPCIE_NAND configure;
- Modify C29XPCIE.h for nand config and enviroment;
Signed-off-by: Po Liu <Po.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Po Liu [Fri, 10 Jan 2014 02:10:58 +0000 (10:10 +0800)]
powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL
Using the TPL method for nand boot by sram was already
supported. Here add some code for mpc85xx ifc nand boot.
- For ifc, elbc, esdhc, espi, all need the SPL without
section .resetvec.
- Use a clear function name for nand spl boot.
- Add CONFIG_SPL_DRIVERS_MISC_SUPPORT to compile the fsl_ifc.c
in spl/Makefile;
Signed-off-by: Po Liu <Po.Liu@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
York Sun [Wed, 8 Jan 2014 21:00:42 +0000 (13:00 -0800)]
powerpc/mpc85xx: Revise workaround for DDR-A003
Existing workaround only handles one RDIMM on reference design. In case
of two RDIMMs being used, the workaround requires two separate writes to
DDR_SDRAM_MD_CNTL register.
This patch also restores two debug registers changed by the workaround.
Signed-off-by: York Sun <yorksun@freescale.com> CC: Ben Collins <ben.c@servergy.com> CC: James Yang <James.Yang@freescale.com>
Shengzhou Liu [Fri, 3 Jan 2014 06:48:44 +0000 (14:48 +0800)]
powerpc/t2080qds: some update for t2080qds
- add more serdes protocols support.
- fix some serdes lanes route.
- fix SGMII doesn't work and incorrect mdio display for XFI when serdes 0x6d.
- correct boot location info for SD/SPI boot.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Priyanka Jain [Fri, 3 Jan 2014 05:54:55 +0000 (11:24 +0530)]
powerpc/t1040qds: Update DDR initialization related settings
Update following DDR related settings for T1040QDS
-Correct number of chip selects to two as t1040qds supports
two Chip selects.
-Update board_specific_parameters udimm structure with settings
derived via calibration.
-Reduced I2C speed to 50KHz as DDR-SPD does not get reliably
read at 400KHz.
Verified the updated settings to be working fine with dual-ranked
Micron, MT18KSF51272AZ-1G6 DIMM at data rate 833MT/s, 1333MT/s and
1600MT/s.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
The change to add 64bit initrd support broke 32bit initrd support as it
always set 64bits worth of data into the properties, even on 32bit
systems. The fix is to use addr_cell_len (which already says how much
data is in 'tmp') to set the property, rather than always setting 8.
Thanks to Stephen Warren for pointing out the fix here.
Reported-by: Otavio Salvador <otavio@ossystems.com.br> Signed-off-by: Tom Rini <trini@ti.com>
