Joe Hershberger [Fri, 8 Feb 2013 20:18:53 +0000 (14:18 -0600)]
net: Correct check for link-local target IP conflict
Make the link-local code conform more completely with the RFC.
This will prevent ARP queries for the target (such as while it is
rebooting) from causing the device to choose a different link-local
address, thinking that its address is in use by another machine.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
David Andrey [Wed, 6 Feb 2013 21:18:37 +0000 (22:18 +0100)]
PHY: micrel.c: add support for KSZ9031
Add support for Micrel PHY KSZ9031 in phylib,
including small rework for KSZ9021 to avoid
code duplication
Signed-off-by: David Andrey <david.andrey@netmodule.com> Cc: Troy Kisky <troy.kisky@boundarydevices.com> Cc: Joe Herschberger <joe.hershberger@gmail.com> Cc: Andy Fleming <afleming@freescale.com> Acked-by: Stefan Roese <sr@denx.de>
Shiraz Hashim [Thu, 13 Dec 2012 11:52:52 +0000 (17:22 +0530)]
net/macb: Add arch specific routine to get mdio control
SPEAr310 and SPEAr320 Ethernet interfaces share same MDIO lines to control their
respective phys. Currently there is a fixed configuration in which only a
particular MAC can use the MDIO lines.
Call an arch specific function to take control of specific mdio lines at
runtime.
Matthias Brugger [Tue, 11 Dec 2012 18:14:16 +0000 (19:14 +0100)]
net: nfs: add dynamic wait period
This patch tackles the time out problem which leads to break the
boot process, when loading file over nfs. The patch does two things.
First of all, we just ignore messages that arrive with a rpc_id smaller
then the client id. We just interpret this messages as answers to
formaly timed out messages.
Second, when a time out occurs we double the time to wait, so that we
do not stress the server resending the last message.
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Tested-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Rob Herring [Mon, 3 Dec 2012 03:00:28 +0000 (21:00 -0600)]
pxe: add support for per arch and SoC default paths
A pxelinux server setup for "default" menu is typically an x86 binary.
This does not work well with a mixed architecture setup. Extend the default
search to look for default-<arch>-<soc> and then default-<arch> before
falling back to just "default".
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Rob Herring [Mon, 3 Dec 2012 03:00:27 +0000 (21:00 -0600)]
pxe: add support for ontimeout token
ontimeout is similar to default, but is the selection on menu timeout.
This is how cobbler sets a default. The label default is supposed to be
the default selection when <enter> is pressed. If both default and
ontimeout are set, last one parsed wins.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Rob Herring [Mon, 3 Dec 2012 03:00:26 +0000 (21:00 -0600)]
pxe: simplify menu display and selection
Menus with lots of entries and long append lines are hard to read.
Just show a numbered list using the label or name and make the choice
by entering the number.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Rob Herring [Mon, 3 Dec 2012 03:00:25 +0000 (21:00 -0600)]
pxe: always display a menu when present
The prompt flag is for displaying a "boot:" prompt in pxelinux. This
doesn't make sense for u-boot as we don't support the pxelinux command
interface. So we should just ignore prompt statements and always show the
menu if a menu is present.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Rob Herring [Mon, 3 Dec 2012 03:00:22 +0000 (21:00 -0600)]
pxe: fix handling of different localboot values
Add support for value of -1 For localboot. A value of -1 means return to
u-boot prompt.
The localboot value is often 0, so we need to distinguish the value from
localboot being selected. A value of greater than or equal to 0 means
attempt local boot command.
If localboot is selected, we don't want to try other entries.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Rob Herring [Mon, 3 Dec 2012 03:00:20 +0000 (21:00 -0600)]
pxe: Use ethact setting for pxe
Get the MAC address using eth_getenv_enetaddr_by_index so that the MAC
address of ethact is used. This enables using the a NIC other than the
first one for PXE boot.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Bo Shen [Wed, 24 Apr 2013 02:46:16 +0000 (10:46 +0800)]
checkpatch: add ignore for network block comment style checking
When use checkpatch.pl to check network related patch, it will report
--->8---
WARNING: networking block comments don't use an empty /* line,
use /* Comment...
---<8---
So, add --ignore NETWORKING_BLOCK_COMMENT_STYLE into .checkpatch.conf
This will help to keep all driver include network related driver use
the same comment style
Using the nand erase option "spread", maybe overwrite
blocks on, for example another mtd partition, if the
erasing range contains bad blocks.
So a limit option is added to nand_erase_opts()
Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Scott Wood <scottwood@freescale.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
Gerhard Sittig [Wed, 5 Jun 2013 12:51:11 +0000 (14:51 +0200)]
ac14xx: rephrase network boot config for development
- remove the builtin 'rootpath' spec (according to U-Boot project
policy) and require user provided environments to contain these
- rephrase the evaluation of the 'muster_nr' approach which allows to
quickly switch among several network boot setups (make the setting
transparent when empty, resulting in default DULG behaviour)
- reduce the ARP timeout for faster network boot
Gerhard Sittig [Wed, 5 Jun 2013 12:51:08 +0000 (14:51 +0200)]
ac14xx: re-order the recovery condition checks
re-order the conditions which make the recovery system startup: combine
those conditions which were explicitly initiated (key press, software
request) and those which post-process error conditions (installer issues)
Gerhard Sittig [Wed, 5 Jun 2013 12:51:05 +0000 (14:51 +0200)]
ac14xx: fix a potential NULL deref in diagnostics
getenv() immediately after setenv() may perfectly legally return NULL, so
make sure to not deference an invalid pointer when creating diagnostic output
This patch adds FDT support to the serial s5p driver.
At present disabling the serial console (from the device tree) crashes
U-Boot. Add checks for this case, so that execution can continue without
a serial console.
It also enables the serial_s5p driver recognize the silent_console option.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Some Exynos5250 silicon may require 1.05v on the MIF to be stable, so to be
safe we can default to 1.05v instead of 1.00v. This can be set optimally later
in the boot process by the kernel.
The 0x6 value for 1.05v comes from the MAX77686 datasheet.
Signed-off-by: Bernie Thompson <bhthompson@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Flag status register polling is required for micron 512Mb flash
devices onwards, for performing erase/program operations.
Like polling for WIP(Write-In-Progress) bit in read status register,
spi_flash_cmd_wait_ready will poll for PEC(Program-Erase-Control)
bit in flag status register.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
There is no other call other than spi_flash_cmd_wait_ready(),
hence removed spi_flash_cmd_poll_bit and use the poll status code
spi_flash_cmd_wait_ready() itself.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
sf: Update sf read to support all sizes of flashes
This patch updated the spi_flash read func to support all
sizes of flashes using bank reg addr facility.
The same support has been added in below patch for erase/write
spi_flash functions:
"sf: Support all sizes of flashes using bank addr reg facility"
(sha1: c956f600cbb0943d0afe1004cdb503f4fcd8f415)
With these new updates on sf framework, the flashes which has < 16MB
are not effected as per as performance is concern and but the
u-boot.bin size incrased ~460 bytes.
sf update(for first 16MBytes), Changes before:
U-Boot> sf update 0x1000000 0x0 0x1000000
- N25Q256 16777216 bytes written, 0 bytes skipped in 199.72s, speed 86480 B/s
- W25Q128BV 16777216 bytes written, 0 bytes skipped in 351.739s, speed 48913 B/s
- S25FL256S_64K 16777216 bytes written, 0 bytes skipped in 65.659s, speed 262144 B/s
sf update(for first 16MBytes), Changes before:
U-Boot> sf update 0x1000000 0x0 0x1000000
- N25Q256 16777216 bytes written, 0 bytes skipped in 198.953s, speed 86480 B/s
- W25Q128BV 16777216 bytes written, 0 bytes skipped in 350.90s, speed 49200 B/s
- S25FL256S_64K 16777216 bytes written, 0 bytes skipped in 66.521s, speed 262144 B/s
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Updated the spi_flash framework to handle all sizes of flashes
using bank/extd addr reg facility
The current implementation in spi_flash supports 3-byte address mode
due to this up to 16Mbytes amount of flash is able to access for those
flashes which has an actual size of > 16MB.
As most of the flashes introduces a bank/extd address registers
for accessing the flashes in 16Mbytes of banks if the flash size
is > 16Mbytes, this new scheme will add the bank selection feature
for performing write/erase operations on all flashes.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Read the flash bank addr register to get the state of bank in
a perticular flash. and also bank write happens only when there is
a change in bank selection from user.
bank read only valid for flashes which has > 16Mbytes those are
opearted in 3-byte addr mode, each bank occupies 16Mytes.
Suppose if the flash has 64Mbytes size consists of 4 banks like
bank0, bank1, bank2 and bank3.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Axel Lin [Fri, 14 Jun 2013 13:12:19 +0000 (21:12 +0800)]
spi: cf_qspi: Use DIV_ROUND_UP at appropriate place
This change slightly improves readability.
Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Richard Retanubun <richardretanubun@ruggedcom.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
sf: winbond: Update the names for W25Q 0x40XX ID's flash parts
Use the exact names for W25Q 0x40XX ID's flash parts, as the same
sizes of flashes comes with different ID's. so-that the distinguishes
becomes easy with this change.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
sf: spansion: Correct name of S25FL128S 64K Sector part
Corrected the name of S25FL128S 64K sector part SPI flash,
S25FL128S supported has been added in below commit
"sf: spansion: Add support for S25FL128S"
(sha1: 1bfb9f156aa66cca6bb9c773867a1f02a84b14be)
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Mike Dunn [Fri, 21 Jun 2013 16:12:28 +0000 (09:12 -0700)]
pxa: fix memory coherency problem after relocation
On the xscale, the icache must be invalidated and the write buffers drained
after writing code over the data bus, even if the caches are disabled. Tested
on the pxa270.
Mike Dunn [Mon, 17 Jun 2013 17:47:28 +0000 (10:47 -0700)]
pxa: turn icache off in cpu_init_crit()
The comment in the low-level initialization function cpu_init_crit() says that
the caches are being disabled, but (oddly) the icache is actually turned on.
This is probably not a good idea prior to relocating code, so this patch turns
it off. Tested on the pxa270.
Mike Dunn [Tue, 18 Jun 2013 18:08:51 +0000 (11:08 -0700)]
pxa: palmtreo680 flash programming utility
This adds a userspace linux utility that writes the u-boot image to an mtd
partition on the docg4 nand flash.
A special utility is required to do this because u-boot is partially loaded by
an initial program loader (IPL) that is permanently programmed to the boot
region of the flash. This IPL expects the image to be written in a unique
format. The characteristics of this format can be summarized as follows:
- Flash blocks to be loaded must have a magic number in the oob bytes of the
first page of the block.
- Each page must be written redundantly in the subsequent page.
- The integrated flash controller's "reliable mode" is used, requiring that
alternate 2k regions (4 pages) are skipped when writing.
For these reasons, a u-boot image can not be written using nandwrite from
mtd-utils.
Mike Dunn [Tue, 18 Jun 2013 18:08:50 +0000 (11:08 -0700)]
pxa: add support for palmtreo680 board
This patch adds support for the Palm Treo 680 smartphone. A quick overview of
u-boot implementation on the treo 680...
The treo 680 has a Diskonchip G4 nand flash chip. This device has a 2k region
that maps to the system bus at the reset vector in a NOR-like fashion so that it
can be used as the boot device. The phone is shipped with this 2k region
configured as write-protected (can't be modified) and programmed with an initial
program loader (IPL). At power-up, this IPL loads the contents of two flash
blocks to SDRAM and jumps to it. The capacity of the two blocks is not large
enough to hold all of u-boot, so a u-boot SPL is used. To conserve flash space,
these two blocks and the necessary number of subsequent blocks are programmed
with a concatenated spl + u-boot image. That way, the IPL will also load a
portion of u-boot proper, and when the spl runs, it relocates the portion of
u-boot that the IPL has already loaded, and then resumes loading the remaining
part of u-boot before jumping to it.
The default_environment is used (CONFIG_ENV_IS_NOWHERE) because I didn't think
that having a writable environment was worth the cost of a flash block, although
adding it would be straightforward. I abuse the CONFIG_EXTRA_ENV_SETTINGS
option to specify the usbtty for the console (CONFIG_SYS_CONSOLE_IS_IN_ENV).
Support for the LCD is included, but currently it is only useful for displaying
the u-boot splash screen. But if u-boot is built without the usbtty console, it
does display the auto-boot progress nicely.
Albert ARIBAUD [Tue, 11 Jun 2013 12:17:32 +0000 (14:17 +0200)]
arm: generalize lib/bss.c into lib/sections.c
File arch/arm/lib/bss.c was initially defined for BSS only,
but is now going to also contain definitions for other
section-boundary-related symbols, so rename it for better
accuracy.
Albert ARIBAUD [Tue, 11 Jun 2013 12:17:31 +0000 (14:17 +0200)]
remove all references to .dynsym
Discard all .dynsym sections from linker scripts
Remove all __dynsym_start definitions from linker scripts
Remove all __dynsym_start references from the codebase
Note: this touches include/asm-generic/sections.h, which
is not ARM-specific, but actual uses of __dynsym_start
are only in ARM, so this patch can safely go through
the ARM repository.
Scott Wood [Thu, 20 Jun 2013 17:45:31 +0000 (12:45 -0500)]
nand: Don't call adjust_size_for_badblocks for erase
adjust_size_for_badblocks reduces the operation size to account
for the block skipping done by the read/write functions when an
interval (partition name or whole chip) is specified rather than a data
amount.
Erase does not do block skipping, except for erase.spread which takes
a data amount rather than an interval (and thus already does not call
adjust_size_for_badblocks). Calling adjust_size_for_badblocks when
block skipping is not done means that if bad blocks are present,
the "nand erase.part" and "nand erase.chip" commands will fail to erase
blocks at the end of the interval.
Even though this part of code was missing, things were working
fine on Exynos5250 because, samsung_get_base_fimd() used
to give the correct base address for Exynos5250 FIMD.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Chris Packham [Sun, 26 May 2013 22:51:46 +0000 (10:51 +1200)]
powerpc/CoreNet: Allow pbl images to take u-boot images != 512K
Instead of assuming that SYS_TEXT_BASE is 0xFFF80000 calculate the initial
pbl command offset by subtracting the image size from the top of the
24-bit address range. Also increase the size of the memory buffer to
accommodate a larger output image.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Andy Fleming <afleming@freescale.com>
Ying Zhang [Mon, 20 May 2013 06:07:26 +0000 (14:07 +0800)]
Makefile: move the common makefile line to public area
Move the common makefile line shared by the SPL and non-SPL to the public area,
so that we can avoid excessive SPL symbols. Some of them will be used by the
SPL later.
This patch is on top of the patch "common/Makefile: Add new symbol
CONFIG_SPL_ENV_SUPPORT for environment in SPL".
Signed-off-by: Ying Zhang <b40530@freescale.com> Acked-by: Tom Rini <trini@ti.com> Acked-by: Tom Rini <trini@ti.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Ying Zhang [Fri, 7 Jun 2013 09:25:16 +0000 (17:25 +0800)]
powerpc/mpc85xx: modify the functionality clear_bss and aligning the end address of the BSS
There will clear the BSS in the function clear_bss(), the reset address of
the BSS started from the __bss_start, and increased by four-byte increments,
finally stoped depending on the address is equal to the _bss_end. If the end
address __bss_end is not alignment to 4byte, it will be an infinite loop.
1. The reset action stoped depending on the reset address is greater
than or equal the end address of the BSS.
2. The end address of the BSS should be 4byte aligned. Because the reset unit
is 4 Bytes.
This patch is on top of the patch "powerpc/mpc85xx: support application
without resetvec segment in the linker script".
Signed-off-by: Ying Zhang <b40530@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Ying Zhang [Mon, 20 May 2013 06:07:23 +0000 (14:07 +0800)]
powerpc/mpc85xx: support application without resetvec segment in the linker script
For SD/SPI 2-stage bootloader, the On-Chip Rom code loads the SPL into L2 SRAM,
then jump to it to begin execution. After that, the SPL loads the final uboot
image into DDR, then jump to it to begin execution. The segment .resetvec in
the SPL and in final U-boot is useless.
So, add new symbols CONFIG_SYS_MPC85XX_NO_RESETVEC for this application.
If CONFIG_SYS_MPC85XX_NO_RESETVEC is set, the segment .resetvec is excluded
and the segment .bootpg is placed in the previous 4K of the segment .text.
Signed-off-by: Ying Zhang <b40530@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Scott Wood [Wed, 15 May 2013 22:50:13 +0000 (17:50 -0500)]
powerpc/mpc85xx: work around erratum A-006593
Erratum A-006593 is "Atomic store may report failure but still allow
the store data to be visible".
The workaround is: "Set CoreNet Platform Cache register CPCHDBCR0 bit
21 to 1'b1. This may have a small impact on synthetic write bandwidth
benchmarks but should have a negligible impact on real code."
Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Mingkai Hu [Thu, 16 May 2013 02:18:13 +0000 (10:18 +0800)]
fsl_ifc: add support for different IFC bank count
Calculate reserved fields according to IFC bank count
1. Move csor_ext register behind csor register and fix res offset
2. Move ifc bank count to config_mpc85xx.h to support 8 bank count
3. Guard fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate the compile
error on some devices that does not have IFC controller.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Liu Gang [Tue, 7 May 2013 08:30:50 +0000 (16:30 +0800)]
powerpc/t4qds: Slave module for boot from SRIO and PCIE
When a T4 board boots from SRIO or PCIE, it needs to finish these processes:
1. Set all the cores in holdoff status.
2. Set the boot location to one PCIE or SRIO interface by RCW.
3. Set a specific TLB entry for the boot process.
4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
5. Set a specific TLB entry in order to fetch ucode and ENV from
master.
6. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
7. Slave's u-boot image should be generated specifically by
make xxxx_SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
For more information about the feature of Boot from SRIO/PCIE, please
refer to the document doc/README.srio-pcie-boot-corenet.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Liu Gang [Tue, 7 May 2013 08:30:49 +0000 (16:30 +0800)]
powerpc/t4qds: Enable master module for Boot from SRIO and PCIE
T4 can support the feature of Boot from SRIO/PCIE, and the macro
"CONFIG_SRIO_PCIE_BOOT_MASTER" will enable the master module of this feature
when building the u-boot image.
You can get some description about this macro in README file, and for more
information about the feature of Boot from SRIO/PCIE, please refer to the
document doc/README.srio-pcie-boot-corenet.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Liu Gang [Tue, 7 May 2013 08:30:48 +0000 (16:30 +0800)]
powerpc/b4860qds: Slave module for boot from SRIO and PCIE
When a b4860qds board boots from SRIO or PCIE, it needs to finish these
processes:
1. Set all the cores in holdoff status.
2. Set the boot location to one PCIE or SRIO interface by RCW.
3. Set a specific TLB entry for the boot process.
4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
5. Set a specific TLB entry in order to fetch ucode and ENV from
master.
6. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
7. Slave's u-boot image should be generated specifically by
make xxxx_SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
For more information about the feature of Boot from SRIO/PCIE, please
refer to the document doc/README.srio-pcie-boot-corenet.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Liu Gang [Tue, 7 May 2013 08:30:47 +0000 (16:30 +0800)]
powerpc/b4860qds: Enable master module for boot from SRIO and PCIE
B4860QDS can support the feature of Boot from SRIO/PCIE, and the macro
"CONFIG_SRIO_PCIE_BOOT_MASTER" will enable the master module of this feature
when building the u-boot image.
You can get some description about this macro in README file, and for more
information about the feature of Boot from SRIO/PCIE, please refer to the
document doc/README.srio-pcie-boot-corenet.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Liu Gang [Tue, 7 May 2013 08:30:46 +0000 (16:30 +0800)]
powerpc/boot: Change the macro of Boot from SRIO and PCIE master module
Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable
the master module of Boot from SRIO and PCIE on a platform. But this
is not a silicon feature, it's just a specific booting mode based on
the SRIO and PCIE interfaces. So it's inappropriate to put the macro
into the file arch/powerpc/include/asm/config_mpc85xx.h.
Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to
"CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from
arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros
in configuration header file of each board which can support the
master module of Boot from SRIO and PCIE.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
