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(parent: 894f1d5) | patch
qemu: change TLBs number to 64 in 34Kf mips cpu model
authorVictor Kamensky <kamensky@cisco.com>
Mon, 19 Oct 2020 22:21:46 +0000 (15:21 -0700)
committerRichard Purdie <richard.purdie@linuxfoundation.org>
Tue, 20 Oct 2020 10:11:41 +0000 (11:11 +0100)
commita99dace7463d310688f4098a51316dc0743651e2
tree9e4cd2f981d98bbd2c9e65be0e4a7699b2bd923etree | snapshot
parent894f1d58d93073d290f35d1090b03717bc7b4dc0commit | diff
qemu: change TLBs number to 64 in 34Kf mips cpu model

Replace OE private qemu patch with one that got upstreamed
and solves the same problem: increase qemumips CI performance
by increasing number of TLBs in CPU model and reduce need to
run software TLB refill code.

Signed-off-by: Victor Kamensky <kamensky@cisco.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
meta/recipes-devtools/qemu/qemu.inc diff | blob | history
meta/recipes-devtools/qemu/qemu/0001-target-mips-Increase-number-of-TLB-entries-on-the-34.patch [new file with mode: 0644] blob
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