From d6ed1be86352edd4ff72b2ada5f0557e8436c1ae Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Tue, 2 Jul 2013 11:52:51 -0300 Subject: [PATCH] perf: Disable FPU tune for i.MX5 SoCs to workaround GCC ICE GCC 4.8 currently ICE when building perf for i.MX5 SoCs and we can workaround it disabling the FPU tunning for it. This is a temporary solution until GCC fixes this in an upcoming release. GCC bugzilla: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57748 Change-Id: I5a23e6b57695a90e9750f0fa28c419b260c83be2 Signed-off-by: Otavio Salvador --- meta-fsl-arm/recipes-kernel/perf/perf.bbappend | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 meta-fsl-arm/recipes-kernel/perf/perf.bbappend diff --git a/meta-fsl-arm/recipes-kernel/perf/perf.bbappend b/meta-fsl-arm/recipes-kernel/perf/perf.bbappend new file mode 100644 index 00000000..604e2b43 --- /dev/null +++ b/meta-fsl-arm/recipes-kernel/perf/perf.bbappend @@ -0,0 +1,3 @@ +# FIXME: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57748 +TUNE_CCARGS_mx5 := "${@oe_filter_out('-mfpu=neon', '${TUNE_CCARGS}', d)}" + -- 2.40.1